Features

• Battery Monitor with Two Threshold Voltages: 1.6 V and 1.75 V

• System Reset and Shut Down Internally Provoked or Requested by an External Device
• Fully Asynchronous State Machine Performing Overall Power Management Control
• Low Consumption for Permanent Battery Monitoring ICC, typ µA100 at AVDD! = 3.1 V
• Applications
– Power Management Units (PMU) in Cordless/Wireless Phones
• Cell Dimensions (Periphery Block)
– X Length: 400 µm
– Y Height: 439 µm
Embedded ASIC
Description
Macrocell:
SOR01 is an analog cell featuring a battery monitor function and an asynchronous
finite state machine providing system power control, system reset, and system Wireless
shut-down signals. The battery monitor function is made of a window comparator,
thresholds VTH160 = 1.6 V and VTH175 = 1.75 V respectively, that controls shut-down and Baseband
power-up states of the finite state machine. System shut down or reset can be digitally
controlled by means of two inputs (ucpwrdwn, ucreset). Figure 3 on page 4 shows a
simplified state diagram of the power control unit.
SOR01 System
(1)
Figure 1. Verilog Symbol
Reset, Battery
Monitor and
Power Control

Note: 1. Pin names are written as they appear on the user screen when the symbol is
opened in the design environment.

2757A–CASIC–24-Sep-03
Pin Description
Table 1. Pin Function Description
Pin/Pad Name Pin/Pad I/O Type Function
avdd! pin I analog Power supply of SOR01. Regulated version of the battery voltage. Typical value is
avdd! = 3.1 V.
agnd! pin I/O analog Analog ground.
vdd! pin I/O analog digital supply.
gnd! pin I/O analog digital ground.
vthr pad O analog Attenuated by two-battery voltage used for battery monitoring. Voltage comes from a
resistive divider connected to the battery. When the battery is at mean voltage
VBAT = 3.5 V, vthr = 1.75 V, the resistive divider must be 0.5% accurate.
vthrint pin O analog Internal output pin connected to vthr when onreg = 1. HI-Z mode when onreg = 0 to
prevent any analog blocks receiving vthrint from sourcing/sinking current when power
supply is off.
vth160 pin I analog Input reference voltage vth160 = 1.6 V ± 1%.
vth175 pin I analog Input reference voltage vth175 =1.75 V ± 20%.
capout pad O analog External analog pad connected to the grounded capacitor that generates the reset delay.
onext pad I digital External grounded switch input with internal pull up used to escape the power-down
state.
ucreset pin I digital Reset input control from MCU. See the SOR01 state diagram in Figure 3 on page 4 for
more details. This pin is inactive when onreg = 0.
ucpwrdwn pin I digital Power down input control from MCU. See the SOR01 state diagram in Figure 3 on page
4 for more details. This pin is inactive when onreg = 0.
onreg pin O digital Output controlling the activation of the voltage regulators. Onreg = 1 corresponds to a
reset or operational state, onreg = 0 corresponds to a power-down/shut-down state.
resetn pin O digital System reset output, active low. When the system goes from reset to operational, resetn
goes high during a time delay after rising of onreg to accommodate the startup time of
voltage regulators.

2 SOR01
2757A–CASIC–24-Sep-03
 SOR01

Block Diagram
Figure 2. Block Diagram

avdd! agnd!
avdd!
vth175
+
comp onreg
-
agnd!
Asynchronous avdd! avdd! vdd!
vthr Finite State Machine 2.5 V
-
resetn
Comp Shifter
capout
avdd! +

+ agnd! agnd! gnd!

vth160 Comp
-
agnd!
avdd!
avdd!
100k

onext

ctrl_rst

vdd! avdd! capout

ucreset
Shifter

gnd! agnd!
agnd!
vdd! avdd! vthrint
vthr
ucpwrdwn
Shifter

gnd! agnd!
avdd! agnd! vdd! gnd

Product Overview

Behavior of the Finite When the comparator detects that VBAT (=2 x VTH) is higher than 3.5 V, the machine
State Machine exits the shut-down mode. It turns the analog functions on (onreg = 1), and releases the
digital system reset after a delay corresponding to the charging time of the external
capacitor, (allows the voltage references to stabilize). Once resetn is high, the system
becomes operational. The processor can then ask the machine to reset the digital core
(ucreset = 1), or to enter the power-down mode (ucpwrdwn = 1) if necessary. In the lat-
ter case, both the regulators and the digital core are switched off. The system will exit its
power-down mode only on a high to low transition of onext, or if the battery goes below
3.2 V, causing the system to enter the shut-down mode.

3
2757A–CASIC–24-Sep-03
State Diagram Figure 3. State Diagram of the Asynchronous Sequential Machine

SHUTDOWN VBAT <3.2 V (2%) POWERDOWN

onreg = 0 onreg = 0
resetn = 0 resetn = 0

VBAT >3.5 V (2%) onext = 0

VBAT <3.2 V (2%) RESET

onreg = 1
resetn = 0

Processor
Delay
Watchdog

VBAT <3.2 V (2%) OPERATIONAL Processor Powerdown

onreg = 1
resetn = 1

4 SOR01
2757A–CASIC–24-Sep-03
 SOR01

Electrical Specifications
Table 2. Electrical Specifications (Power Supply avdd! = 3.1 V typ, 2.8 V min, 3.6 V max, Temperature -40° C to +85° C)
Parameters Conditions Min Typ Max Units
General information
avdd! 2.8 3.1 3.6 V
vdd! 1.65 1.8 1.95 V
Total current consumption (avdd!, agnd!) avdd! = 3.1 V, the cell is not charging the 60 100 170 µA
external capacitor
Total current consumption (avdd!, agnd!) avdd! = 3.1 V, the cell is charging the 70 120 200 µA
external capacitor
Peak current at startup (avdd!, agnd!) avdd! = 3.1 V - - 3 mA
Total current consumption (vdd!, gnd!) vdd! = 1.8 V - - 1 µA
Start-up delay time once avdd! = 2.8 V - - 500 µs
onreg high logic level - avdd! - V
resetn high logic level - vdd! - V
onext internal pull-up 100 - - kΩ
onext, high logic level leakage < 10 µA avdd x 0.8 - - V
onext, low logic level leakage < 10 µA - - avdd x 0.2 V
Battery Monitoring Function
Comparator input offset voltage - 5 25 mV
Input impedance vthr, vth175, vth160 5 - - MΩ
Delayed Reset Function
Output current reference (capout pin) 12 22 35 µA
v250, comparator threshold voltage 2.45 2.5 2.55 V
vcapout, max - avdd! - V
ron, internal resistance of the switch used to avdd! = 3.1 V 120 140 160 Ω
discharge the external capacitor
Peak current when discharging the external avdd! = 3.1 V - - 150 mA
capacitor
tdischarge, vthr < 1.6 V to resetn = 0 & onreg C = 47 nF - - 30 µs
= 0 (discharge of the external capacitor)
tcharge, onreg = 1 to resetn = 1 delay time C = 47 nF 3.8 5.3 10 ms
(charge of the external capacitor)

5
2757A–CASIC–24-Sep-03
Typical Application
Figure 4.

3.1 V 3.1 V LDO 3.2 V ... 5.2 V

Regulator

3 x 1.2 V
NIMH Cells
VLMT

AVSS3

RSTN

ON

VTHR

vth175
vth175 onreg
vthr Asynch.
avddd! vth160 F.SM.
vrefp vthr160 resetn
agnd!
vbg
ucpwrdwn capout
vrefn
ucreset
vthrint Battery
onext Monitoring
dcal[3:0] BG015 SOR01
SOR01 is supplied by BG015 (avdd! implicit connection)

MCU

6 SOR01
2757A–CASIC–24-Sep-03
 SOR01

Testability Guidelines
To test SOR01, one must verify that the internal Finite State Machine (F.S.M) can transi-
tion through all the states as described in Figure 3 on page 4. The only way to verify this,
is to apply signals on the inputs and to check the values of the outputs.
Notes: 1. vdd! and gnd! are considered here as input pins since the digital regulator is
controlled by SOR01 (i.e. vdd! = 0 V if onreg = 0, and once onreg = 1 then
vdd! ramps up to 1.8 V).
2. refer to Table 1, “Pin Function Description,” on page 2 for input and output
pin definitions.

Recommended Test The recommended test sequence is described in Table 3 below.

Sequence
Table 3. Recommended Test Sequence
Step Operation Description resetn onreg
1 apply avdd! = 3.1V F.S.M in shut-down mode. 0 0
apply vth160 = 1.6V
apply vth175 = 1.75V
apply vthr < 1.75 V (1)
2 apply vthr > 1.75 V F.S.M exits the shut-down state. 0 1
3.a force capout = 0 V and measure current flowing F.S.M in reset state tries to charge the external 0 1
from capout (2) capacitor.
3.b apply vdd! = 1.8 V Simulate start-up of digital regulators. 0 1
3.c apply capout > 2.5 V Simulate external capacitor end of charge. The 1 1
system enters the operational state
4 apply ucreset positive pulse (3) Simulate reset request from MCU. 1 1
5.a idem 3.a
5.b idem 3.b
5.c idem 3.c
6 apply ucpwrdwn positive pulse (3) Simulate power-down request from MCU. 1 0
7 ground onext input Simulate user requested escape of the 1 0
power-down state.
8.a idem 3.a
8.b idem 3.b
8.c idem 3.c
9 apply vthr < 1.6V Simulates battery discharge, FSM exits power- 0 0
down mode and enters shut-down mode.
Notes: 1. This step must last at least the startup delay time specified in “Electrical Specifications” Table 2 on page 5. Any other step
must last at least 50 µs.
2. capout sources a current from avdd to agnd which value is about 20 µA (see “Electrical Specifications” Table 2 on page 5).
3. typical pulse: trise = 10 ns, tfall = 10 ns, thigh = 1 µs.

7
2757A–CASIC–24-Sep-03
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2757A–CASIC–24-Sep-03