COMP60062 System Level Design

Appendix B: ARM Assembly Language Mnemonics and Directives

Most examples of the assembler that you need to write can be found in test.s in the TLM direc-
tory. However there are many other instructions and this appendix lists some commonly used
instructions as a quick reference guide; it is not a fully comprehensive list. ARM instructions
conditionally execute according to the “cc” code specified (see the table later). “cc” in the in-
structions shows the position of the condition code if any. For most instructions, the “cc” code
is omitted so the instruction always executes. Instructions are 32 bits long

Data Processing
Adding S to the end of any of the mnemonics causes the status register (officially referred to as
the Current Processor Status Register CPSR) to be updated according to the result from the
Arithmetic & Logic Unit (ALU). The bits set in the status register are used as the “cc” code to
determine if data operations are to be executed and in conditional branch instructions to deter-
mine if a branch is taken. The four bits in the status register that are used to determine conditions
are: the zero bit Z (the result of the arithmetic operation was all zeros), the sign bit N (N=’1’
means the ALU result is negative, N=’0’ indicates a positive or zero result), the carry bit C (C=1
indicates the carry bit out of the most significant ALU bit is ‘1’, C=’0’ means the carry bit out
of the most significant ALU bit is ‘0’), and an overflow bit V (V=’1’ means that two positive
quantities have added to yield a negative result, or two negative quantities have added to give a
positive result. V=’0’ indicates the operation performed is in range).

There are 15 general purpose registers, R0 to R14, that you can use in your code; R15 contains
the Program Counter and should not be manipulated by you! The CPSR is another, separate
register held within the microprocessor.

A semicolon ‘;’ indicates a comment to the end of the line.

ADDccS Rd, Rn, Rm/#nn ;Rd=Rn+Rm/#nn, set status

ADCcc Rd, Rn, Rm/#nn ;add with carry C
SUBcc Rd, Rn, Rm/#nn ;subtract Rd=Rn-Rm/#nn
SBCcc Rd, Rn, Rm/#nn ;subtract with borrow
;Rd=Rn-Rm/#nn+C-1
RSBccS Rd, Rn, Rm/#nn ;reverse minus, set status
;Rd=Rm/#nn-Rn
RSCcc Rd, Rn, Rm/#nn ;reverse minus with borrow
;Rd=Rm/#nn-Rn+C-1
ANDcc Rd, Rn, Rm/#nn ;Rd=Rn AND Rm/#nn
ORRcc Rd, Rn, Rm/#nn ;OR operation
EORcc Rd, Rn, Rm/#nn ;XOR
BICcc Rd, Rn, Rm/#nn ;bit clear, Rd=Rn &Rm/#nn

MOVcc Rd, Rm/#nn ;move Rm/#nn to Rd

MVNcc Rd, Rm/#nn ;move Rm/#nn to Rd

CMPcc Rn, Rm/#nn ;set status on Rn-Rm/#nn

CMNcc Rn, Rm/#nn ;set status on Rn+Rm/#nn
TSTcc Rn, Rm/#nn ;set status on Rn AND Rm/#nn

AppendixB.29
 TEQcc Rn, Rm/#nn ;set status on Rn XOR Rm/#nn
If the second source operand is a register (Rm), it can be shifted (see later).

MULcc Rd, Rm, Rs ;Rd=Rm*Rs

MLAcc Rd, Rm, Rs, Rn ;Rd=Rm*Rs+Rn
For multiplication orders (MULcc and MLAcc), adding S to set the status register results in only
the zero and sign bits being updated. The carry is undefined and overflow is unaffected by the
order. Note that the multiplication of the two 32-bit integer quantities gives a single length 32-
bit result in Rd (being the least significant 32-bits of the result).

In data processing instructions, the literal value, #nn, is restricted. Bits set to 1 need to span a
maximum of eight bits anywhere within the 32 bits. Thus 0x11C (=228) is ok as a literal as is
0x002E4000 but 0x103 is invalid. In test.s, loading 0x103 into register R1 is performed by two
instructions (move followed by add). An alternative is to do a LDR instruction (see Assembler
Supplied ‘Pseudo Operations’ later).

Shifting
If the data processing operation specifies the second operand as a register (Rm) then this can be
optionally shifted by a shift amount specified as a literal #c or by the amount specified in the
borrom eight bits of a register Rc. The shift on Rm is performed prior to combining it with the
first source operand Rn, and the contents of register Rm are unaffected by the shift operation.
You will notice that there is no arithmetic shift left; this is because it is equivalent to a logical
shift left. Shifting is useful in scaling variables. For example, multiplying by two yields a far
better performance if the variable is logically shifted left one place. Similarly scaling a number
by dividing by two can be achieved by an arithmetic shift right of one place. The shifts are:

LSL #c ;logical shift left #c places

LSL Rc ;logical shift left by places in Rc
;LSL shift range is 0 to 31 with ‘0’s
;shifted into least significant end

LSR #c ;logical shift right by #c places

LSR Rc ;logical shift right by places in Rc
;logical shift right by 0 to 32
;places with ‘0’s inserted at most
;significant end

ASR #c ;arithmetic shift right by #c places

ASR Rc ;arithmetic shift right by places in Rc
;arithmetic shift right 0 to 32
;places with the sign bit (i.e.
;the most significant bit) copied
;into the most significant end

ROR #c ;circular rotate right by #c places

ROR Rc ;circular rotate right by places in Rc
;bits from least signficant end feed
;into the most significant end,
;shift range is 0 to 32

AppendixB.30
 RRX ;one place right shift. Carry from
;status reg shifts into most signif-
;icant bit and if status reg set by
;instruction, least signicant bit
;updates carry bit in status regis-
;ter. This enables a 1-bit circular
;rotate through the carry
The shift required on Rm is specified as the fourth parameter in the instruction e.g.
add r1, r4, r5, LSL #3
This results in r1 being set to r4+8*r5

Loads and Stores

LDRcc Rd, [Rn] ;loads a 32-bit word

;into Rd from memory
;address given by Rn
;contents
LDRccH Rd, [Rn, Rm/#nn] ;loads a half word into
;Rd from addr Rn+Rm/#nn
;with most significant 16
;bits in Rd set to zero

LDRccB Rd, [Rn, Rm/#nn] ;loads 8-bits into Rd

;top 24 bits are ‘0’s

STRcc Rd, [Rn] ;stores Rd in memory

;at addr in Rn
STRcc Rd, [Rn, Rm/#nn] ;stores Rd in Rn+Rm/#nn
STRccH Rd, [Rn,Rm/#nn] ;stores 16 ls bits of Rd
STRccB Rd, [Rn,Rm/#nn] ;stores ls byte of Rd

LDMccFD Rd, {register list} ;multiple reg load,

;load from addr Rd
STMccFD Rd!, {register list};multiple reg store,
;Rd is updated after
;each store operation
Notes: You will not need to use the load multiple and store multiple orders. Also, be aware that
there are various addressing modes to assist with the updating of addresses if loading/storing
arrays; these have been omitted in the interests of simplicity. The word, halfword and byte load/
store transfers above are the only orders you will require.

Control Transfer

Bcc Label ;conditional branch to label

BLcc Procedure_start ;conditional branch and link
SWIcc Number ;software interrupt

AppendixB.31
Special Control Operations

MRScc Rd, CPSR ;Rd=status register

MRScc Rd, SPSR ;Rd=saved status register
MSRcc CPSR_f, #nn ;sets flags in status reg
MSRcc SPSR_c, Rm ;sets mode in saved status reg
The MRS and MSR are used to read and write the Current Program Status Register (CPSR) and
the Saved Program Status Register (SPSR). These orders are commonly used to change proces-
sor mode and to enable/disable interrupts, when the core is in a privileged mode (i.e. not User
mode). You will not need to use these instructions.

Assembler Supplied ‘Pseudo Operations’

NOP ; no operation
MOV Rd, #-nn ; assembles to MVN
CMP Rn, #-nn ; assembles to CMN

ADR Rd, label ;Rd=label address. This instr is

;replaced by add Rd, R15,#nn with usual
;restriction on #nn value applying

ADRL Rd, label

;Rd=label address- used when
;#nn in ADR is out of range
LDR Rd, =nnnnnnnn ; Load constant
Note: the last operation (LDR) places the constant (nnnnnnnn)
somewhere ‘convenient’ in memory (probably at the end of the
code) and plants an instruction which loads this value. The
pseudo-operation therefore generates two words (one for the
load instruction and a memory loaction for the data constant);
these are unlikely to be adjacent in the memory map. If the con-
stant is ‘short’ enough, the assembler will substitute a (sin-
gle) MOV instruction.

Directives

Directive mnemonics are case insensitive.

ORG &<address> ;Set address of

;code following
ALIGN ;to next 4-byte boundary
ALIGN N ;to next N-byte boundary

DEFB 0, 2, “bytes” ;byte(s) follow DEFB

DEFH &ABCD, 2+2 ;halfword(s) follow DEFH
DEFW &12345678 ; Define word(s)
DEFB, DEFH and DEFW allow data to be planted amongst the
instructions in a program.

label EQU value ; Set value of “Label”

AppendixB.32
 DEFS &<number e.g. 20> ;Reserves 20 bytes
;at this point

INCLUDE <filename> ; What it says!

Condition Codes

cc Meaning Flag condition

EQ Equal Z

NE Not Equal Z

CS/HS Carry Set/Higher or Same (unsigned) C

CC/LO Carry Clear/Lower (unsigned) C

MI Minus (negative) N

PL Plus (positive) N

VS Overflow Set V

VC Overflow Clear V

HI Higher (unsigned) C.Z

LS Lower or Same (unsigned) C+Z

GE Greater than or Equal (signed) N⊕V

LT Less Than (signed) N⊕V

GT Greater Than (signed) (N ⊕ V) . Z

LE Less than or Equal (signed) (N ⊕ V) + Z

AL Always TRUE

Operators in Expressions

It is possible, and often valuable, to allow the assembler to work out some values (such as the
length of strings and tables). Thus instead of a simple number, an integer expression can be
used. The following is a summary of the most useful ones.

Unary operators:
+, -, ~

Binary operators, highest precedence first:

Logical shifts: { << LSL SHL } { >> LSR SHR }
Logical AND: AND
Logical ORs: { | OR } { ^ EOR }
Multiply/Divide: * { / DIV } { \ MOD }
Add/Subtract: + -
The operators within braces {} give valid alternatives for expressing the operation. Thus a log-
ical shift left in an expression can be specified by <<, by LSL, or by SHL.

AppendixB.33
Numbers

Numeric constants default to decimal (base 10).

Hexadecimal numbers should be prefixed with “&”, “$”, or “0x”.
Binary numbers should be prefixed with “:” or “0b”
Octal numbers -if you really want these - should be prefixed with “@”

AppendixB.34