CMOS Technology: Present and Future
Bijan Davari
Semiconductor and Research Development Center (SRDC)
IBM Microelectronics Division, Hopewell Junction, NY 12533
A3STRACT
Presently, we are going through an exciting phase of the
semiconductor industry, as the miniaturization of the
dimensions is accelerated and at the same time some of the
fundamental limits of device scaling, as well as optical
lithography, are rapidly drawing near. h this paper, the
impact of these limits on the future development of CMOS
technology are examined and some of the advanced device,
interconnect, and functional integration techniques to further
extend technology scaling are discussed. Beyond these
advances, the spectacular success that the semiconductor
industry has had can only continue by increasing the silicon
chip fictional integratio~ once the device performance and
miniaturization starts to saturate. The success of this phase
of the semiconductor business relies heavily on circuit and
architectural innovations, aided by embedded technologies.
The cost of the integrated system on a chip should remain
significantly below the price of the system that it intends to
replace in addition to delivering added performance.
INTRODUCTION
Traditional CMOS scaling relies on the miniaturization of
the device, isolation, interconnect dimensions, and
optimized, reduce& supply-voltage to achieve higher
performance and density and simultaneously contain the
escalating power-density and maintain adequate reliability
margins [1]. Problems arise when non-scalable parameters
such as the device threshold voltage (VT) and intercomect
RC delay result in performance saturation [1,2], and optical
lithography extendibility issues slow down the pace of the
dimensional shrink [3]. The mandatory reduction of the
supply-voltage also results in issues such as the reduced
effectiveness of burn-in and screen techniques, and
worsening of the soft error rate (SER). It is shown that by
exploiting new materials and processes such as copper
interconnects [4] and Silicon On Insulator (S01, [5]) the
scaling path can be further extended.
However, it will be argued that, even after using the above
technologies and before the year 2005, the FET device
performance gain saturates as the minimum effective channel
length m) approaches 0.03wm (nominal effeixive
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channel length of about 0.04pm) @ 1.OV supply voltage
and the gate oxide thickness of about 1.5nm [6]. This
corresponds to a gate lithography of 0.071.uniandthe 0.1pm
technology generation. On the DRAM side, the 4X increase
in the number of bits per chip every three years will slow
down as the transition from the folded bit line architecture (8
lithography squares) to a much less noise immune, open bit
line structure (4 lithography squares) becomes necessary.
Beyond this point, the performance growth of silicon chips
should continue by increasing functional integration, made
possible by technologies such as, embedded nonvolatile
memory, embedded DRAM [7], mixed signal, etc., with
heavy reliance on circuit and architectural inncwations.
CMOS TECHNOLOGY TODAY:
NEARING THE LIMITS!
Device Scaling: For high-performance, digital CMOS
applications, the supply-voltage transition from 3.3V to 2.5V
took about 5 years from the early 1990’s to 1995 due to the
reluctance to depart from standardized voltage levels [1].
After this transitio% the pace of supply-voltage (VDD)
reduction was accelerated significantly as reflected in the
revised National Technology Roadmap for Semiconductors
(NTRS) released in 1997 [8]. The primary mason has been
to achieve maximum device performance at a given
lithography generation while maintaining aclequate device
reliability, and containing switching power (C VDD2F) [2].
The transitions from 2.5V to 1.8V to 1.5V supply-voltages
for 0,35pnL 0.25~m and O.18ym CMOS generations,
respectively, have been taking place at about 2-year
intervals. A device performance gain of about 30°/0-400/0
and a density enhancement of 2X is delivered between
successive technologies. Therefore, even at this accelerated
pace of voltage reductio% the active power-density has been
steadily rising since the circuit density and performance
enhancements outpace the power reduction achieved via VDD
scaling. A low-power scaling scenario with more aggressive
supply voltage reduction can offer relatively constant power
density [1].
As we prowess along the supply-voltage reduction pat~ the
impact of the non-scalability of the threshold voltage (VT)
becomes more severe. Generally, for every 100mV
(c) 1999 IEEE
reduction in VT, the device off current (10$ and the standby
current increase by 10X (85°C). Low standby current is
required to allow for functional operation under burn-~ IDN
testing at room temperature, fimctioml dynamic circuits, and
adequately low standby power dissipation at worst case
operating temperature [2]. The exponential dependence of
the standby current on VT tends to limit the minimum
allowable VT to about 0,20V at room temperature.
Therefore, as the VDDdecreases without the corresponding
reduction in VT, the device performance gain slows down
due to the reduced overdrive. This effect is demonstrated in
Fig. 1, where the performance improvement of successive
CMOS generations down to sub-O.1pm regime is presented
[2]. The lower &shed line represents the ideal scaling
scenario where the performance improves proportional to the
channel length. We can see that the device performance gain
departs fkom the ideal case for shorter channel lengths at
reduced voltages, mainly due to fact that the VT is scaled
down less than VDD for the reasons mentioned above.
Therefore, the VDDcannot be significantly reduced below
1.OVfor performance driven applications, unless new circuit
techniques and chip architectures allow decoupling of the
device off-current from performance which would make it
possible to reduce VT proportional to VDD.
The overall chip performance in most designs is calibrated
against the VTof the nominal or long channel devices, while
the off current is determined by the minimum channel length.
A key element in minimizing the VTof the nominal device is
the reduction of the device short channel effect (V,
difference between nominal and minimum channel length at
a given technology generation). Excellent short channel
behavior has been demonstrated for nFET and pFET devices
down to 0.06P and 0.08~ respectively, in a O.18~m
generation technology, by employing aggressive
source/drain halo, shallow extensions and thin gate dielectric
[9]. Further device optimization and thinner gate dielectrics
will enable short channel devices down to 0.03pm.
A lower limit for the gate dielectric thickness might be on
the order of 1.5nm (SiOz) which is the thickness at which the
tunneling gate current approaches the device off-current at
VDD of 1.OV [6]. The gate dielectric reliability is another
key issue which might dictate the minimum allowable
thickness [10].
Due to these limitations, it will be diflicult to achieve CMOS
devices with Lm below 0.03~m for room temperature
operatio~ even if all the manufacturing issues with respect
to yielding the very thin gate dielectrics and short channel
lengths are resolved. Given the current pace of CMOS
technology development (sub-O.1j.un L~ in manufacturing
today), we should reach 0.031,uuminimum effective channel
length before 2005. This corresponds to a nominal effective
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channel length of about 0.04~m. One can always improve
the tolerances and reduce the nominal channel len~ and
thus gain some level of higher performance, however, the
lower limit of the device channel length poses a significant
barrier to future scaling of CMOS technologies.
Integration and Copper Interconnect: Presently, the most
advanced bulk CMOS technology that will be in
manufacturing in 1999 is the O.18pm generation [11,12,13].
This technology [11] offers twice the density c~fthe previous
0.25wm CMOS generatio~ [14], and about 40% higher
device performance, in span of two years. An inverter delay
below 11 psec is achieved at supply-voltage of 1.5V (Fig.2).
The choice of the supply-voltage is consistent with the
high-performance scaling scenario [2], delivering the highest
device performance at dimensions consistent with nominal
effective channel length (L,j-r) under 0.1~m. In this
technology, 7 levels of copper metalizatiorl are offered,
delivering low interconnect RC delay as well as low line to
line and total capacitances [4, 11]. The application of local
interconnect allows dense SRAM cell size as small as
3.84p’ [11].
Fig. 3 shows the effect of the copper in reducing the
capacitances, relative to an optimized aluminum interconnect
[12] and for several dielectrics with dielectric constants
ranging slom 8=4.1 (Undopped SiOz, US)G) to 8=3.6
(Fluorinated SiOz, FSG) to 8=2.9 (hydrogen silsequioxane,
HSG). Relative to the Ai/FSG system with the same sheet
resistance, the Cu/FSG and Cu/USG deliver 17% and 10%
reduction in line to line capacitance, respectively, Fig.3a.
This is due to metal height reduction in copper, made
possible by its lower resistivity [4,11]. The total capacitance
for CW’FSGis reduced by about IO?40relative to AM?SG,
Fig.3b. Overall, the combination of dual damascene copper
interconnect with low e dielectrics will allow continued
scaling of the interconnect lines down to 0.1~m CMOS
without significant circuit delay impact and insurmountable
manufacturing yield loss and cost. Hierarchical interconnect
schemes, dictating thicker and wider lines at upper levels
must still be employed to contain the long net delays within
an acceptable range, consistent with the several GHz
operating frequencies of the systems which will be built in
these technologies.
Lithography: The 1997 NTRS Roadmap [8] of the
lithography minimum feature size for the gate level and
general lithography (half pitch) is shown in Fig.4 along with
the 1994 N’TRS Roadmap. As we can see, there has been a
significant acceleration of the general lithography (about a
year) which is a measure of the density and a very significant
acceleration of the gate lithography (about three years)
which is a measure of device performance. This
acceleratio~ in part, can be attributed to the robust 248nm
(c) 1999 IEEE
DUV lithography system winch not only orrers slgnmcam
wavelength reduction (A?J?L =47’%0) relative to its
predecessor (I-line @ 365nm), but also offers extendibility
possibly down to O.13pm generatio~ by employing high
numerical aperture tools and various resolution enhancement
technologies such as Phase Shift Mask (PSM) and off-axis
illumination [15].
The discussion of the lithogmphy ecosystem (exposure tools,
resist, mask making, RET ......) is beyond the scope of this
paper but the key point is that the optical lithography which
has continued to deliver consistently on all fmna i.e.,
resolutio% tolerance, overlay, and throughput is becoming
significantly more challenging as we move beyond O.13~m
generation. Shorter wavelength systems with 193nm and
157nm are needed for the 0.1m generation and beyond with
many unknowns and at the same time offering less
improvement (AM) relative to the 2481uu systems. All the
other non-optical lithography technologies are significantly
behind in one or more of the key requirements. The net is
that unless there is an overwhelming economic drive, the
pace of the lithographic shrink will slow down after the
O.lpm generation which is also before year 2005.
FUTURE OF CMOS TECHNOLOGY:
PATH TO CONTINUED GROWTH
The two key bottlenecks in the path towards sustained
CMOS growth are: performance saturation and the slow
down of density enhancement. The following are some
ahernatives to extend further growth.
Silicon On Insulator: One of the least disruptive
technologies that offers additional device level performance
at a given lithography and supply-voltage is (S01) [5]. SOI
CMOS devices are built on a layer of insulator instead of
bulk silico~ Fig.5, and offer about 20Y0-35Y0performance
enhancement. SOI offers an additional degree of freedom to
deliver higher device performance without pushing on
channel length and gate oxide thickness, since the SOI
performance gain over bulk comes from elimination of the
area junction capacitance, higher dynamic drive current, and
elimination of the body effect [5]. Higher performance gain
is expected if circuits, optimized for SOI devices, are
employe~ e.g., stacked devices, or extensive use of pass
gates as in CPL. The performance advantage of SOI is
demonstrated in a 64-bit microprocessor, built in 0.22pm
CMOS as shown in Table-1 [16]. The key challenges of
employing SOI technology are the availability of low
cosdlow defect substrate, and minimimtion of floating body
effects which complicate device models and circuit
techniques. Floating body effects in a partially depleted
design lead to kink effect, history effect, pass gate leakage
and lower device breakdown voltage due to bipolar effect.
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Dy proper opmmzauon 01 me uevIw utx+y CUM p WGM,
these issues can be contained for 1,8V supply-voltage [5,
17].
As the supply-voltage drops, the impact of the SOI
shortcomings are reduced while the advantages become
more significant. In addition to higher performance at the
same worst-case off current, SOI offers better SER
immunity, reduced noise coupling through substrate, and
possibly tighter ground rules due to elimination of latch-up.
The SOI performance gain can be traded off with
significantly lower active power dissipation by reducing the
supply-voltage in a given design. A 2-3X active power
reduction can be achieved relative to bulk CMOS at the
same performance, Fig.6 [17].
Variations of the SOI device such as Dynamic Threshold
MOS (DTMOS) [18] and double gate [19] may offer fiulher
advantages for operation at lower than 1.OV, or higher
device currents, respectively. Ano@er possible device
enhancement can come from increased carrier nobilities by
using strained silicon FET devices [20]. These novel
materials and structures introduce additional device design
and processing challenges which will most likely push their
application beyond year 2005.
Cooled CMOS: Lowering the operating te~perature of the
CMOS circuits improves the device performance and at the
same time reduces the interconnect resistance. The
performance gain is due steeper sub-threshold slope which
allows a lower VT at a given off-current, and higher carrier
nobilities. Depending on the device design point, about
30% device performance gain can be achieved at -30 “C
[21].
Embedded DRAM: Functional integration, made possible
by embedding analog and dense memories, is a critical
direction which can lead to significant performance
enhancement of silicon chip even if the device and
intercormect performances saturate. One attractive
technology for such integration is the embedded DRAM into
a high-performance logic base. In a recent ‘worQ a trench
DRAM with a cell size of 0.62~m2 is integrated into a
high-performance CMOS logic technology [7]. This
represents about a 6X cell density enhancement relative to
the state of the art SR4M in the same technology. The
logic peri%ormanceof this technology can be 2-3X higher
than a DRAM base embedded technology, Fig,7 [7,9]. Other
distinguishing features of a logic buse embedded DR4M
include: flexibility in designing a high-speed DRAM macro
with appropriate (and in some cases more relaxed)
application specific specs on retention time ;and cell size,
and the migratability of the existing ASIC and various
design cores. The exploitation of the trench DRAM is
(c) 1999 IEEE
particularly usefid, since after the fabrication of the trench
storage capacitors, the silicon surface is flat and all the
process heat cycles associated with the storage node are
completed, Fig.7 [7]. Therefore the high-performance logic
devices can be built undisturbed as they are not subject to
the storage node heat cycle and topography, as would be the
case for stacked storage capacitor. This technology can
offer significant increase in memo~ bus width, bandwidm
and lower latency, at reduced power diasipatkm, leading to
an overall system performance enhancement and cost
reduction.
We are at the very early stages of exploiting this embedded
technology, and innovative circuit and system architecture
designs are key in realizing its full potential. An important
factor in the success of the embedded technologies and
applications is that the total system cost should be reduced.
Therefore silicon-level embedded technologies where the
chip cost exceeds the system price would not be pervasive.
However, in those cases, opportunities might exist where a
package-level embedded technology, such as chip staclG
could provide the optimum cost-petiormance system.
SUMMARY and CONCLUSIONS
The semiconductor industry, Iieling and at the same time
funded by the huge Information Technology business, is
moving rapidly through an unprecedented phase of
performance and productivity boost. The CMOS
technology, which is the workhorse of this industry, has been
running at an accelerated pace in the past 5 years, and is
beginning to run out of steam. Today’s CMOS technolo~
uses bulk devices and aluminum interconnects, By
migrating to technologies such as copper interconnect and
SOI, we will extend the life of CMOS technology.
However, before the year 2005, when the FET channel
lengths approach 0.03 ~m and supply voltages go down to
1.OV, the device performance gain will saturate, even with
SOI (we can expect about 2X device performance
enhancement by then). Also, the 4X density boost that we
will enjoy between now and year 2003, will slow down
subsequently, due to significant lithography challenges post
0.1pm generation.
Fig.8 depicts some of the concepts discussed in this paper.
The lower line is the bulk CMOS base line with aluminum
interconnect. In this case, the silicon performance boost
mainly comes from the FET devices which deviate horn the
ideal scaling at the 0.1pm channel length ( 1.5V) as shown in
Fig. 1. In addition to the device performance saturatio~ the
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interconnect delay degrades the performance as the
dimensions shrink. By using copper and low & dielectric
instead of ahnninumRiOz, we can gain back allarge portion
of the performance loss due to interconnect RC delay and
capacitances. Employing SOI devices will give us another
30% performance boost, and then cooling the chips to
-30 “C, will yield an additional 30Y0.Other novel materials
(such as, strained silicon) and device structures (such as,
DTMOS, dual gate) are not included in Fig,,8 as they are
unlikely to have a significant impact before the year 2005.
Circuit and architecture innovations, along with embedded
technologies, will have to carry the load in maintaining the
pace of the silicon performance growth as we exhaust the
device and intercomect gains.
ACKNOWLEDGMENT
I would like to express my gratitude to all members of the
IBM Semiconductor Research and Development Center
(SRDC) who made this work possible. My special thanks
go to Fari Assaderaghi, Tim Brunner, Hi~ Calhoun,
Emmanuel Crabbe, Scott Crowder, Subu Iyer, Russ Lange,
Tak Ning, Ghavarn Shahidi and Lisa Su for many helpfbl
discussions and their contribution to this work.
REFERENCES
1. B. Davan, et al., Proc. of IEEE, VO1.83,PP.595,(1995)
2. B. Davan, et al., IEDMTech.Digest,pp. 555, (1996)
3. T. Bnmner, IEDMTech.Digest,pp. 9, (1997)
4. D. Edelstein,et al., IEDMTech.Digest,pp.773, (1997)
5, G. Shahidi,et al., ISSCCTech.Digest,pp.426, (,1999)
6. S.H.Lo, et al., IEEE, EDL, 18,PP.209,(1997)
7. S. Crowder,et al., IEDMTech Digest,pp. 1017,(1998)
8. The NationalTechnologyRoadrnapfor Semiconductors,
publishedby the SemiconductorIndustrialAssociation,San
Jose,CA (1997)
9. M. Hargrove,et al., IEDMTech Digest,pp. 627, (1998)
10. J.H. Stathis,et al., IEDMTechDigest,pp. 167.,(1998)
11. S. Crowder,VLSITechnologySymp,(1999)
12. S. Yang, et al., IEDMTech.Digest,pp. 197,(1998)
13. M. Redder, et al., IEDMTech. Digest,pp. 623, (1998)
14. S, Subbanna,et al., IEDMTech.Digest,pp. 275, (1996)
15. M. Levenson,SPIE VO1.3051,pp.2, (1997)
16. D. H. Allen,ISSCCTech. Digest,pp.438, (1999)
17. D.J. Schepis,et al., IEDMTech. Digest,pp. 587, (1997)
18, F. Assaderaghi,et al., IEDMTech.Digest,pp. 809,(1994)
19. H.S. Wong,et al., IEDMTech.Digest,pp. 427, (1997)
20. K. Rim, et al., IEDMTech.Digest,pp. 707, (1!?98)
21. Y. Taur,et al., IEDMTech.Digest,pp. 215, (1997)
(c) 1999 IEEE
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Table 1. Comparison of 64-bit microprocessor
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(c) 1999 IEEE
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(c) 1999 IEEE