Digital
g Logic
g Analysis
y & Design
g
Outline
Review - Positional Number Systems
Radix Conversion
Representation of Negative Numbers
Addition and Subtraction of Signed Numbers
Adders and Subtracters
Multipliers
Combinational Shifter
C
Comparatort
Floating Point Representation
Floating Point Addition
Floating Point Multiplication
© ptb/dkb (November 19, 2010) Arithmetic Circuits 2
1
Positional Number System – a review
Value of a number is determined by a weighted sum of its digits
Weighting is implicit and is determined for each digit by the position
of the digit in the number
Let the number have n digits to the left of the radix point and m digits
to the right of the radix point. Di is the ith digit, R is the radix or base
of the number,V is the value of the number.
n 1
V Di R i n digits m digits
i m
E l : 12.3410 4 10 2 3 10 1 2 10 0 1 101
Example
Radix Conversion
Conversion from radix R to Decimal
Example
11.011 2 1 2 3 1 2 2 0 2 1 1 2 0 1 21
0.125 0.25 0 1 2
3.37510
2
Conversion from Decimal to Radix R
Let rk be the kth digit of the radix R number :
Convert integer part: Let Di be the integer part of the decimal number
1. k=0; Dk =Di ;
2. rk =Dk mod R;
3. Dk 1 Dk / R ;
4. if (Dk+1= 0) then quit ;
else k=k+1; and go to 2
Example
Convert 3.375 to binary
D0 3.375 3; r0 3 mod 2 1
D1 3 / 2 1; r1 1 mod 2 1
D2 1 / 2 0;
3
Conversion among Radices that are
Powers of 2
Conversion among binary, octal and hex can be done by “grouping”
bits as follows:
1. First,, express
p each octal or hex digit
g as a binary
y number. This is the
conversion to binary.
2. To convert from binary to octal or hex, group sets of 3 bits (for octal) or
4 bits (for hex). The grouping must start at the binary point and go to
the left for the integer part of the number and to the right for the
fractional part. Add 0 bits as needed to the left end or right end of the
number.
3. Treat each group of bits as an octal (or hex) digit and rewrite it as a 0-7
(0-f).
(0 f).
IIn mathematics,
th ti there
th are infinitely
i fi it l many positive
iti andd negative
ti
integers. However, in a practical hardware system only a fixed
number of integers can be represented.
4
Sign Magnitude Representation
Use MSB as a sign bit as follows,
MSB = 0 for positive integers S Magnitude (n-1 bits)
MSB = 1 for negative integers n bits
Other bits encode magnitude of integer.
Range of representation with n bits is: 2 n 1 X 2 n 1
The range is symmetric around 0.
There are two representations for 0, i.e., 0000 and 1000.
Examples:
5
Twos Complement Representation
Positive integers are represented “as is”. Negative integers are
formed by subtracting magnitude of negative integer from 0;
borrowing from imaginary position to the left of MSB.
(Shortcut: bit-wise complement
p of the integer
g and add 1)).
Example: 5 = 0101 -5 = 0000 – 0101 = 1011
All positive integers have MSB=0; negative integers have MSB=1
Range of representation with n bits is: 2 n 1 X 2 n 1
The range is asymmetric around 0.
There is only one representation for 0, i.e., 0000.
Examples:
Assume a 5-bit representation, Convertt the
C th following
f ll i signed
i d
01110 = 14 numbers to a 8-bit representation.
10111 = -9
15 = 01111 01011 = 00001011
16 = not with 5 bits
-16 = 10000 10111 = 11110111
10001 = 17 – 24 = 1
01100 = 12 – 24 = -4
00000 = 0 – 24 = -16
0 = 0 + 24 = 10000
15 = 15 + 24 = 11111
6
Addition and Subtraction of Signed
Numbers
X Y X Y
Addition/Subtraction in Sign
Magnitude Representation
7
Addition/Subtraction in 1’s
Complement Representation
Negation is trivial – just invert all bits
Addition is performed in 2 steps:
1. Add all bits; any carry out of bit position i must be added into bit position
(i +1).
2. Add the result of first step with the carry out of the MSB position from
step 1. This carry is called the End Around Carry (EAC).
Examples:
Addition/Subtraction in 2’s
Complement Representation
Negation is expensive – first invert all bits; then add 1.
Addition is performed by adding all bits; any carry out of bit position i
mustt be
b added
dd d iinto
t bit position
iti (i +1).
1) Ignore
I carry outt off MSB.
MSB
Examples:
8
Overflow Detection
Some additions and subtractions may produce results that cannot be
represented using the number of bits allocated for the result (i.e.,
precision).
example, for an n-bit 2’s
For example 2 s complement represented number
number, if the
result is greater than (2n-1-1) it can’t be represented using n-bits.
There is an overflow.
How can overflow be detected?
If (carry into the MSB) ≠ (carry out of the MSB) then overflow has occurred.
Examples:
for 1’s comp. numbers
1011 (-4) for 2’s comp. numbers
+ 1010 (-5)
0100 0100 (4)
10101 - 1011 + 0101 (-5)
+ 1
0110 (6) OVFL 1001 (-7) OVFL
Inputs Outputs
a b Carry Sum
0 0 0 0
Sum a b a b a b
0 1 0 1
C
Carry ab
1 0 0 1
1 1 1 0
9
Half Adder
Sum a b a b a b
y ab
Carry
Half adders cannot accept a carry input and hence it is not possible
to cascade them to construct an n-bit binary adder.
Full Adder
Full Adder is a combinational circuit that forms the arithmetic sum of
three input bits. It is described by the following truth table:
Inputs Outputs
c b a Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Sum a b c a b c a b c a b c a b c
C out a b a c b c a b c a b
10
Full Adder Implementation - 1
Sum a b c a b c a b c a b c a b c
C out a b a c b c a b c a b
ai bi
ai
si bi
Full
Adder
ci+1 (FA) ci
ci+1
ci
Full Adder at bit i
si
ai
si bi
ci+1 ci
ai bi
Full
Adder
ci+1 (FA) ci
si
11
Performance of a Full Adder
Use a 2-input NAND gate implementation of a 1-bit full adder. Why ?
12
Performance of an n-bit Ripple Carry
Adder
Subtracter
13
2’s Complement Subtracter
Design a 4-bit subtracter using 2’s complement number representation.
Diff = A - B
Inputs: A = (a3a2a1a0) Outputs: Diff = (s3s2s1s0)
B = (b3b2b1b0) Cout is ignored
A B
BCD Addition
When we add two BCD digits, the sum may exceed 9
we need to do appropriate correction.
Let X = x3x2x1x0 and Y = y3y2y1y0 represent the two BCD digits and
S = s3s2s1s0 be their sum.
sum
Z X Y
if Z 9 then S Z and cout 0
if Z 9 then S Z 6 and cout 1
X 0111 7 X 1000 8
+Y +0101 +5 +Y +1001 +9
Z 1100 1 2 Z 10001 1 7
+0110 +0110
1 0010 1 0111
cout=1 S=2 cout=1 S=7
© ptb/dkb (November 19, 2010) Arithmetic Circuits 29
14
1-Digit BCD Adder
X Y
x3 y3 x2 y2 x1 y1 x1 y1
4 bit Adder
4-bit Add cin FA FA FA FA cin
Z z3 z2 z1 z0
6 0
Z>9
?
yes MUX
FA HA
15
Bit--Serial Adder
Bit
16
Unsigned Binary Multiplication
m n 1 m 1 n 1 m 1 n 1
P X Y pk 2 k x i 2 i y j 2 j x i y j 2 i j
k 0 i 0 j 0 i 0 j 0
Array Multiplier
x3 x2 x1 x0
x3x2x1x0 y0
× y3y2y1y0
y0x3 y0x2 y0x1 y0x0
y1x3 y1x2 y1x1 y1x0 y1
y2x3 y2x2 y2x1 y2x0
y3x3 y3x2 y3x1 y3x0 HA FA FA HA
y2
FA FA FA HA
y3
FA FA FA HA
p7 p6 p5 p4 p3 p2 p1 p0
17
Performance of Array Multiplier
m
x3 x2 x1 x0
y0
y1
HA FA FA HA
n
y2
Critical path 1 FA FA FA HA
Critical path 2
y3
FA FA FA HA
p7 p6 p5 p4 p3 p2 p1 p0
t mult t and m 1 n 2 t carry n 1 t sum
y1
HA HA HA
y2
FA FA FA
y3
FA FA FA
p7 p6 p5 p4 p3 p2 p1 p0
© ptb/dkb (November 19, 2010) Arithmetic Circuits 44
18
Signed Multiplication
Combinational Shifter
19
Logarithmic Depth Shifter
Left Shifter Right Shifter
in[7:0]
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
shift right by 5
1 shift
f 0
0 shift1
1 shift2
1 shift3
7 6 5 4 3 2 1 0
Area = O(nlog2n) out[7:0]
Note: Interconnections are shown for
Time = O(log2n)
Arithmetic Shift operation
© ptb/dkb (November 19, 2010) Arithmetic Circuits 53
xn-1 yn-1 x2 y2 x1 y1 x0 y0
x y x y x y x y
EQn EQUIV EQ EQ3 EQUIV EQ2 EQUIV EQ1 EQUIV EQ0
n-1
EQO EQI EQO EQI EQO EQI EQO EQI
20
4-Bit Comparator
Magnitude comparator for
n-bit unsigned binary numbers
Inputs: a3a2a1a0
4 4
b3b2b1b0
altbin aeqbin agtbin b3-0 a3-0
Outputs: altbout altbin
aeqboutCOMP4 aeqbin
altbout aeqbout agtbout agtbin
agtbout
Logic Equations:
agtbout a 3 0 >b3 0 a3 0 =b3 0 agtbin
aeqbout a3 0 =b3 0 aeqbin
altbout a3 0 <b3 0 a 3 0 =b3 0 altbin
a30 b30
a3b3 a3 b3 a2b2 a3 b3 a2 b2 a1b1 a3 b3 a2 b2 a1 b1 a0b0
a30 b30 a3 b3 a2 b2 a1 b1 a0 b0
a30 b30 a30 b30 a30 b30
© ptb/dkb (November 19, 2010) Arithmetic Circuits 55
x11…0
y11…0
11 0
x11…8 y11…8 x7…4 y7…4 x3…0 y3…0
4 4 4 4 4 4
b
3-0 3-0 a XLTY8 b3-0 a3-0 b3-0 a3-0
XLTY XLTY4
altb altbin XEQY8 altbout altb altb altbin 0
XEQY out in XEQY4 out
aeqboutCOMP4 aeqbin aeqboutCOMP4 aeqbin aeqb COMP4 aeqb
in
1
XGTY agtb XGTY8 agtb XGTY4
out
agtbout in agtbout in agtbout agtbin 0
21
MIN/MAX Circuit
Use a 4-bit comparator to design an 8-bit MIN/MAX circuit.
Inputs: unsigned inputs, X ≡ x7..0 , Y ≡ y7..0
and a control signal MINMAX
Output: min X ,Y if MINMAX 1
Z
max X ,Y if MINMAX 0
MINMAX
X>Y MINMAX Z S
X 0 0 Y 1
12 COMP 0 1 X 0
X>Y
Y 1 0 X 0
12 S
1 1 Y 1
0
MUX Z
1 12
22
IEEE Floating
Floating--Point Format
Single Precision Format: (32 bits)
1 8 bits 23 bits
F = (-1)S × 1. M × 2E-127
Special reserved values:
E=0 with M = 0 represents ZERO
E = 255 with M = 0 represents ± oo
E = 255 with M ≠ 0 represents NaN
Double Precision Format: (64 bits)
1 11 bits 52 bits
F = (-1)S × 1. M × 2E-1023
© ptb/dkb (November 19, 2010) Arithmetic Circuits 59
Examples
Convert 4.62×102 to IEEE single precision format:
4.62×102 = 462 = 111001110.0 = 1.110011100 × 28
Mantissa = 110011100 Exponent = 8+127 = 135 = 10000111
0 1000 0111 1100 1110 0000 0000 0000 000 = 0 87 CE0000
23
Floating--Point Addition (unsigned)
Floating
How to add two floating-point numbers?
(Ma,Ea) + (Mb,Eb)
Example: Addition
Add (0 11000000, 011) to (0 10101100, 100) (input numbers are
positive and are in the normalized form with excess-4 exponent).
That is, (1.11000000 × 2011-100) + (1.10101100 × 2100-100) = ?
24
Floating--Point Multiplication
Floating
How to multiply two floating-point numbers?
(Ma, Ea) × (Mb, Eb)
1. MPROD = M1 × M2
2. EPROD = E1 + E2- bias
3. Post-normalize MPROD by shifting by an appropriate amount
and then updating EPROD by the same amount.
4. Rounding may be required to store the result in the same
number
b off bits
bit ((precision)
i i ) as th
the iinputs.
t
5. If necessary, normalize and update EPROD
6. Result = (MPROD, EPROD).
Example: Multiplication
Multiply (0 10101100, 0101) and (0 11000000, 0110) (input
numbers positive and are in the normalized form with
excess-8
excess 8 exponent).
That is, (1.10101100 × 20101-1000) × (1.11000000 × 20110-1000) = ?
25
Example: Centigrade – Fahrenheit Converter
<<1 32 (00100000)
8 8
8-bit adder
How would you design 8
this adder efficiently?
F
clk
1 1 1 1
4 4 4 4
+ + + y[n]
y[n]
y[n]
x[n]
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
n 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
n n
Input Signal Output Signal (4-point avg.) Output Signal (8-point avg.)
© ptb/dkb (November 19, 2010) Arithmetic Circuits 66
26
Filter Implementation
Since all samples get multiplied by ¼ we can do it once at the end.
Multiply by ¼ (i.e. divide by 4) is done by shifting right by 2 bits.
4 clk 4 4 4
+ + 6
+ 5 4
y[n]
5 6-bit 6 bit
6-bit
5-bit 4
add add add 3
2
1
0
27