(Final Version)
Help:
email: bsim3@bsim.eecs.berkeley.edu
How to get a copy of this manual and SPICE source code (model part only):
APPENDIX C: References
In the mist of all these new features, BSIM3v3 still retains the same physical
underpinnings of BSIM3 Version 2.0. For example, his new model still has the
extensive built-in dependencies of important dimensional and processing
parameters (e.g. channel length, width, gate oxide thickness, junction depth,
substrate doping concentration, etc.). This allows users to accurately model the
MOSFET over a wide range of channel lengths as well as channel widths for
present as well as future technologies. Furthermore, BSIM3v3 still relies on a
coherent pseudo-2D formulation to model various short-channel and high field
effects such as the following:
Meticulous care has been taken to mesh the above model enhancements with high
levels of accuracy and minimum simulation costs. In addition, the enhanced
expressions yield more continuous behavior and should also help to facilitate faster
SPICE convergence properties.
• Chapter 2 will highlight the physical basis and arguments used in deriving
BSIM3v3’s I-V equations.
• Chapter 3 will combine these various BSIM3v3 equations for different
operational regimes in a unified I-V model.
• Chapter 4 will present the new capacitance model.
• Chapter 5 will detail the inclusion of the new model for transient modeling
called the NQS (Non-Quasi-Static) Model.
• Chapter 6 will discuss SPICE model file extraction.
• Chapter 7 will provide results of some benchmark tests applied on the model to
illustrate its general robustness (no discontinuities).
• Chapter 8 will conclude with the noise model.
• Chapter 9 will describe the MOS diode model.
• Finally, the Appendix will list all model equations and references used
throughout this manual. In addition, model parameters which can be binned
during parameter extraction will also be listed.
regimes. By using threshold voltage, the whole device operation regime can be
divided into three operational regions.
First, if the gate voltage is greater than the threshold voltage, the inversion charge
density is larger than the substrate doping concentration. The MOSFET is then
operating in the strong inversion region and drift current is dominant. Second, if
the gate voltage is much less than the threshold voltage, the inversion charge
density is smaller than the substrate doping concentration. The MOSFET is now
considered to be operating in the weak inversion (or subthreshold) region.
Diffusion current is now dominant [2]. Lastly, if the gate voltage is very close to
the threshold voltage, the inversion charge density is close to the doping
concentration and the MOSFET is operating in the transition region. In such a
case, both diffusion and drift currents are equally important.
The standard threshold voltage of a MOSFET with long channel length/width and
uniform substrate doping concentration [2] is given by:
(2.1.1)
where VFB is the flat band voltage, VTideal is the ideal threshold voltage of the long
channel device at zero volt substrate bias, and γ is the substrate bias effect
coefficient and is given by:
(2.1.2)
2 ε si qN a
γ=
Cox
where Na is the substrate doping concentration. The surface potential is given by:
(2.1.3)
K T N
φ s = 2 B ln( a )
q ni
Equation (2.1.1) assumes that the channel is uniform and makes use of the one
dimensional Poisson equation in the vertical direction of the channel. This model
is valid only when the substrate doping concentration is constant and the channel
length is long. Under these conditions, the potential is uniform along the channel.
But in reality, these two conditions are not always satisfied. Modifications have to
be made when the substrate doping concentration is not uniform or and when the
channel length is short, narrow, or both.
The substrate doping level is not constant in the vertical direction as shown
in Figure 2-1.
Nch
Nsub
(2.1.4)
Vth = VTideal + K1 ( φ s − Vbs − φ s ) − K2 Vbs
For a zero substrate bias, Eqs. (2.1.1) and (2.1.4) give the same result. K1
and K2 can be determined by the criteria that Vth and its derivative versus
Vbs should be the same at Vbm, where Vbm is the maximum substrate bias
voltage. Therefore, using equations (2.1.1) and (2.1.4), K1 and K2 [3] will
be given by the following:
(2.1.5)
K1 = γ 2 − 2 K2 φ s − Vbm
(2.1.6)
φ s − Vbx − φ s
K2 = ( γ 1 − γ 2 )
2 φ s ( φ s − Vbm − φ s ) + Vbm
where γ1 (or γ2) is the body effect coefficient when the substrate doping
concentration is Nch (or Nsub) as shown in Figure 2-1.
(2.1.7)
2 qε si N ch
γ1 =
Cox
(2.1.8)
2 qε si N sub
γ2 =
Cox
Vbx is the body bias when the depletion width is equal to Xt. Therefore, Vbx
satisfies:
(2.1.9)
2
qN ch X
= φ s − Vbx
t
2ε si
For some technologies, the doping concentration near the drain and the
source is higher than that in the middle of the channel. This is referred to as
lateral non-uniform doping and is shown in Figure 2-2. As the channel
length becomes shorter, lateral non-uniform doping will cause the
threshold voltage to increase in magnitude because the average doping
concentration in the channel is larger. The average channel doping can be
calculated as follows:
(2.1.10)
N a ( L − 2 L x ) + N ds ⋅ 2 Lx 2 L N − Na
N eff = = N a (1 + x ds )
L L Na
Nlx
≡ N a (1 + )
L
(2.1.11)
Vth = Vtho + K 1 ( Φs − Vbseff − Φs ) − K 2 Vbse
NLX
+ K1 1 + − 1 Φs + ( K 3 + K 3bVb
Leff
Eq. (2.1.11) can be derived by setting Vbs = 0, and using K1 ∝ (Neff)0.5. The
fourth term in Eq. (2.1.11) is used empirically to model the body bias
dependence of the lateral non-uniform doping effect. This effect gets
stronger at a lower body bias. Examination of Eq. (2.1.11) shows that the
threshold voltage will increase as channel length decreases [3].
The short channel effect can be modeled in the threshold voltage by the fol-
lowing:
(2.1.12)
Vth = Vtho + K 1 ( Φs − Vbseff − Φs ) − K 2 Vbs
NLX
+ K1 1 + − 1 Φs +- (∆V
K 3th+ K 3bV
Leff
where ∆Vth is the threshold voltage reduction due to the short channel
effect. Many models have been developed to calculate ∆Vth. They used
either numerical solutions [4], a two-dimensional charge sharing approach
[5,6], or a simplified Poisson's equation in the depletion region [7-9]. A
simple, accurate, and physical model was developed by Z.H. Liu, et al,
[10]. Their model was derived by solving the quasi two-dimension Poisson
equation along the channel. This quasi-2D model concluded that:
(2.1.13)
∆Vth = θ th ( L )[ 2 ( Vbi − φ s ) + Vds ]
where Vbi is the built-in voltage of a PN junction between the substrate and
the source. Vbi is given by:
(2.1.14)
K T N N
Vbi = B ln( ch 2 d )
q ni
where Nd in Eq. (2.1.14) is the source doping concentration, and Nch is the
substrate doping concentration. The expression θth(L) is a short channel
effect coefficient that has a strong dependence on the channel length and is
given by:
(2.1.15)
θ th ( L ) = [exp( − L 2 lt ) + 2 exp( − L lt )]
(2.1.16)
ε si Tox X dep
lt =
ε ox η
(2.1.17)
2ε si (φ s − Vbs )
X dep =
qN ch
Xdep is larger near the drain than in the middle of the channel due to the
drain voltage. Xdep / η represents the average depletion width along the
channel.
make the model fit a wide technology range, several parameters such as
Dvt0, Dvt2, Dsub, Eta0 and Etab are introduced, and the following modes are
used in SPICE to account for charge sharing and the DIBL effects
separately.
(2.1.18)
θ th ( L ) = Dvt 0 [exp( − Dvt 1 L / 2lt ) + 2 exp( − Dvt 1 L / lt )]
(2.1.19)
∆Vth( L ) = θth ( L )(Vbi − φs )
(2.1.20)
ε si Tox Xdep
lt = (1 + Dvt 2 Vbs )
ε ox
(2.1.21)
θ dibl ( L ) = [exp( − Dsub L / 2lt 0 ) + 2 exp( − Dsub L / lt 0 )]
(2.1.22)
∆Vth (Vds ) = θdibl ( L )( Eta 0 + EtabVbs)Vds
As channel length L decreases, ∆Vth will increase, and in turn Vth will
decrease. If a MOSFET has a LDD structure, Nd in Eq. (2.1.14) is the
doping concentration in the lightly doped region. Vbi in a LDD-MOSFET
will be smaller as compared to conventional MOSFETs, therefore the
threshold voltage reduction due to the short channel effect will be smaller
in LDD-MOSFETs.
As the body bias becomes more negative, the depletion width will increase
as shown in Eq. (2.1.17). Hence ∆Vth will increase due to the increase in lt.
The term:
VTideal + K1 φ s − Vbs − K 2 Vbs
will also increase as Vbs becomes more negative (for NMOS). Therefore,
the changes in:
VTideal + K1 φ s − Vbs − K 2 Vbs
and in ∆Vth will compensate for each other and make Vth less sensitive to
Vbs. This compensation is more significant as the channel length is
shortened. Hence, the Vth of short channel MOSFET is less sensitive to
body bias as compared to a long channel MOSFET. For the same reason,
the DIBL effect and the channel length dependence of Vth are stronger as
Vbs is made more negative. This was verified by experimental data shown in
Figure 2-3 and Figure 2-4. Although Liu, et al, found a accelerated Vth roll-
off and non-linear drain voltage dependence [10] as the channel became
very short, a linear dependence of Vth on Vds is nevertheless a good
approximation for circuit simulation as shown in Figure 2-4. This figure
shows that Eq. (2.1.13) can fit the experimental data very well.
Furthermore, Figure 2-5 shows how this model for Vth can fit various
channel lengths under various bias conditions.
Figure 2-3. Threshold voltage versus the drain voltage at different body biases.
The actual depletion region in the channel is always larger than what is
usually assumed under the one-dimensional analysis due to the existence of
fringing fields [2]. This effect becomes very substantial as the channel
width decreases and the depletion region underneath the fringing field
becomes comparable to the "classical" depletion layer formed from the
vertical field. The net result is an increase threshold voltage magnitude. It
is shown in [2] that this increase can be modeled as:
(2.1.23)
2
πqN a ( X d max ) T
= 3 π ox φ s
2 Cox W W
The right hand side of Eq. (2.1.23) represents the additional voltage
increase. BSIM3v3 models this change in threshold voltage by Eq.
(2.1.24a). This formulation includes but is not limited to the inverse of
channel width due to the fact that the overall narrow width effect is
dependent on process (i.e. isolation technology) as well. Hence, the
introduction of parameters K3, K3b, and W0.
(2.1.24a)
Tox
( K 3 + K 3bVbs) φ
(W +W
eff ’+
(Weff W0)) s
0
Weff ’ is the effective channel width (with no bias dependencies), which will
be defined Section 2.9. In addition, we must also consider the narrow width
effect for small channel lengths. To do this we introduce the following:
(2.1.24b)
Weff ' Leff Weff ' Leff
DVT 0 w exp( − DVT 1w ) + 2 exp( − DVT 1w ) (Vbi − Φs )
2ltw ltw
When all of the above considerations for non-uniform doping, short and
narrow channel effects on threshold voltage are considered, the final,
complete Vth expression implemented in SPICE is as follows:
(2.1.25)
V th = V th o + K 1 ( Φ s − V b s eff − Φ s ) − K 2 V b s eff
N LX TOX
+ K 1 1+ − 1 Φs + (K 3 + K 3 b V b s eff ) Φs
L e ff W e ff ' + W 0
W e ff ' L e ff W e ff ' L e ff
− D VT 0 w exp ( − D VT 1w ) + 2 e x p ( − D V T 1w ) ( V b i − Φ s )
2 l tw l tw
− D V T 0 e x p ( − D V T 1
L e ff L e ff
) + 2 exp (− D VT 1 ) ( V b i − Φ s )
2 lt lt
(2.1.25) (cont.)
− exp( − Dsub
Leff Leff
) + 2 exp( − Dsub ) ( Etao + EtabVbseff ) Vds
2lto lto
In Eq. (2.1.25), all Vbs terms have been substituted with a Vbseff
expression as shown in Eq. (2.1.26). This is done in order to set an upper
bound for the body bias value during simulations. Unreasonable values can
occur if this expression is not introduced. See Section 3.8 for details
(2.1.26).
Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ 1) 2 − 4δ 1Vbc ]
K12
Vbc = 0.9(φs − )
4K 2 2
substrate voltage, etc. Sabnis and Clemens [13] proposed an empirical unified
formulation based on the concept of an effective field Eeff which lumps many
process parameters and bias conditions together. Eeff is defined by
(2.2.1)
Q + (Qn 2 )
Eeff = B
ε si
The physical meaning of Eeff can be interpreted as the average electrical field
experienced by the carriers in the inversion layer [14]. The unified formulation of
mobility is then empirically given by:
(2.2.2)
µ0
µ eff =
1 + ( Eeff E0 ) ν
Values for µ0, E0, a n d ν were reported by Liang et al. [15] and Toh et al. [16] to be
the following for electrons and holes:
Table 2-1. Mobility and related parameters for electrons and holes.
For a NMOS transistor with n-type poly-silicon gate, Eq. (2.2.1) can be rewritten
in a more useful form that explicitly relates Eeff to the device parameters [14]:
(2.2.3)
Vgs + Vth
Eeff ≅
6 Tox
Eq. (2.2.2) fits experimental data very well [15], but it involves a power function
which is a very time consuming function for circuit simulators such as SPICE. A
Taylor expansion Eq. (2.2.2) is used, and the coefficients are left to be determined
using experimental data or to be obtained by fitting the unified formulation. Thus,
we have:
(Mobmod=1) (2.2.4)
µo
µeff =
gsteff + 2 Vth
Vgst V gsteff + 2Vth 2
1 + (Ua + Uc Vbseff )( ) + Ub ( gst )
TOX TOX
.(Mobmod=2) (2.2.5)
µo
µeff =
Vgst V gsteff
) + Ub ( gst ) 2
gsteff
1 + (Ua + UcVbseff )(
TOX TOX
The unified mobility expressions in subthreshold and strong inversion regions will
be discussed in Section 3.2.
To consider the body bias dependence of Eq. 2.2.4 further, we have introduced the
following expression:
µo
µeff =
V gsteff + 2Vth Vgsteff + 2Vth 2
1 + [Ua ( gst ) + Ub ( gst ) ](1 + UcVbseff )
TOX TOX
(2.3.1)
µ eff E
v= , E < Esat
1 + ( E Esat )
= vsat , E > Esat
The parameter Esat corresponds to the critical electrical field at which the carrier
velocity becomes saturated. In order to have a continuous velocity model at E =
Esat, Esat must satisfy:
(2.3.2)
2 vsat
Esat =
µ eff
will cause threshold voltage to vary along the channel. This effect is called bulk
charge effect [14].
In BSIM3v3, the parameter Abulkis used to take into account this bulk charge effect.
This parameter is a modification from that of BSIM1 and BSIM2 where the bulk
charge parameter was "a" [3]. Several extracted parameters such as A0, Bo,B1 are
introduced to account for the channel length and width dependences of the bulk
charge effect. In addition, the parameter Keta is introduced to model the change in
bilk charge effect under high back or substrate bias conditions. It should be pointed
out that narrow width effects have been considered in the formulation of Eq.
(2.4.1). The Abulk expression used in BSIM3v3 is given by:
(2.4.1)
K1 A0 Leff Leff Bo 1
Abulk = (1 + { [1 − AgsVgsteff ( )2 ] + })
2 Φs − Vbseff Leff + 2 XJXdep Leff + 2 XJXdep Weff ' + B1 1 + KETA Vbseff
where A0, Ags, K1,Bo, B1 and Keta are determined by experimental data. Eq.
(2.4.1) shows that Abulk is very close to 1.0 if the channel length is small, and Abulk
increases as channel length increases.
In the strong inversion region, the general current equation at any point y
along the channel is given by:
(2.5.1)
I ds = WCox (Vgst − AbulkV ( y ))v ( y )
The parameter Vgst = (Vgs - V th), W is the device channel width, Cox is the
gate capacitance per unit area, V(y) is the potential difference between
minority-carrier quasi-Fermi potential and the equilibrium Fermi potential
in the bulk at point y, v(y) is the velocity of carriers at point y, and Abulk is
the coefficient accounting for the bulk charge effect.
With Eq. (2.3.1) (i.e. before carrier velocity saturates), the drain current
can be expressed as:
(2.5.2)
µ eff E ( y )
I ds = WCox (Vgs − Vth − AbulkV ( y ))
1 + E ( y ) E sat
(2.5.3)
I ds dV ( y )
E ( y) = =
µ eff WCox (V − AbulkV ( y )) − I ds E sat dy
gst
(2.5.4)
W 1
I ds = µ eff Cox (Vgs − Vth − Abulk Vds 2)Vds
L 1 + Vds E sat L
The drain current model in Eq. (2.5.4) is valid before the carrier velocity
saturates.
For instances when the drain voltage is high (and thus the lateral electrical
field is high at the drain side), the carrier velocity near the drain saturates.
The channel now can be reasonably divided into two portions: one adjacent
to the source where the carrier velocity is field-dependent and the second
where the velocity saturates. At the boundary between these two portions,
the channel voltage is the saturation voltage (Vdsat) and the lateral
electrical is equal to Esat. After the onset of saturation, we can substitute v
= vsat and Vds = Vdsat into Eq. (2.5.1) to get the saturation current:
(2.5.5)
I ds = WCox (Vgst − AbulkVdsat )v sat
(2.5.6)
E sat L(V gs − Vth )
Vdsat =
AbulkE sat L + (V gs − Vth )
(2.5.9)
V Vds
Ids = ds =
Rtot Rch + Rds
W 1 (Vgst − Abulk Vds 2 )Vds
= µ eff Cox
L 1 + Vds ( Esat L ) W (Vgst − Abulk Vds 2 )
1 + Rds µ eff Cox
L 1 + Vds ( Esat L )
Due to parasitic resistance, the saturation voltage Vdsat will be larger than
that predicted by Eq. (2.5.6). Let Eq. (2.5.5) be equal to Eq. (2.5.9). The
Vdsat with parasitic resistance Rds expression is then:
(2.5.10)
− b − b 2 − 4 ac
Vdsat =
2a
(2.5.11)
1
a = Abulk
2
Rds Cox Wv sat + ( − 1) Abulk
λ
2
b = −(Vgst ( − 1) + Abulk E sat L + 3 Abulk Rds Cox Wv sat Vgst )
λ
c = Esat LVgst + 2 Rds Cox Wvsat Vgst 2
λ = A1Vgst + A 2
(2.5.11)
The variable Rdsw is the resistance per unit width, Wr is a fitting parameter,
Prwb is the body effect coefficient, and Prwg is the gate-bais effect effect.
The first region is the triode (or linear) region in which carrier velocity is not
saturated. The output resistance is very small because the drain current has a strong
dependence on the drain voltage. The other three regions belong to the saturation
region. As will be discussed later, there are three physical mechanisms which
affect the output resistance in the saturation region: channel length modulation
(CLM) [4, 14], drain-induced barrier lowering (DIBL) [4, 6, 14], and the substrate
current induced body effect (SCBE) [14, 18, 19]. All three mechanisms affect the
output resistance in the saturation range, but each of them dominates in only a
single region. It will be shown next that channel length modulation (CLM)
dominates in the second region, DIBL in the third region, and SCBE in the fourth
region.
3.0 14
10
Rout (KOhms)
2.0
8
Ids (mA)
1.5
6
1.0
4
0.5
2
0.0 0
0 1 2 3 4
V ds (V)
Generally, drain current is a function of the gate voltage and the drain voltage. But
the drain current depends on the drain voltage very weakly in the saturation region.
A Taylor series can be used to expand the drain current in the saturation region [3].
(2.6.1)
∂Ids (Vgs , Vds )
Ids (Vgs , Vds ) = Ids (Vgs , Vdsat ) + (Vds − Vdsat )
∂Vds
V − Vdsat
≡ Idsat (1 + ds )
VA
where,
(2.6.2)
I dsat = I ds ( Vgs,Vdsat ) = Wvsat Cox ( Vgst − Abulk Vdsat )
and
(2.6.3)
∂ Ids −1
VA = Idsat ( )
∂ Vds
The parameter VA is called the Early Voltage (analogous to the BJT) and is
introduced for the analysis of the output resistance in the saturation region. Only
the first order term is kept in the Taylor series. For simplicity, we also assume that
the contributions to the Early Voltage from all three mechanisms are independent
and can be calculated separately.
(2.6.4)
∂ I ds ∂ L −1 Abulk Esat L + Vgst ∂ ∆L −1
VACLM = I dsat ( ) = ( )
∂ L ∂ Vds Abulk Esat ∂ Vds
(2.6.5)
Abulk Esat L + Vgst
VACLM = ( Vds − Vdsat )
Abulk Esat l
where VACLM is the Early Voltage due to channel length modulation alone.
The parameter Pclm is introduced into the VACLM expression not only to
compensate for the error caused by the Taylor expansion in the Early
Voltage model, but also to compensate for the error in Xj since:
l ∝ Xj
and the junction depth, Xj, can not generally be determined very accurately.
Thus, the VACLM became:
(2.6.6)
1 Abulk Esat L + Vgst
VACLM = ( Vds − Vdsat )
Pclm Abulk Esat l
(2.6.7)
∂ I ds ∂ Vth −1 1 1
VADIBLC = I dsat ( ) = (Vgst − ( +
∂ Vth ∂ Vds θ th ( L ) Abulk Vdsat V
The combination of the CLM and DIBL effects determines the output
resistance in the third region, as was shown in Figure 2-6.
(2.6.8)
θ rout ( L ) = Pdiblc1 [exp( − Drout L / 2 lt ) + 2 exp( − Drout L / lt )] + Pdiblc 2
The variables Pdiblc1, Pdiblc2, Pdiblcb and Drout are the newly introduced
parameters to correct for DIBL effect in the strong inversion region. The
reason why Dvt0 is not equal to Pdiblc1 and Dvt1 is not equal to Drout is
because the gate voltage modulates the DIBL effect. When the threshold
voltage is determined, the gate voltage is equal to the threshold voltage.
But in the saturation region where the output resistance is modeled, the
gate voltage is much larger than the threshold voltage. Drain induced
barrier lowering may not be the same at different gate bias. Pdiblc2 is
usually very small (may be as small as 8.0E-3). If Pdiblc2 is placed into the
threshold voltage model, it will not cause any significant change. However
it is an important parameter in VADIBL for long channel devices, because
Pdiblc2 will be dominant in Eq. (2.6.8) if the channel is long.
Body Effect
(2.6.9)
Esat L + Vdsat + 2 Rds vsat Cox W ( Vgst − Abulk Vds / 2 )
VAsat =
1 + Abulk Rds vsat Cox W
(2.6.10)
1 1
VA = VAsat + ( + ) −1
VACLM VADIBL
(2.6.11)
Vds − Vdsat
Idso = Wv sat Cox (Vgst − Abulk Vdsat )(1 + )
VA
(2.6.12)
PvagVVgs
gsteff 1 1
VA = VAsat + (1 + )( + ) −1
E satL eff VACLM VADIBLC
When the electrical field near the drain is very large (> 0.1MV/cm), some
electrons coming from the source will be energetic (hot) enough to cause
impact ionization. This creates electron-hole pairs when they collide with
silicon atoms. The substrate current Isub thus created during impact
ionization will increase exponentially with the drain voltage. A well known
Isub model [20] is given as:
(2.6.13)
A Bi l
Isub = i Idsat (Vds − Vdsat ) exp( − )
Bi Vds − Vdsat
The parameters Ai and Bi are determined from extraction. Isub will affect
the drain current in two ways. The total drain current will change because it
is the sum of the channel current from the source as well as the substrate
current. The total drain current can now be expressed [21] as follows:
(2.6.14)
I ds = Idso + I sub
(Vds − Vdsat )
= Idso 1 +
Bi Bil
exp( )
Ai Vds − Vdsat
The total drain current, including CLM, DIBL and SCBE, can be written as:
(2.6.15)
Vds − Vdsat Vds − Vdsat
I ds = Wv sat Cox (Vgst − Abulk Vdsat )(1 + )(1 + )
VA VASCBE
where VASCBE can also be called as the Early Voltage due to the substrate
current induced body effect. Its expression is the following:
(2.6.16)
Bi Bil
VASCBE = exp( )
Ai Vds − Vdsat
From Eq. (2.6.16), we can see that VASCBE is a strong function of Vds. In
addition, we also observe that VASCBE is small only when Vds is large.
This is why SCBE is important for devices with high drain voltage bias.
The channel length and gate oxide dependence of VASCBE comes from
Vdsat and l. In BSIM3v3, we replace Bi with PSCBE2 and Ai/Bi with
PSCBE1/L to yield the following expression for VASCBE:
(2.6.17)
1 P P l
= SCBE 2 exp( − SCBE1 )
VASCBE L Vds − Vdsat
(2.7.1)
Vds Vgs − Vth − Voff
I ds = I s 0 (1 − exp( − )) exp( )
vt nv
nvttm
(2.7.2)
W qε si N ch 2
I s0 = µ 0 vt
L 2φ s
(2.7.3)
(Cdsc + CdscdVds + Cdscb Vbseff ) exp( − DVT1
Leff Leff
) + 2 exp(− DVT1 )
Cd 2 lt lt Cit
n = 1 + Nfactor + +
Cox Cox Cox
(2.8.1)
L eff = Ldrawn − 2 dL
(2.8.2a)
Weff = Wdrawn − 2dW
(2.8.2b)
Weff = Wdrawn − 2 dW
The only difference between Eq. (2.8.1a) and (2.8.1b) is that the former includes
bias dependencies. The parameters dW and dL are modeled by the following:
(2.8.3)
dW = dW + dWg Vgsteff + dWb ( φs − Vbseff − φs )
'
Wl Ww W
dW ' = Wint + W ln
+ Wwn + W ln wl Wwn
L W L W
(2.8.4)
L Lw L
dL = Lint + L lln + Lwn + L ln wl Lwn
L W L W
These complicated formulations require some explanation. From Eq. (2.8.3), the
variable Wint models represents the tradition manner from which "delta W" is
extracted (from the intercepts of straights lines on a 1/Rds vs. Wdrawn plot). The
parameters dWg and dWb have been added to account for the contribution of both
front gate and back side (substrate) biasing effects. For dL, the parameter Lint
represents the traditional manner from which "delta L" is extracted (mainly from
the intercepts of lines from a Rds vs. Ldrawn plot).
The remaining terms in both dW and dL are included for the convenience of the
user. They are meant to allow the user to model each parameter as a function of
W(drawn), L(drawn), and their associated product terms. In addition, the freedom
to model these dependencies as other than just simple inverse functions of W and L
is also provide for the user in BSIM3v3. For dW, they are Wln and Wwn. For dL
they are Lln and Lwn.
By default all of the above geometrical dependencies for both dW and dL are
turned off. Again, these equations are provided in BSIM3v3 only for the
convenience of the user. As such, it is up to the user must adopt the correct
extraction strategy to ensure proper use.
Figure 2-7 shows a NMOSFET with a depletion region in the n+ poly-silicon gate.
The doping concentration in the n+ poly-silicon gate is Ngate and the doping
concentration in the substrate is Nsub. The gate oxide thickness is Tox. The depletion
width in the poly gate is Xp. The depletion width in the substrate is Xd. If we
assume the doping concentration in the gate is infinite, then no depletion region
will exist in the gate, and there would be one sheet of positive charge whose
thickness is zero at the interface between the poly-silicon gate and gate oxide.
In reality, the doping concentration is, of course, finite. The positive charge near
the interface of the poly-silicon gate and the gate oxide is distributed over a finite
depletion region with thickness Xp. In the presence of the depletion region, the
voltage drop across the gate oxide and the substrate will be reduced, because part
of the gate voltage will be dropped across the depletion region in the gate. That
means the effective gate voltage will be reduced.
Ngate
Figure 2-7. Charge distribution in a MOSFET with the poly gate depletion effect.
The device is in the strong inversion region.
The effective gate voltage can be calculated in the following manner. Assume the
doping concentration in the poly gate is uniform. The voltage drop in the poly gate
(Vpoly) can be calculated as:
(2.9.1)
Ngate 2
1 qN poly X poly
V poly = X poly E poly =
2 2 ε si
where Epoly is the maximum electrical field in the poly gate. The boundary
condition at the interface of poly gate and the gate oxide is
(2.9.2)
ε ox Eox = ε si E poly = 2 qε si Ngate
polyV poly
where Eox is the electrical field in the gate oxide. The gate voltage satisfies
(2.9.3)
V gs − VFB − φ s = V poly + Vox
where Vox is the voltage drop across the gate oxide and satisfies Vox = EoxTox.
(2.9.4)
a (Vgs − VFB − φ s − V poly ) − V poly = 0
2
where (2.9.5)
2
ε ox
a = --------------------------------------
2
-
2qε si N gate T ox
By solving the equation (2.9.4), we get the effective gate voltage (Vgs_eff) which is
equal to:
(2.9.6)
2
qεqsiεNsigate
N g Tox 2 ε ox2 (V gs − V FB − φ s )
V gs _ eff = V FB + φ s + ox ( 1+ − 1)
ε ox2 qε si N gate T
poly ox
2
Figure 2-8 shows Vgs_eff / Vgs versus the gate voltage. The threshold voltage is
assumed to be 0.4V. If Tox = 40 Å, the effective gate voltage can be reduced by 6%
due to the poly gate depletion effect as the applied gate voltage is equal to 3.5V.
1.00
Tox=80A
80 Å
Vgs_eff / Vgs
Tox=60A
60 Å
Vgs_eff/Vgs
0.95
Tox=40A
To x = 40 Å
0.90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Vgs
V g s (V)
(V)
Figure 2-8. The effective gate voltage versus applied gate voltage at different gate
oxide thickness.
The drain current reduction in the linear region as a function of the gate voltage
can now be determined. Assume the drain voltage is very small, e.g. 50mV. Then
the linear drain current is proportional to Cox(Vgs - Vth). The ratio of the linear drain
current with and without poly gate depletion is equal to:
(2.9.7)
I ds (V gs _ eff ) (V gs _ eff − Vth )
=
I ds (Vgs ) (Vgs − Vth )
Figure 2-9 shows Ids(Vgs_eff) / Ids(Vgs) versus the gate voltage using eq. (2.9.7).
The drain current can be reduced by several percent due to gate depletion.
1.00
Tox=80A
80 Å
Ids(Vgs_eff)/Ids(Vgs)
Ids(Vgs_eff) / Ids(Vgs)
Tox=60A
60 Å
0.95
Tox=40A
To x = 40 Å
0.90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Vgs
V (V)
(V)
gs
Figure 2-9. Ratio of linear region current with poly gate depletion effect and that
without.
The development of separate model expressions for such device operation regimes as
subthreshold and strong inversion were discussed in Chapter 2. Although these
expressions can each accurately describe device behavior within their own respective
region of operation, problems are likely to occur between two well-described regions or
within transition regions. In order to circumvent this issue, a unified model should be
synthesized to not only preserve region-specific expressions but also to ensure the
continuities of current (Ids) and conductance (Gx) and their derivatives in all transition
regions as well. Such high standards are met in BSIM3v3. As a result, convergence and
calculation efficiencies are much improved.
This chapter will describe the unified natured of BSIM3v3’s model equations. While most
of the parameter symbols in this chapter are explained in the following text, a complete
description of all I-V model equation parameters can be found in the Appendix A.
(3.1.1a)
Vgs − Vth
Qchsubs 0 = Q0 exp( )
nvt
where, Q0 is:
(3.1.1b)
qεsiNch Voff
Q0 = vt exp( − )
2φs nvt
(3.1.2)
Qchs 0 = Cox (Vgs − Vth)
In both Eqs. (3.1.1a) and (3.1.2), the parameters Qchsubs0 and Qchs0 are the channel
charge densities at the source for very small Vds. To form a unified expression, an
effective (Vgs-Vth) function named Vgsteff is introduced to describe the channel
charge characteristics from subthreshold to strong inversion:
(3.1.3)
Vgs − Vth
2 n vt ln 1 + exp( )
Vgsteff = 2 n vt
2 Φs Vgs − Vth − 2Voff
1 + 2 n COX exp( − )
qεsiNch 2 n vt
The unified channel charge density at the source end for both subthreshold and
inversion region can therefore be written as:
(3.1.4)
Qchs 0 = CoxVgsteff
Figures 3-1 and 3-2 show the "smoothness" of Eq. (3.1.4) from subthreshold to
strong inversion regions. The Vgsteff expression will be used again in subsequent
sections of this chapter to model the drain current.
3.0
2.5
Vgsteff Function
2.0
exp[(Vgs-Vth)/n*vt]
1.5
Vgsteff (V)
1.0
0.5
0.0
Vgs=Vth
-0.5
-1.0
(Vgs-Vth)
-1.5
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Vgs-Vth
Vgs-Vth (V)
(V)
2
Log(Vgsteff)
-2
(Vgs-Vth)
Log(Vgsteff)
-4
-6
-8
exp[(Vgs-Vth)/n*vt]
-10
-12
-14
Vgs=Vth
-16
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
Vgs-Vth
Vgs-Vth(V)(V)
Eq. (3.1.4) serves as the cornerstone of the unified channel charge expression at the
source for small Vds. To account for the influence of Vds, the Vgsteff function
must keep track of the change in channel potential from the source to the drain. In
other words, Eq. (3.1.4) will have to include a y dependence. To initiate this
formulation, consider first the re-formulation of channel charge density for the
case of strong inversion:
(3.1.5)
Qchs ( y ) = Cox (Vgs − Vth − AbulkVF ( y ))
The parameter VF(y) stands for the quasi-Fermi potential at any given point, y,
along the channel with respect to the source. This equation can also be written as:
(3.1.6)
Qchs ( y ) = Qchs 0 + ∆Qchs ( y )
The term ∆Qchs(y) is the incremental channel charge density induced by the drain
voltage at point y. It can be expressed as:
(3.1.7)
∆Qchs ( y ) = − CoxAbulkVF ( y )
For the subthreshold region (Vgs<<Vth), the channel charge density along the
channel from source to drain can be written as:
(3.1.8)
Vgs − Vth − AbulkVF ( y )
Qchsubs ( y ) = Q0 exp( )
nvt
AbulkVF ( y )
= Qchsubs 0 exp( − )
nvt
A Taylor series expansion of the right-hand side of Eq. (3.1.8) yields the following
(keeping only the first two terms):
(3.1.9)
AbulkVF ( y )
Qchsubs ( y ) = Qchsubs 0(1 − )
nvt
(3.1.10)
Qchsubs ( y ) = Qchsubs 0 + ∆Qchsubs ( y )
(3.1.11)
AbulkVF ( y )
∆Qchsubs ( y ) = − Qchsubs 0
nvt
Note that Eq. (3.1.9) is valid only when VF(y) is very small, which is maintained,
fortunately, due to the fact that Eq. (3.1.9) is only used in the linear regime (i.e.
Vds ≤2vt).
Eqs. (3.1.6) and (3.1.10) both have drain voltage dependencies. However, they are
decuple and a unified expression for Qch(y) is desperately needed. To obtain a
unified expression along the channel, we first assume:
(3.1.12)
∆ Qchs ( y ) ∆ Qchsubs ( y )
∆Qch ( y ) =
∆Qchs ( y ) + ∆Qchsubs ( y )
Here, ∆Qch(y) is the incremental channel charge density induced by the drain
voltage. Substituting Eq. (3.1.7) and (3.1.11) into Eq. (3.1.12), we obtain:
(3.1.13)
VF ( y )
∆Qch( y ) = Qchs 0
Vb
(3.1.14)
Vgsteff + 2 vt
Vb =
Abulk
(3.1.15)
VF ( y )
Qch( y ) = Qchs 0(1 − )
Vb
(Mobmod=1) (3.2.1)
µo
µeff =
Vgsteff + 2Vth Vgsteff + 2Vth 2
1 + (Ua + Uc Vbseff )( ) + Ub ( )
TOX TOX
To account for depletion mode devices, another mobility model option is given by
the following:
(Mobmod=2) (3.2.2)
µo
µeff =
Vgsteff Vgsteff 2
1 + (Ua + UcVbseff )( ) + Ub ( )
TOX TOX
To consider the body bias dependence of Eq. 3.2.1 further, we have introduced the
following expression:
µo
µeff =
Vgsteff + 2Vth Vgsteff + 2Vth 2
1 + [Ua ( ) + Ub ( ) ](1 + UcVbseff )
TOX TOX
Generally, the following expression [2] is used to account for both drift and
diffusion current:
(3.3.1)
dVF ( y )
Id ( y ) = WQch( y ) µne( y )
dy
(3.3.2)
µeff
µne ( y ) =
Ey
1+
Esat
(3.3.3)
VF ( y ) µeff dVF ( y )
Id ( y ) = WQchso(1 − )
Vb 1 + Ey dy
Esat
Eq. (3.3.3) resembles the equation used to model drain current in the strong
inversion regime. However, it can now be used to describe the current
characteristics in the subthreshold regime when Vds is very small
(Vds<2vt). Eq. (3.3.3) can now be integrated from the source to drain to get
the expression for linear drain current in the channel. This expression is
valid from the subthreshold regime to the strong inversion regime:
(3.3.4)
Vds
WµeffQchs 0Vds(1 − )
Ids 0 = 2Vb
Vds
L(1 + )
Va
The current expression when Rds > 0 can be obtained based on Eq. (2.5.9)
and Eq. (3.3.4). The expression for linear drain current from subthreshold
to strong inversion is:
(3.3.5)
Idso
Ids =
RdsIdso
1+
Vds
(3.4.1)
Idso
Ey =
Idso 2 2 Ids 0 WQchs 0 µeff y
(WQchs 0 µeff − ) −
Esat Vb
(3.4.2)
WµeffQchs 0 EsatLVb
Idsat =
2 L( EsatL + Vb )
Let Vds=Vdsat in Eq. (3.3.4) and set this equal to Eq. (3.4.2), we get the
following expression for Vdsat:
(3.4.3)
EsatL(Vgsteff + 2vt )
Vdsat =
AbulkEsatL + Vgsteff + 2 vt
The Vdsat expression for the extrinsic case is formulated from Eq. (3.4.3)
and Eq. (2.5.10) to be the following:
(3.4.4a)
−b − b 2 − 4ac
Vdsat =
2a
where,
(3.4.4b)
1
a = A bulk 2WeffνsatCoxR DS + ( − 1) Abulk
λ
(3.4.4c)
2
b = − (Vgsteff + 2vt )( − 1) + AbulkEsatLeff + 3 Abulk (Vgsteff + 2vt )WeffνsatCoxRDS
λ
(3.4.4d)
c = (Vgsteff + 2 vt ) EsatLeff + 2(Vgsteff + 2 vt ) WeffνsatCoxR DS
2
(3.4.4e)
λ = A1Vgsteff + A2
(3.5.1)
Ids =
Idso (Vdsat ) 1 + Vds − Vdsat 1 + Vds − Vdsat
RdsIdso( Vdsat ) VA VASCBE
1+
Vdsat
where,
(3.5.2)
PvagVgsteff 1 1
VA = VAsat + (1 + )( + ) −1
E satL eff VACLM VADIBLC
(3.5.3)
AbulkVdsat
EsatLeff + Vdsat + 2 RDSνsatCoxWeffVgsteff [1 − ]
2(Vgsteff + 2vt )
VAsat =
2 / λ − 1 + RDSνsatCoxWeffAbulk
(3.5.4)
AbulkEsatLeff + Vgsteff
VACLM = (Vds − Vdsat )
PCLMAbulkEsat litl
(3.5.5)
(Vgsteff + 2vt ) AbulkVdsat
VADIBLC = 1 −
θrout(1 + PDIBLCBVbseff ) AbulkVdsat + Vgsteff + 2 vt
(3.5.6)
Leff Leff
θrout = PDIBLC1 exp( − DROUT ) + 2 exp( − DROUT ) + PDIBLC 2
2 lt 0 lt 0
(3.5.7)
− Pscbe1 litl
exp
1 Pscbe2
=
VASCBE Leff Vds − Vdsat
(3.6.1)
Ids =
Idso( Vdseff ) 1 + Vds − Vdseff 1 + Vds − Vdseff
RdsIdso (Vdseff ) VA VASCBE
1+
Vdseff
Most of the previous equations which contain Vds and Vdsat dependencies are now
substituted with the Vdseff function. For example, Eq. (3.5.4) now becomes:
(3.6.2)
AbulkEsatLeff + Vgsteff
VACLM = (Vds − Vdseff )
PCLMAbulkEsat litl
(3.6.3)
1 Pscbe 2 − Pscbe1 litl
= exp
VASCBE Leff Vds − Vdseff
(3.6.4)
Vdseff
1
(
= Vdsat − Vdsat − Vds − δ + (Vdsat − Vds − δ ) 2 + 4δVdsat
2
)
The expression for Vdsat is that given under Section 3.4. The parameter δ is an
extracted constant. The dependence of Vdseff on Vds is given in Figure 3-3. The
Vdseff function follows Vds in the linear region and tends to Vdsat in the
saturation region. Figure 3-4 shows the effect of δ on the transition region between
linear and saturation regimes.
1.4
Vdseff=Vdsat Vdseff=Vds
1.2
1.0
0.8 Vgs=1V
Vdseff (V)
Vgs=3V
0.6 Vgs=5V
0.4
0.2
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vds (V)
Figure 3-3. Vdseff vs. Vds for δ=0.01 and different Vgs.
Vdseff=Vdsat Vdseff=Vds
2.0
1.5 δ =0.05
δ =0.01
Vdseff (V)
1.0 δ =0.001
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vds (V)
Figure 3-4. Vdseff vs. Vds for Vgs=3V and different δ values.
(3.7.1)
αo βo Idso Vds − Vdseff
Isub = (Vds − Vdseff ) exp( − ) 1 +
Leff Vds − Vdseff RdsIdso VA
1+
Vdseff
(3.8.1)
Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ 1) 2 − 4δ 1Vbc ]
where δ1= 0 .0 0 1 .
Previous BSIM capacitance models used long channel charge models in which the ratio of
Cij/Leff (where i and j are the transistor nodes) did not scale with Leff. This resulted in an
overestimation of capacitance values for devices smaller than a Ldrawn of 2 µm. This
effect was particularly severe at low drain biases. In addition, previous capacitance
models also showed appalling discontinuities for the gate capacitance at threshold voltage.
These factors as wells as others necessitated the development of a new charge and
capacitance model.
• Separate effective channel length and width are used for capacitance and I-V
models.
• A simple short channel capacitance model with accuracy down to the 0.2 µm
Leff range.
• Intrinsic C-V model is no longer piece-wise (i.e. divided into inversion,
depletion, triode and saturation regions). Instead, a single equation is used for
each nodal charge covering all regions of operation. This ensures continuity of
all derivatives and enhances convergence properties. The inversion
In the previous C-V model (BSIM3 Version 2.0), both the I-V and C-V parts of the
model used the same Leff and Weff expressions.. This is not so in the new model
BSIM3v3. The geometry dependence for the intrinsic capacitance part is given as
the following:
(4.2.1)
Wl Ww Wwl
δWeff = DWC + Wln
+ Wwn + W ln Wwn
L W L W
(4.2.2)
Ll Lw Lwl
δLeff = DLC + L ln
+ Lwn + L ln Lwn
L W L W
(4.2.3)
Lactive = Ldrawn − 2δLeff
(4.2.4)
Wactive = Wdrawn − 2δWeff
The meanings of DWC and DLC are different from those of Wint and Lint in the I-
V model. Lactive and Wactive are the effective length and width of the intrinsic
device for capacitance calculations. Unlike the case with I-V, we assumed that
these dimensions have no voltage bias dependence. The parameter δLeff is equal
to the source/drain to gate overlap length plus the difference between drawn and
actual POLY CD due to processing (gate printing, etching and oxidation) on one
side. Overall, a distinction should be made between the effective channel length
extracted from the capacitance measurement and from the I-V measurement.
There has been no recent major work performed in the area of intrinsic
capacitance modeling suitable for implementation into a circuit simulator.
One bottleneck is the difficulty in capacitance measurement, especially in
the deep micron regime. At very short channel lengths, the MOSFET
intrinsic capacitance is very small yet the conductance is large. The large
conductance results in large in-phase currents during high frequency
measurement and overloads the C-V meter. Also the effects of the parasitic
inductance in the experimental setup will be more profound. Moreover,
since charge can only be measured at high impedance nodes (i.e. the gate
and substrate nodes), only 8 of the 16 capacitance components in an
intrinsic MOSFET, can be directly measured.
Similar to the I-V model, the development of the capacitance model was
carried out with an effort to balance physics with simulation efficiency.
Several physical models have been published. These were either too
complicated or lacked continuity from one operation region to another. A
good model should be simple yet include most of the physical concepts.
The accumulation charge and the substrate charge are associated with the
substrate node while the channel charge comes from the source and drain
nodes:
(4.3.1)
Qg = −(Qsub + Qinv + Qacc )
Qb = Qacc + Qsub
Q = Q + Q
inv s d
The substrate charge can be divided into two components - the substrate
charge at zero source-drain bias (Qsub0), which is a function of gate to
(4.3.2)
Q g = −(Qinv + Qacc + Qsub0 + δQsub )
The total charge is computed by integrating the charge along the channel.
The threshold voltage along the channel is modified due to the non-
uniform substrate charge by:
(4.3.3)
Vth ( y ) = Vth ( 0 ) + ( Abulk − 1 )Vy
(4.3.4)
L active Lactive
(
therefore Qg = Wactive ∫ q g dy =Wactive Cox ∫ Vgt + Vth − VFB − φ s − Vy dy )
0 0
Lactive L active
(
Qb = Wactive ∫ qb dy = − WactiveCox ∫ Vth − VFB − φ s − (1 − Abulk )Vy dy
)
0 0
dV y
dy =
εy
and
(4.3.5)
µ eff Cox
J ds =
Lactive
(V gt −
Abulk
2 ) ( )
Vds Vds = µ eff Cox Vgt − AbulkVds ε y
(4.3.6)
Q = −W L C V − Abulk V +
2 2
Abulk Vds
c active active ox
gt 2
ds
A
12Vgt − bulk Vds
2
n Qb = − Qg − Qc = Qsub 0 + δQsub
Q = − Q + W L C V − Vds +
2
Abulk Vds
active active ox gt
g sub 0
2 Abulk
12Vgt − Vds
2
where,
(4.3.7)
Qsub 0 = −Wactive Lactive 2ε Si qN b (2φ b − Vbs )
2
1 − Abulk V − (1 − Abulk ) AbulkVds
e
δQsub = Wactive Lactive Cox
ds
2 A
12Vactive − bulk Vds
2
The inversion charges are supplied from the source and drain electrodes
such that Qinv = Qs + Qd. The ratio of Qd and Qs is the charge partitioning
ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60
(XPART = 0, 0.5 and 1) which are the ratios of Qd to Qs in the saturation
region. We will revisit charge partitioning in Section 4.3.4.
(4.3.8)
∂Qi
Cij =
∂V j
∑C
i
ij = ∑ Cij = 0
j
(4.3.9)
Vgsteff ,cv
Vdsat ,iv < Vdsat ,cv < Vdsat ,iv Lactive →∞
=
Abulk
(4.3.10a)
Vgsteff ,cv
cdsat ,cv =
Vdsat,cv
CLC CLE
Abulk 1 +
L
active
(4.3.10b)
V gs – Vth
V gsteff ,cv = nv t ln 1 + exp ----------------------
nv t
The parameter Abulk can now be substituted by Abulk' in the long channel
equation where:
(4.3.11)
CLC CLE
(4.3.11a)
K1 A0 Leff Bo 1
Abulk 0 = 1 + { + }
2 Φs − Vbseff Leff + 2 XJXdep Weff ' + B1 1 + KETA Vbseff
By setting CLC to zero, the new model reduces back to the old model. At
very short channel lengths where velocity overshoot is prominent, the
channel charges is only a weak function of channel length and saturation
velocity. The effect of velocity overshoot is minimal and is not
implemented into the model.
In the old formulation, the capacitance is divided into four regions. There
were separate equations modeling the nodal charges in each region. From
one region to another the charges were conserved, but not their slopes.
Therefore, the capacitances in some of these transitions were
discontinuous. In the new model, a single equation is used to model each
charge for all regions.
(4.3.12)
( ) (
Q ( inv ,s ,d ) V gt = Q( inv ,s ,d ) V gsteff ,cv))
Now,
(4.3.13)
∂Vgxt
( ) (
C (inv ,s ,d ),g Vgt = C(inv ,s ,d ),g Vgsteff,cv
gsteff ) ∂Vgs
C ( ) (
(inv ,s ,d ),(s ,d ,b ) Vgt = C(inv ,s ,d ),(s ,d ,b ) Vgsteff,cv
gsteff )
where,
(4.3.14)
V gst
∂V gsteff ,cv exp --------- -
nv t
-------------------------- = -------------------------------------------
∂Vgs V gst
1 + exp ----------
nv t
(4.3.16)
{
V FBeff = vfb − 0.5 V3 + V3 2 + 4δ 3 vfb } where V3 = vfb − Vgb − δ 3 ; δ 3 = 0.02
(4.3.16a)
vfb = V th − φs − K 1 φs
(4.3.17)
(
Qacc = − Wactive L active C ox VFBeff − vfb )
(4.3.18)
A parameter Vcveff is used to smooth out the transition between linear and
saturation regions. It affects the inversion charge.
(4.3.19)
{
Vcveff = Vdsat ,cv − 0.5 V4 + V4 2 + 4δ 4 Vdsat , cv } where V4 = Vdsat , cv − Vds − δ 4 ; δ 4 = 0.02
(4.3.20)
2 2
Abulk ' Abulk ' Vcveff
Qinv = −Wactive Lactive Cox Vgsteff ,cv− Vcveff +
2 A '
12Vgsteff ,cv− bulk Vcveff
2
Below is a list of all he three partitioning schemes for the inversion charge:
(4.3.21)
2
1 − Abulk ' (1 − Abulk ' ) Abulk ' Vcveff
δQsub = Wactive Lactive Cox Vcveff −
2 A '
12Vgsteff ,cv− bulk Vcveff
2
(4.3.22)
2 2
Wactive Lactive Cox Abulk ' Abulk ' Vcveff
Qs = Qd = 0 .5Qinv =− V − V +
2 gsteff,cv 2 cveff Abulk '
12Vgsteff ,cv− Vcveff
2
This is the most physical model of the three partitioning schemes in which
the channel charges are allocated to the source and drain electrodes by
assuming a linear dependence to the distance.
(4.3.23)
Lactive
y
Qs = Wactive ∫ q c 1 − dy
Lactive
0
Lactive
Q = W y
active ∫ q c dy
d
0
Lactive
(4.3.24)
( ) ( ) ( )
Abulk ' Vcveff
Wactive LactiveCox 4 2 2 2 3
Qs = − 2 Vgsteffcv − Vgstefcvf Abulk ' Vcveff + Vgsteff Abulk ' Vcveff
3 2
−
2Vgsteff cv − bulk Vcveff
A ' 3 3 15
2
(4.3.25)
( ) ( ) ( )
Abulk ' Vcveff
Wactive LactiveCox 5 2 1 3
Qd = − 2 Vgsteffcv − Vgsteff cv Abulk ' Vcveff + Vgsteff cv Abulk ' Vcveff
3 2
−
2Vgsteffcv − bulk Vcveff
A ' 3 5
2
(4.3.26)
V ( )
2
Abulk ' Vcveff Abulk ' Vcveff
Qs = − Wactive Lactive Cox + −
gsteff,cv
gstefcvf
2 4 Abulk '
24 Vgsteff,cv − Vcveff
gsteffcv 2
(4.3.27)
V ( )
2
3 Abulk ' Vcveff Abulk ' Vcveff
Qd = − Wactive Lactive Cox − +
gsteff,cv
gsteffcv
2 4 Abulk '
8 Vgsteff,cv − Vcveff
gsteffcv 2
The effects of body bias and DIBL is included in the capacitance model by
modifying the threshold voltage to make it consistent with the I-V model.
In deriving the capacitances additional differentiations are need to account
for the dependence of threshold voltage on drain and substrate biases. The
intrinsic capacitances can be derived based on the above charge equations.
(4.3.28)
∂Qs , d ,g ,b ∂Vgsteffcv
C( s, d , g, b ),g =
∂Vgsteffcv ∂Vgt
(4.3.29)
∂Qs, d , g ,b ∂Qs, d , g ,b ∂Vgsteffcv ∂Vth ∂Vth
C( s , d , g , b ) , s = − + +
∂Vds ∂Vgsteffcv ∂Vgt ∂Vds ∂Vbs
(4.3.30)
∂Qs , d ,g , b ∂Qs , d ,g , b ∂Vgsteffcv ∂Vth
C( s ,d ,g ,b ), d = −
∂Vds ∂Vgsteff cv ∂Vgt ∂Vds
(4.3.31)
∂Qs , d ,g, b ∂Qs ,d , g,b ∂Vgsteffcv ∂Vth
C( s ,d , g,b ), b = −
∂Vbs ∂Vgsteff cv ∂Vgt ∂Vbs
(4.4.1)
ε ox t poly π
CF = ln 1 + α=
α t ox 2
(4.4.2)
2ε ox 4 × 10 −7
CF = ln 1 +
π t ox
(4.5.1)
Qoverlap, s CKAPPA 4 Vgs,overlap
= CGS0Vgs + CGS1Vgs − Vgs,overlap +− −1 + 1 +
Wactive 2 CKAPPA
(4.5.2)
1
( ) (V )
2
Vgs ,overlap = V gs − δ 1 + gs −δ1 − 4δ 1 where δ 1 = 0 .02
2
where CKAPPA is a user input parameter. If the average doping in the LDD region
is known, CKAPPA can be calculated by:
2eSi qN LDD
2
Cox
(4.5.3)
Qoverlap, d CKAPPA 4Vgd, overlap
= CGD0 Vgd + CGD1Vgd − Vgd ,overlap +− −1 + 1 +
Wactive 2 CKAPPA
(4.5.4)
1
( ) (V )
2
Vgd ,overlap = Vgd − δ 2 + gd −δ2 − 4δ where δ 2 = 0 .02
2 2
(4.5.5)
(
Qoverlap ,g = − Qoverlap ,s + Qoverlap ,d )
In the above expressions, if CGS0 and CGD0 (the heavily doped S/D region to
gate overlap capacitance) are not given, they are calculated according to the
following:
CGD0 = (DLC*Cox) - CGD1 (if DLC is given and DLC > CGD1/Cox)
0.5
0.0 ∆Qb
-0.5
Qd (60%)
Q/(W*L*Cox))
-1.0
Qb (sum)
Qs (40%)
-1.5
Qinv
-2.0
-2.5 Q (sum)
-3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Vds (V)
0.7
0.6
C (sum)
0.5
Cinv
0.4
C/(W*L*Cox))
0.3
Cd (40%)
0.2
0.1
Cs (60%)
0.0
-0.1
∆ Cb
-0.2
2
Qs (60%)
Qd (40%)
1 ∆ Qb
Qacc
Q/(W*L*Cox))
0
Qb0
-1
-2 Qb (sum)
Qinv
-3
Q(sum)
-4
-4 -3 -2 -1 0 1 2 3 4
Vgs
Vgs (V)(V)
1.0
0.8 C (sum)
Cacc
C/(W*L*Cox))
0.6
Cinv
Cs (60%)
0.4
Cd (40%)
Cb
0.2
Cb (sum)
0.0
∆ Cb
-4 -3 -2 -1 0 1 2 3 4
Vgs
Vgs(V)(V)
3
Vfbeff Comp
Vfbeff (V) 2
-1
-2 Vfbeff
-3
-4
-4 -3 -2 -1 0 1 2 3 4
Vgb
Vgs(V)(V)
The NQS model also includes the use of the model parameter Xpart (usually
associated with the A.C. model) to control charge partition to the source/drain. In
BSIM3v3, the Elmore resistance, RElmore, is calculated from the channel resistance
under strong inversion as:
(5.2.1)
2 2
L eff L eff
- ≈ ---------------------------
R Elmore = ---------------------
εµ eff Q ch εµ eff Q cheq
where ε is the Elmore constant of the RC network in the channel with a theoretical
value close to 5. Qch is the actual channel charge in the channel and Qcheq
represents the quasi-static equilibrium channel charge. The value RElmoreCChannel
is the relaxation time constant for charging and discharging the channel. Under
strong inversion, the conduction is mainly due to drift current. As such, the
relaxation time constant due to drift current is given by:
(5.2.2)
3
CoxWeff Leff
τ drift ≈ RElmore CoxWeff Leff ≈
εµ eff Qcheq
(5.2.3)
q ( Leff / 4 ) 3
τ diff ≈
µ eff kT
The overall relaxation time for channel charging and discharging is given by the
combination of both the diffusion and the drift terms:
(5.2.4)
1 1 1
= +
τ τ diff τ drift
Using this relaxation time concept, the NQS transient effect in BSIM3v3 is
implemented with the subcircuit given in Figure 5-2. The parameters Xd and Xs are
the charge partition allocated to the drain and source and are assigned values of 0.4
and 0.6, respectively.
The state variable, Qdef, is an additional node created to keep track of the amount
of deficit (or surplus) channel charge necessary to achieve equilibrium . Qdef will
decay exponentially into the channel with a bias dependent NQS relaxation time τ.
The derivative of Qdef with respect to time is the gate charging current. This gate
current is partitioned into separate drain and source current components. A
complete list of all NQS model equations is provided in the Appendix.
Qdef
Qdef
id = Id ( dc) + Xd
τ
∂Q ∂Q eq
cheq Qdef
------------------ X s + Xd = 1
∂∂tt τ
Qdef
is = − Id ( dc) + Xs
τ
device performance quite well. Values extracted in this manner will now have
some physical relevance.
BSIM3v3 uses group device extraction strategy. This requires measured data from
devices with different geometries. All devices are measured under the same bias
conditions. The resulting fit might not be absolutely perfect for any single device
but will be better for the group of devices under consideration.
One large size device and two sets of smaller-sized devices are needed to
extract parameters, as shown in Figure 6-1.
W Large W and L
W min
L
Lmin
3) Ids vs. Vgs@ Vds = Vdd with different Vbs. (Vdd is the maximum drain
voltage)
4) Ids vs. Vds@ Vbs = Vbb with different Vgs. (|Vbb| is the maximum body
bias)
6.3.2 Optimization
(6.3.1)
∂ f ∂ f ∂f
fexp ( P10, P20, P30 ) − fsim ( P1( m ) , P2( m ) , P3( m ) ) = sim ∆P1m + sim ∆P2m + sim ∆P3m
∂ P1 ∂ P2 ∂ P3
Initial Guess of
Parameters P i
Model Equations
∆P i
P (m+1)= P (m)
+ ∆ P
i i i
∆P no
< δ
i
(m)
P i
yes
STOP
To change Eq. (6.3.1) into a form that a linear least-squares fit routine can
be use (i.e. in a form of y = a + bx1 + cx2), both sides of the Eq. (6.3.1) are
divided by ∂fsim / ∂P1. This gives the change in P1, ∆P1(m) , for the next
iteration such that:
(6.3.2)
Pi( m + 1) = Pi( m ) + ∆Pi( m )
where i=1, 2, 3 for this example. The (m+1) parameter values for P2 and P3
are obtained in an identical fashion. This process is repeated until the
incremental parameter change in parameter values ∆Pi(m) are smaller than a
pre-determined value. At this point, the parameters P1, P2, and P3 have
been extracted.
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Step 8
Step 9
Step 10
Step 11
Step 12
Step 13
Step 14
Step 15
Step 16
Step 17
Step 18
Step 19
Step 20
Step 21
Step 22
Below is a list of model parameters which have special notes for parameter
extraction.
vth0 Threshold voltage for large W and L device @ 0.7 (NMOS) V nI-1
Vbs=0V -0.7 (PMOS)
k1 First order body effect coefficient 0.5 V1/2 nI-2
Vtho = VFB + φs + K1 φs
VFB = Vtho − φs − K 1 φs
K1 = gamma2 − 2 K 2 φs − Vbm
φs = 2vtm 0 ln
Nch
ni
k B Tnom
vtm 0 =
q
.
Tnom 1 5 Eg 0
ni = 1.45 x 10 10 exp 21. 5565981 −
300.15 2vtm 0
7.02x 10 −4 Tnom 2
Eg 0 = 1.16 −
Tnom + 1108
nI-3. If nch is not given and gamma1 is given, nch is calculated from:
gamma12 Cox 2
Nch =
2 qεsi
If both gamma1 and nch are not given, nch defaults to 1.7e23 1/m 3 and
gamma1 is calculated from nch.
2 qε si Nch
gamma1 =
Cox
2 qε si N sub
gamma 2 =
Cox
qNchX t 2
Vbx = φs −
2ε si
cgso=0
cgdo=0
2 ε ox 4 × 10 −7
CF = ln 1 +
π Tox
A series of tests [26] have been performed on BSIM3v3 to check its robustness (lack of
discontinuities), accuracy, and performance. Although all benchmark test results could not
be included in this chapter, the most important ones will be presented in this chapter for a
0.5µm, 90 Angstrom, 3.3V technology.
Figure
Device Size Bias Conditions Notes Number
W/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-1
W/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-2
W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-3
W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-4
W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-5
W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V; Linear scale 7-6
W/L=20/5
W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-7
Figure
Device Size Bias Conditions Notes Number
W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Linear scale 7-8
W/L=20/5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Linear scale 7-9
Vbs=0V
W/L=20/0.5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Linear scale 7-10
Vbs=0V
W/L=20/5 Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to - Linear scale 7-11
3.3V
W/L=20/0.5 Gm/Ids vs. Vgs @ Vds=0.05V; Vbs=0V to - Linear scale 7-12
3.3V
W/L=20/0.5 Ids vs. Vds @Vbs=0V; Vgs=0.5V, 0.55V, BSIM3 Ver- 7-13
0.6V sion 2.0 vs.
BSIM3v3
W/L=20/5 Ids vs. Vds @Vbs=0V; Vgs=1.15V to 3.3V Linear scale 7-14
W/L=20/0.5 Ids vs. Vds @Vbs=0V; Vgs=1.084V to Linear scale 7-15
3.3V
W/L=20/0.5 Rout vs. Vds @ Vbs=0V; Vgs=1.084V to Linear scale 7-16
3.3V
1.E-02
1.E-03
Vds=3.3V
1.E-04
1.E-05
Vds=0.05V
1.E-06
Ids (A)
1.E-07
Solid lines: Model results
1.E-08 Symbols: Exp.data
1.E-09 W/L=20/5
1.E-10 Tox=9 nm
Vbs=0V
1.E-11
1.E-12
0.0 1.0 2.0 3.0 4.0
Vgs (V)
1.8E-03
Solid lines: Model result
1.6E-03
Symbols: Exp.data
1.4E-03 W/L=20/5
1.2E-03 Tox=9 nm
Ids (A)
1.0E-03 Vbs=0V
8.0E-04
6.0E-04 Vds=3.3V
4.0E-04
2.0E-04 Vds=0.05V
0.0E+00
0.0 1.0 2.0 3.0 4.0
Vgs (V)
1.0E+00
1.0E-01
Vds=3.3V
1.0E-02
1.0E-03
1.0E-04
1.0E-05 Vds=0.05V
Ids (A)
1.0E-06
1.0E-07
Solid lines: Model results
1.0E-08
Symbols: Exp. data
1.0E-09
W/L=20/0.5
1.0E-10
Tox=9 nm
1.0E-11
Vbs=0V
1.0E-12
0.0 1.0 2.0 3.0 4.0
Vgs (V)
Figure 7-3. Same as Figure 7-1 but for short channel device.
1.0E-02
9.0E-03 Solid lines: Model results
8.0E-03 Symbols: Exp. data
7.0E-03 W/L=20/0.5
Tox=9 nm
6.0E-03
Ids (A)
Vbs=0V Vds=3.3V
5.0E-03
4.0E-03
3.0E-03
2.0E-03
1.0E-03 Vds=0.05V
0.0E+00
0.0 1.0 2.0 3.0 4.0
Vgs (V)
Figure 7-4. Same as Figure 7-2 but for short channel device.
1.E-03
1.E-04 Vbs=0V
1.E-05
1.E-06 Vbs=-3.3V
Ids (A)
1.E-07
1.E-08
Solid lines: Model results
1.E-09 Symbols: Exp. data
1.E-10 W/L=20/5
Tox=9 nm
1.E-11 Vds=0.05V
1.E-12
0.0 1.0 2.0 3.0 4.0
Vgs (V)
8.1.1 Parameters
There exists two models for flicker noise. One is called as Spice2 flicker
noise model, another one is called as BSIM3 flicker noise model [33,34].
The parameters in the models are listed in Table 8-1.
Symbols Symbols
used in used in Description Default Unit
equation SPICE
Noia noia Noise parameter A (NMOS) 1e20 none
(PMOS) 9.9e18
Noib noib Noise parameter B (NMOS) 5e4 none
(PMOS) 2.4e3
Noic noic Noise parameter C (NMOS) -1.4e-12 none
(PMOS) 1.4e-12
Em em Saturation field 4.1e7 V/m
Af af Frequency exponent 1 none
Ef ef Flicker exponent 1 none
Kf kf Flicker noise parameter 0 none
8.1.2 Expressions
where Vtm is the thermal voltage, µeff is the effective mobiity at the given
bias condition, Leff and Weff are the effective channel length and width,
respectively. The parameter N0 is the charge density at the source given by:
(8.2)
C ox ( V GS – V TH )
N 0 = ----------------------------------------
q
(8.3)
C ox ( V GS – V TH – V D S ′ )
N l = ---------------------------------------------------------
q
V DS ′ = MIN ( V D S, V DSAT )
∆Lclm refers to channel length reduction due to CLM and is given by:
(8.4)
V DS – V DSAT
-----------------------------
Litl
- + Em
Litl × log --------------------------------------------
-
E SAT if VDS > VDSAT
∆ L cl m =
0 otherwise
2 × Vsat
E SAT = ---------------------
u e ff
2. Otherwise,
(8.5)
S l imi t × S wi
FlickerNoise = --------------------------
S li mit + S wi
(8.6)
NoiaVtIds 2
Swi =
WeffLeff f Ef 4 x 10 36
8 kT
( gm + gds + gmb )
3
2. For BSIM3v3 thermal noise model
4 KTµeff
Qinv
Leff 2
Abulk
Qinv = − Weff Leff C ox Vgsteff (1 − Vdseff )
2(Vgsteff + 2vt )
The derivation for this last thermal noise expression is based on the noise
model found in [35].
If the saturation current Isbs is larger than zero, the following equations is
used to calculate the source/bulk diode current:
Vbs<0.5V
(9.1.1)
Vbs
Ibs = Isbs[exp( ) − 1] + G min Vbs
Nvtm
Vbs>0.5V
(9.1.2)
(9.1.3)
(9.1.4a)
Eg0 Eg T
− + XTI ln( )
Js = Js 0 exp[ Vtm 0 Vtm Tnom ]
Nj
(9.1.4b)
Eg0 Eg T
− + XTI ln( )
Jssw = Js0sw exp[ Vtm0 Vtm Tnom
]
Nj
(9.1.5)
7.02e −4 T 2
Eg = 116
. −
T + 1108.0
where Js0 is the saturation current density at Tnom. If Js0 is not given in
the simulation, Js0=1.e-4A/m2. Js0sw is the sidewall saturation current
density at Tnom. The default value of Js0sw is 0.
(9.1.6)
If the saturation current Isbd is larger than zero, the following equations is
used to calculate the drain/bulk diode current:
Vbd<0.5V
(9.1.7)
Vbd
Ibd = Isbd[exp( ) − 1] + G min Vbd
Nvtm
Vbd>0.5V
(9.1.8)
(9.1.9)
(9.1.10)
9.1.2 Parameters
The parameters for the DC model of the source/drain diode are listed in
Table 9-1.
Symbols Symbols
used in used in Description Default Unit
equation SPICE
Js0 js Saturation current density 1.e-4 A/m2
Js0sw jssw Side wall saturation current 0 A/m
density
nj nj Emission coefficient 1 none
XTI xti Junction current tempera- 3.0 none
ture exponent coefficient
Source and drain junction capacitance can be divided into two components:
the junction bottom area capacitance Cjb and the junction periphery
capacitance Cjp. The formula for both the capacitances is similar, but with
different model parameters. The equation of Cjb includes the parameters
such as Cj, Mj, and Pb. The equation of Cjp includes the parameters such
as Cjsw, Mjsw, Pbsw, Cjswg, Mjswg, Pbswg.
If Ps >Weff
(9.2.1a)
Otherwise:
(9.2.1b)
C a p b s = A S C jb s + P S C jb s s w g
if Vbs<0
(9.2.2)
Vbs − Mj
Cjbs = Cj (1 − )
Pb
if Vbs>0
(9.2.3)
Vbs
Cjbs = Cj (1 + Mj )
Pb
If Cjsw is large than zero, Cjbssw is calculated by:
if Vbs<0
(9.2.4)
Vbs − Mswj
Cjbssw = Cjsw(1 − )
Pbsw
if Vbs>0
(9.2.5)
Vbs
Cjbssw = Cjsw(1 + Mjsw )
Pbsw
if Vbs<0
(9.2.6)
Vbs −Mjswg
Cjbsswg = Cjswg(1 − )
Pbswg
if Vbs>0
(9.2.7)
Vbs
Cjbsswg = Cjswg(1 + Mjswg )
Pbswg
If PD > Weff:
(9.2.8a)
C apb d = A D C jb d + ( P D − W e ff ) C jb d sw + W e ff C jb d sw g
Otherwise:
(9.2.8b)
C a p b d = A D C jb d + P D C jb d s w g
if Vbd<0
(9.2.9)
Vbd − Mj
Cjbd = Cj (1 − )
Pb
if Vbd>0
(9.2.10)
Vbd
Cjbd = Cj (1 + Mj )
Pb
if Vbd<0
(9.2.11)
Vbd − Mswj
Cjbdsw = Cjsw (1 − )
Pbsw
if Vbd>0
(9.2.12)
Vbd
Cjbdsw = Cjsw(1 + Mjsw )
Pbsw
if Cjswg is larger than zero, Cjbdswg is calculated by:
if Vbd<0
(9.2.13)
Vbd −Mjswg
Cjbdswg = Cjswg(1− )
Pbswg
if Vbd>0
(9.2.14)
Vbd
Cjbdswg = Cjswg(1+ Mjswg )
Pbswg
9.2.2 Parameters
The parameters for the capacitance model of the source/drain diode are
listed in Table 9-2.
Symbols Symbols
used in used in Description Default Unit
equation SPICE
Cj cj Bottom junction capaci- 5e-4 F/m2
tance per unit area at zero
bias
Mj mj Bottom junction capaci- 0.5 none
tance grading coefficient
Pb pb Bottom junction built-in 1.0 V
potential
Cjsw cjsw Source/drain sidewall junc- 5e-10 F/m
tion capacitance grading
coefficient per unit length at
zero bias
Mjsw mjsw Source/drain sidewall junc- 0.33 none
tion capacitance grading
coefficient
Pbsw pbsw Source/drain sidewall junc- 1.0 V
tion built-in potential
Cjswg cjswg Source/drain gate sidwall Cjsw F/m
junction capacitance per
unit length at zero bias
Mjswg mjswg Source/drain gate sidewall Mjsw none
junction capacitance grad-
ing coefficient
Pbswg pbswg Source/drain gate sidewall Pbsw V
junction built-in potential
A.2 DC Parameters
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Vth0 vth0 Threshold voltage @Vbs=0 for 0.7 V nI-1
Large L. (NMOS)
-0.7
(PMOS)
K1 k1 First order body effect coeffi- 0.5 V1/2 nI-2
cient
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
K2 k2 Second order body effect coef- 0.0 none nI-2
ficient
K3 k3 Narrow width coefficient 80.0 none
K3b k3b Body effect coefficient of k3 0.0 1/V
W0 w0 Narrow width parameter 2.5e-6 m
Nlx nlx Lateral non-uniform doping 1.74e-7 m
parameter
Vbm vbm Maximum applied body bias in -3.0 V
Vth calculation
Dvt0 dvt0 first coefficient of short-chan- 2.2 none
nel effect on Vth
Dvt1 dvt1 Second coefficient of short- 0.53 none
channel effect on Vth
Dvt2 dvt2 Body-bias coefficient of short- -0.032 1/V
channel effect on Vth
Dvt0w dvt0w First coefficient of narrow 0 1/m
width effect on Vth for small
channel length
Dvt1w dvtw1 Second coefficient of narrow 5.3e6 1/m
width effect on Vth for small
channel length
Dvt2w dvt2w Body-bias coefficient of narrow -0.032 1/V
width effect for small channel
length
µ0 u0 Mobility at Temp = Tnom
NMOSFET 670.0 cm2/V/
PMOSFET 250.0 sec
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Ua ua First-order mobility degrada- 2.25E-9 m/V
tion coefficient
Ub ub Second-order mobility degrada- 5.87E-19 (m/V)2
tion coefficient
Uc uc Body-effect of mobility degra- mobmod m/V2
dation coefficient =1, 2:
-4.65e-11
mobmod
=3:
-0.046 1/V
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Wr wr Width Offset from Weff for Rds 1.0 none
calculation
Wint wint Width offset fitting parameter 0.0 m
from I-V without bias
Lint lint Length offset fitting parameter 0.0 m
from I-V without bias
dWg dwg Coefficient of Weff’s gate 0.0 m/V
dependence
dWb dwb Coefficient of Weff’s substrate 0.0 m/V 1/2
body bias dependence
Voff voff Offset voltage in the subthresh- -0.08 V
old region at large W and L
Nfactor nfactor Subthreshold swing factor 1.0 none
Eta0 eta0 DIBL coefficient in subthresh- 0.08 none
old region
Etab etab Body-bias coefficient for the -0.07 1/V
subthreshold DIBL effect
Dsub dsub DIBL coefficient exponent in drout none
subthreshold region
Cit cit Interface trap capacitance 0.0 F/m2
Cdsc cdsc Drain/Source to channel cou- 2.4E-4 F/m2
pling capacitance
Cdscb cdscb Body-bias sensitivity of Cdsc 0.0 F/Vm2
Cdscd cdscd Drain-bias sensitivity of Cdsc 0.0 F/Vm2
Pclm pclm Channel length modulation 1.3 none
parameter
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Pdiblc1 pdiblc1 First output resistance DIBL 0.39 none
effect correction parameter
Pdiblc2 pdiblc2 Second output resistance DIBL 0.0086 none
effect correction parameter
Pdiblcb pdiblcb Body effect coefficient of 0 1/V
DIBL correction parameters
Drout drout L dependence coefficient of the 0.56 none
DIBL correction parameter in
Rout
Pscbe1 pscbe1 First substrate current body- 4.24E8 V/m
effect parameter
Pscbe2 pscbe2 Second substrate current body- 1.0E-5 m/V
effect parameter
Pvag pvag Gate dependence of Early volt- 0.0 none
age
δ delta Effective Vds parameter 0.01 V
Ngate ngate poly gate doping concentration 0 cm-3
α0 alpha0 The first parameter of impact 0 m/V
ionization current
β0 beta0 The second parameter of impact 30 V
ionization current
Rsh rsh Source drain sheet resistance in 0.0 Ω/
ohm per square square
Js0sw jssw Side wall saturation current 0 A/m
density
Jso js Source drain junction saturation 1.E-4 A/ m2
current per unit area
Symbols Symbols
used in used in Description
equation SPICE Default Unit Note
Xpart xpart Charge partitioning rate flag 0 none
CGS0 cgso Non LDD region source-gate calculated F/m nC-1
overlap capacitance per
channel length
CGD0 cgdo Non LDD region drain-gate calculated F/m nC-2
overlap capacitance per
channel length
CGB0 cgbo Gate bulk overlap capaci- 0.0 F/m
tance per unit channel length
Cj cj Bottom junction per unit area 5e-4 F/m2
Mj mj Bottom junction capacitance 0.5
grating coefficient
Mjsw mjsw Source/Drain side junction 0.33 none
capacitance grading coeffi-
cient
Cjsw cjsw Source/Drain side junction 5.E-10 F/m
capacitance per unit area
Cjswg cjswg Source/drain gate sidwall Cjsw F/m
junction capacitance grading
coefficient
Mjswg mjswg Source/drain gate sidewall Mjsw none
junction capacitance coeffi-
cient
Symbols Symbols
used in used in Description
equation SPICE Default Unit Note
Pbsw pbsw Source/drain side junction 1.0 V
built-in potential
Pb pb Bottom built-in potential 1.0 V
Pbswg pbswg Source/Drain gate sidewall Pbsw V
junction built-in potential
CGS1 cgs1 Light doped source-gate 0.0 F/m
region overlap capacitance
CGD1 cgd1 Light doped drain-gate region 0.0 F/m
overlap capacitance
CKAPPA ckappa Coefficient for lightly doped 0.6 F/m
region overlap
capacitance Fringing field
capacitance
Cf cf fringing field capacitance calculated F/m nC-3
CLC clc Constant term for the short 0.1E-6 m
channel model
CLE cle Exponential term for the short 0.6 none
channel model
DLC dlc Length offset fitting parame- lint m
ter from C-V
DWC dwc Width offset fitting parameter wint m
from C-V
Vfb vfb Flat-band voltage parameter -1 V
(for capmod=0 only)
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Elm elm Elmore constant of the channel 5 none
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Wl wl Coefficient of length depen- 0.0 mWln
dence for width offset
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Tnom tnom 27 oC
Temperature at which parame-
ters are extracted
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Noia noia Noise parameter A (NMOS) 1e20 none
(PMOS) 9.9e18
Noib noib Noise parameter B (NMOS) 5e4 none
(PMOS) 2.4e3
Noic noic Noise parameter C (NMOS) -1.4e- none
12
(PMOS) 1.4e-12
Em em Saturation field 4.1e7 V/m
Af af Frequency exponent 1 none
Ef ef Flicker exponent 1 none
Kf kf Flicker noise parameter 0 none
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Tox tox Gate oxide thickness 1.5e-8 m
Xj xj Junction Depth 1.5e-7 m
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Symbols Symbols
used in used in Description Default Unit Note
equation SPICE
Lmin lmin Minimum channel length 0.0 m
Vtho = VFB + φs + K1 φs
VFB = Vtho − φs − K 1 φs
K1 = gamma2 − 2 K 2 φs − Vbm
φs = 2vtm 0 ln
Nch
ni
k B Tnom
vtm 0 =
q
.
Tnom 1 5 Eg 0
ni = 1.45 x 10 10 exp 21. 5565981 −
300.15 2vtm 0
7.02x 10 −4 Tnom 2
Eg 0 = 1.16 −
Tnom + 1108
nI-3. If nch is not given and gamma1 is given, nch is calculated from:
gamma12 Cox 2
Nch =
2 qεsi
If both gamma1 and nch are not given, nch defaults to 1.7e23 1/m 3 and
gamma1 is calculated from nch.
2 qε si Nch
gamma1 =
Cox
2 qε si N sub
gamma 2 =
Cox
qNchX t 2
Vbx = φs −
2ε si
cgso=0
cgdo=0
2 ε ox 4 × 10 −7
CF = ln 1 +
π Tox
− exp( − Dsub
Leff Leff
) + 2 exp( − Dsub ) ( Etao + EtabVbseff ) Vds
2lto lto
2εsi(Φs − Vbseff )
Xdep =
qNch
2εsiΦs
Xdep 0 =
qNch
(δ1=0.001)
Vbseff = Vbc + 0.5[Vbs − Vbc − δ 1 + (Vbs − Vbc − δ 1) 2 − 4δ 1Vbc ]
K12
Vbc = 0.9(φs − )
4K 2 2
NchNDS
Vbi = vt ln( )
ni 2
Vgs − Vth
2 n vt ln 1 + exp(
2 n vt
)
Vgsteff =
2 Φs Vgs − Vth − 2Voff
1 + 2 n COX exp( − )
qεsiNch 2 n vt
εsi
Cd =
Xdep
B.1.3 Mobility
For Mobmod=1
µo
µeff =
V gsteff + 2Vth Vgsteff + 2Vth 2
1 + (Ua + Uc Vbseff )( ) + Ub ( )
TOX TOX
For Mobmod=2
µo
µeff =
Vgsteff Vgsteff 2
1 + (Ua + UcVbseff )( ) + Ub ( )
TOX TOX
For Mobmod=3
µo
µeff =
Vgsteff + 2Vth Vgsteff + 2Vth 2
1 + [Ua ( ) + Ub ( ) ](1 + UcVbseff )
TOX TOX
−b − b 2 − 4ac
Vdsat =
2a
1
a = A bulk 2WeffνsatCoxR DS + ( − 1) A bulk
λ
2
b = − (Vgsteff + 2vt )( − 1) + AbulkEsatLeff + 3 Abulk (Vgsteff + 2vt )WeffνsatCoxRDS
λ
λ = A1Vgsteff + A2
K1 A0 Leff Leff Bo 1
Abulk = (1 + { [1 − AgsVgsteff ( )2 ] + })
2 Φs − Vbseff Leff + 2 XJXdep Leff + 2 XJXdep Weff ' + B1 1 + KETA Vbseff
2νsat
E sat =
µeff
Vdseff = Vdsat −
1
2 (
Vdsat − Vds − δ + (Vdsat − Vds − δ ) 2 + 4δVdsat )
Ids =
Idso ( Vdseff ) 1 + Vds − Vdseff 1 + Vds − Vdseff
RdsIdso( Vdseff ) VA VASCBE
1+
Vdseff
Vdseff
WeffµeffCoxVgsteff (1 − A bulk )Vdseff
2(Vgsteff + 2vt )
Idso =
Leff [1 + Vdseff / ( EsatLeff )]
PvagVgsteff 1 1
VA = VAsat + (1 + )( + ) −1
E satLeff VACLM VADIBLC
AbulkEsatLeff + Vgsteff
VACLM = (Vds − Vdseff )
PCLMAbulkEsat litl
Leff Leff
θrout = PDIBLC1 exp( − DROUT ) + 2 exp( − DROUT ) + PDIBLC 2
2 lt 0 lt 0
AbulkVdsat
EsatLeff + Vdsat + 2 RDSνsatCoxWeffVgsteff [1 − ]
2(Vgsteff + 2vt )
VAsat =
2 / λ − 1 + RDSνsatCoxWeffAbulk
ε si Tox X j
litl =
ε ox
Ngate 2
1 qN poly X poly
V poly = X poly E poly =
2 2 ε si
2
ε ox
a = --------------------------------------
2
-
2qε si N gate T ox
2
qεqsiεNsigate
N g T ox 2 ε ox2 (V gs − V FB − φ s )
V gs _ eff = V FB + φ s + ox ( 1+ − 1)
ε ox2 qε si N gate 2
poly Tox
L eff = Ldrawn − 2 dL
Weff = Wdrawn − 2 dW
Wl Ww W
dW ' = Wint + W ln
+ Wwn + W ln wl Wwn
L W L W
Ll Lw Lwl
dL = Lint + L ln + Lwn + L ln Lwn
L W L W
B.1.10Drain/Source Resistance
B.1.11Temperature Effects
T µte
µo ( T ) = µo ( Tnorm)( )
Tnorm
T
Rdsw (T ) = Rdsw (Tnorm ) + Pr t( − 1)
Tnorm
Wl Ww Wwl
δWeff = DWC + Wln
+ Wwn + Wln Wwn
L W L W
Ll Lw Lwl
δL eff = DLC + Lln
+ Lwn + Lln Lwn
L W L W
Qoverlap , s
= CGS0Vgs
Wactive
if (Vgs <0)
else
Qoverlap,s
= (CGS0 + CKAPPACGS1) Vgs
Wactive
1
( ) (V )
2
Vgs ,overlap = Vgs − δ 1 + gs −δ1 − 4δ 1 where δ 1 = 0.02
2
Qoverlap,d
= CGD0Vgd
Wactive
if (Vgd <0)
else
Qoverlap,d
= (CGD0 + CKAPPACGD1) Vgd
Wactive
1
( ) (V )
2
Vgd ,overlap = V gd − δ 2 + gd −δ2 − 4δ where δ 2 = 0 .02
2 2
(
Q overlap ,g = − Q overlap ,s + Q overlap ,d )
(
Qg = Wactive Lactive Cox Vgs − Vbs − Vfb )
Qsub = −Qg
Qinv = 0
Qg = −Qb
Qinv = 0
Vgs − Vth
Vdsat ,cv =
Abulk '
CLC CLE
Abulk ' = Abulk 0 1 +
Leff
K1 A0 Leff Bo 1
Abulk 0 = 1 + { + }
2 Φs − Vbs Leff + 2 XJXdep Weff + B1 1 + KETA Vbs
'
if Vds<Vdsat
otherwise
Vdsat
Qg = Wactive Lactive Cox(Vgs − Vfb − Φs − )
3
1
Qs = Qd = − Wactive Lactive Cox(Vgs − Vth )
3
if (Vds <Vdsat)
Qd = −Wactive LactiveCox
(Vgs − Vth ) 2 Abulk ' Vds(Vgs − Vth ) ( Abulk ' Vds )2
Vgs − Vth A ' Abulk ' Vds [ − +
− bulk
Vds + 6 8 40
2 2 A '
(Vgs − Vth − bulk Vds )2
2
Qs = −(Qg + Qb + Qd )
otherwise
Vdsat
Qg = Wactive Lactive Cox(Vgs − Vfb − Φs − )
3
4
Qd = − Wactive Lactive Cox (Vgs − Vth )
15
Qs = − (Qg + Q b + Qd )
if Vds <Vdsat
Vgs − Vth Abulk ' ( Abulk ' Vds ) 2
Qd = − Wactive Lactive Cox + Vds −
2 4 A '
24(Vgs − Vth − bulk Vds)
2
Qs = −(Qg + Qb + Qd )
otherwise
Vdsat
Qg = Wactive Lactive Cox(Vgs − Vfb − Φs − )
3
Qd = 0
Qs = −(Qg + Qb)
if (Vgs <Vfb+Vbs+Vgsteffcv)
(
Qg 1 = − Wactive Lactive Cox Vgs − Vfb − Vbs − Vgsteffcv )
else
Qb 1 = −Qg 1
Vgsteffcv
Vdsat ,cv =
Abulk '
CLC CLE
A bulk '= A bulk 0 1 +
L
eff
K1 A 0 Leff Bo 1
Abulk 0 = 1 + { + }
2 Φs − Vbseff Leff + 2 XJXdep Weff + B1 1 + KETA Vbseff
'
Vgs − Vth
Vgsteffcv = n vt ln 1 + exp(
n vt
)
if (Vds <=Vdsat)
2
Vds Abulk ' Vds
Qg = Qg 1 + Wactive Lactive Cox Vgsteff cv − +
2 Abulk '
12 Vgsteff cv − Vds
2
1− 2
Qb = Qb 1 + Wactive Lactive Cox
Abulk '
Vds −
(1 − Abulk ' )Abulk ' Vds
2 A '
12 Vgsteffcv − bulk Vds
2
W L C A ' 2
Abulk ' Vds 2
Qs = Qd = − active active ox Vgsteff cv − bulk Vds +
2 2 Abulk '
12 Vgsteffcv − Vds
2
Qd = − (Qg + Qb + Qs )
V (
ds )
2
Abulk ' Vds A ' V
Qs = − Wactive Lactive Cox gstefcv
+ −
bulk
2 4 Abulk '
24 Vgsteffcv − Vds
2
Qd = − (Qg + Qb + Qs )
if (Vds >Vdsat)
Qd = − (Qg + Qb + Qs )
2Vgstefcv
Qs = − Wactive Lactive Cox
3
Qd = − (Qg + Qb + Qs )
Q inv = Q s + Q d
{
V FBeff = vfb − 0.5 V3 + V3 2 + 4δ 3 vfb } where V3 = vfb − Vgb − δ 3 ; δ 3 = 0.02
vfb = Vth − φs − K 1 φs
(
Qacc = − Wactive L active C ox VFBeff − vfb )
Vgsteff,cv
Vdsat , cv =
gstefcvf
A bulk '
CLC CLE
Abulk ' = Abulk 0 1 +
Lactive
K1 A0 Leff Bo 1
Abulk 0 = 1 + { + }
2 Φs − Vbseff Leff + 2 XJXdep eff + 1 1 +
'
W B K ETA Vbseff
Vgs − Vth
Vgsteffcv = n vt ln 1 + exp(
n vt
)
{
Vcveff = Vdsat ,cv − 0.5 V4 + V4 2 + 4δ 4 Vdsat , cv } where V4 = Vdsat ,cv − Vds − δ 4 ; δ 4 = 0.02
2 2
A ' Abulk ' Vcveff
Qinv = − Wactive Lactive Cox Vgsteff cv − bulk Vcveff +
2 Abulk '
12 Vgsteff cv − Vcveff
2
1 − A ' ( bulk ) bulk cveff
1 − A ' A ' V 2
2
Abulk ' Vcveff 2
Wactive L active Cox V cv − Abulk ' V
Qs = Qd = 0.5Qinv = − cveff +
2 gsteff 2 Abulk
12 Vgsteffcv − Vcveff
2
( ) ( ) (
− Abulk' Vcveff )
Wactive LactiveCox 4 2 2 2 3
Qs = − 2 Vgsteffcv − Vgsteffcv
3
gstefcvf Abulk ' Vcveff + Vgsteff Abulk ' Vcveff
2
2Vgsteff cv − bulk Vcveff
A ' 3 3 15
2
(
V 3 − 5 V cv 2 A V + V cv A V
) ( ) ( )
Abulk ' Vcveff
Wactive LactiveCox 2 1 3
Qd = − 2 gsteffcv bulk ' cveff bulk ' cveff −
Abulk ' 3
gsteffcv
gsteff gsteff
5
2Vgsteffcv − Vcveff
2
Vgsteffcv A ' V ( )
2
A ' V
Qs = − Wactive Lactive Cox gstefcvf
+
bulk cveff
−
bulk cveff
2 4 Abulk '
24 Vgsteffcv − Vcveff
2
V ( )
2
3 Abulk ' Vcveff A ' V
Qd = − Wactive Lactive Cox
bulk cveff
− +
gsteffcv
2 4 Abulk '
8 Vgsteffcv − Vcveff
2
Qeq = − (Qg + Qb )
Actual channel charge and Qdef obtained from subcircuit (Figure 5-2):
1 1 1
gτ = = +
τ τ drift τ diff
CoxWeff Leff 3 ζ
τ drift = ≈
µ eff ε Qeq − αQdef Qeq
where,
ε ≡ Elmore Constant (default = 5) 0.0 ≤ α ≤ 1.0 ( default = 0.5)
and
CoxWeff Leff 3
ζ=
µ eff ε
qLeff 2
τ diff =
16 µ eff KT
KfIds af
Flic ker Noise =
CoxLeff 2 f ef
2. For noimod=2 and 3
1. Vgs>Vth+0.1:
where Vtm is the thermal voltage, µeff is the effective mobiity at the given
bias condition, Leff and Weff are the effective channel length and width,
respectively. The parameter N0 is the charge density at the source given by:
C ox ( V GS – V TH )
N 0 = ----------------------------------------
q
C ox ( V GS – V TH – V D S ′ )
N l = ---------------------------------------------------------
q
V DS ′ = MIN ( V D S, V DSAT )
∆Lclm refers to channel length reduction due to CLM and is given by:
V DS – V DSAT
------------------------------ + Em
Litl
Litl × log --------------------------------------------
-
E SAT if VDS > VDSAT
∆L cl m =
0 otherwise
2 × Vsat
E SAT = ---------------------
u e ff
2. Otherwise,
S l imi t × S wi
FlickerNoise = --------------------------
S li mit + S wi
NoiaVtIds 2
Swi =
WeffLeff f Ef 4 x 10 36
8 kT
( gm + gds + gmb )
3
2. For noimod=2 and 4
4 KTµeff
Qinv
Leff 2
Abulk
Qinv = − Weff Leff C ox Vgsteff (1 − Vdseff )
2(Vgsteff + 2vt )
The derivation for this last thermal noise expression is based on the noise
model found in [35].
[1] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p.11, vol. 18, 1989.
[2] Muller and Kamins, Devices Electronics for Integrated Circuits, Second Edition.
[4] J.A. Greenfield and R.W. Dutton, "Nonplanar VLSI Device Analysis Using the
Solution of Poisson's Equation," IEEE Trans. Electron Devices, vol. ED-27, p.1520,
1980.
[5] H.S. Lee. "An Analysis of the Threshold Voltage for Short-Channel IGFET's," Solid-
State Electronics, vol.16, p.1407, 1973.
[7] T. Toyabe and S. Asai, "Analytical Models of Threshold Voltage and Breakdown
Voltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis,"
IEEE J. Solid-State Circuits, vol. SC-14, p.375, 1979.
[8] D.R. Poole and D.L. Kwong, "Two-Dimensional Analysis Modeling of Threshold
Voltage of Short-Channel MOSFET's," IEEE Electron Device Letter, vol. ED-5, p.443,
1984.
[10] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, and Y.C. Cheng,
"Threshold Voltage Model For Deep-Submicrometer MOSFETs," IEEE Tran.
Electron Devices, vol. 40, pp. 86-95, Jan., 1993.
[11] Y.C. Cheng and E.A. Sullivan, "Effect of Coulombic Scattering on Silicon Surface
Mobility," J. Appl. Phys. 45, 187 (1974).
[12] Y.C. Cheng and E.A. Sullivan, Surf. Sci. 34, 717 (1973).
[13] A.G. Sabnis and J.T. Clemens, "Characterization of Electron Velocity in the Inverted
<100> Si Surface," Tech. Dig.- Int. Electron Devices Meet., pp. 18-21 (1979).
[14] G.S. Gildenblat, VLSI Electronics: Microstructure Science, p. 11, vol. 18, 1989.
[15] M.S. Liang, J.Y. Choi, P.K. Ko, and C. Hu, "Inversion-Layer Capacitance and
Mobility of Very Thin Gate-Oxide MOSFET's," IEEE Trans. Electron Devices, ED-
33, 409, 1986.
[16] F. Fang and X. Fowler, "Hot-electron Effects and Saturation velocity in Silicon
Inversion Layer," J. Appl. Phys., 41, 1825, 1969.
[19] K.Y. Toh, P.K. Ko and R.G. Meyer, "An Engineering Model for Short-channel MOS
Devices," IEEE Jour. of Solid-State Circuits, vol. 23, No. 4, Aug. 1988.
[20] C. Hu, S. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan and K.W. Kyle, "Hot-Electron Induced
MOSFET Degradation - Model, Monitor, Improvement," IEEE Tran. on Electron
Devices, Vol. 32, pp. 375-385, Feb. 1985.
[21] F.C. Hsu, P.K. Ko, S. Tam, C. Hu and R.S. Muller, "An Analytical Breakdown Model
for Short-Channel MOSFET's," IEEE Trans. on Electron Devices, Vol.ED-29, pp.
1735, Nov. 1982
[23] M. Shur, T.A. Fjeldly, T. Ytterdal, and K. Lee, “ A Unified MOSFET Model,” Solid-
State Electron., 35, pp. 1795-1802, 1992.
[25] C. F. Machala, P. C. Pattnaik and P. Yang, "An Efficient Algorithms for the Extraction
of Parameters with High Confidence from Nonlinear Models," IEEE Electron Device
Letters, Vol. EDL-7, no. 4, pp. 214-218, 1986.
[26] Y. Tsividis and K. Suyama, “MOSFET Modeling for Analog Circuit CAD: Problems
and Prospects,” Tech. Dig. vol. CICC-93, pp. 14.1.1-14.1.6, 1993.
[28] D. S. Jeon, et al, IEEE Tran. on Electron Devices, vol. ED-36, no. 8, pp1456-1463,
1989.
[30] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, Second
Edition.
[31] Mansun Chan, et al, "A Relaxation time Approach to Model the Non-Quasi-Static
Transient Effects in MOSFETs," IEDM, 1994 Technical Digest, pp. 169-172, Dec.
1994.
[33] K.K. Hung et al, “A Physics-Based MOSFET Noise Model for Circuit Simulators,”
IEEE Transactions on Electron Devices, vol. 37, no. 5, May 1990.
[34] K.K. Hung et al, “A Unified Model for the Flicker Noise in Metal-Oxide
Semiconductor Field-Effect Transistors,” IEEE Transactions on Electron Devices,
vol. 37, no. 3, March 1990.
[35] T.P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New
York, 1987.
Below is a list of all BSIM3v3 model parameters which can or cannot be binned. All
model parameters which can be binned follow the following implementation:
PL PW Pp
P = P 0 + --------- + ---------- + --------------------------
L W
eff L ×W
eff eff eff
For example, for the parameter k1: P0=k1, PL=lk1, PW=wk1, PP=pk1. Binunit is a bin unit
selector. If binunit=1, the units of Leff and Weff used in the binning equation above have
the units of microns. Otherwise, they are in meters.
For example, for a device with Leff=0.5µm and Weff=10µm. If binunit = 1, the parameter
values for vsat are 1e5, 1e4, 2e4, and 3e4 for vsat, lvsat, wvsat, and pvsat, respectively.
Therefore, the effective value of vsat for this device is:
To get the same effective value of vsat for binunit = 0, the values of vsat, lvsat, wvsat, and
pvsat would be 1e5, 1e-2, 2e-2, 3e-8, respectively. Thus,
As a final note: although BSIM3v3 supports binning as an option for model extraction, it
is not strongly recommended.
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
none level BSIMv3 model selector NO
Mobmod mobmod Mobility model selector NO
Capmod capmod Flag for the short channel NO
capacitance model
Nqsmod nqsmod Flag for NQS model NO
Noimod noimod Flag for Noise model NO
D.2 DC Parameters
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Vth0 vth0 Threshold voltage @Vbs=0 for YES
Large L.
K1 k1 First order body effect coeffi- YES
cient
K2 k2 Second order body effect coef- YES
ficient
K3 k3 Narrow width coefficient YES
K3b k3b Body effect coefficient of k3 YES
W0 w0 Narrow width parameter YES
Nlx nlx Lateral non-uniform doping YES
parameter
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Dvt0 dvt0 first coefficient of short-channel YES
effect on Vth
Dvt1 dvt1 Second coefficient of short- YES
channel effect on Vth
Dvt2 dvt2 Body-bias coefficient of short- YES
channel effect on Vth
Dvt0w dvt0w First coefficient of narrow YES
width effect on Vth for small
channel length
Dvt1w dvtw1 Second coefficient of narrow YES
width effect on Vth for small
channel length
Dvt2w dvt2w Body-bias coefficient of nar- YES
row width effect for small chan-
nel length
µ0 u0 Mobility at Temp = Tnom
NMOSFET YES
PMOSFET
Ua ua First-order mobility degrada- YES
tion coefficient
Ub ub Second-order mobility degrada- YES
tion coefficient
Uc uc Body-effect of mobility degra- YES
dation coefficient
νsat vsat Saturation velocity at Temp = YES
Tnom
A0 a0 Bulk charge effect coefficient YES
for channel length
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Ags ags gate bias coefficient of Abulk YES
B0 b0 Bulk charge effect coefficient YES
for channel width
B1 b1 Bulk charge effect width offset YES
Keta keta Body-bias coefficient of bulk YES
charge effect
A1 a1 First non0saturation effect YES
parameter
A2 a2 Second non-saturation factor YES
Rdsw rdsw Parasitic resistance per unit YES
width
Prwb prwb Body effect coefficient of Rdsw YES
Prwg prwg Gate bias effect coefficient of YES
Rdsw
Wr wr Width Offset from Weff for Rds YES
calculation
Wint wint Width offset fitting parameter NO
from I-V without bias
Lint lint Length offset fitting parameter NO
from I-V without bias
dWg dwg Coefficient of Weff’s gate YES
dependence
dWb dwb Coefficient of Weff’s substrate YES
body bias dependence
Voff voff Offset voltage in the subthresh- Yes
old region for large W and L
Nfactor nfactor Subthreshold swing factor YES
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Eta0 eta0 DIBL coefficient in subthresh- YES
old region
Etab etab Body-bias coefficient for the YES
subthreshold DIBL effect
Dsub dsub DIBL coefficient exponent in YES
subthreshold region
Cit cit Interface trap capacitance YES
Cdsc cdsc Drain/Source to channel cou- YES
pling capacitance
Cdscb cdscb Body-bias sensitivity of Cdsc YES
Cdscd cdscd Drain-bias sensitivity of Cdsc YES
Pclm pclm Channel length modulation YES
parameter
Pdiblc1 pdiblc1 First output resistance DIBL YES
effect correction parameter
Pdiblc2 pdiblc2 Second output resistance DIBL YES
effect correction parameter
Pdiblcb pdiblcb Body effect coefficient of YES
DIBL correction parameters
Drout drout L dependence coefficient of the YES
DIBL correction parameter in
Rout
Pscbe1 pscbe1 First substrate current body- YES
effect parameter
Pscbe2 pscbe2 Second substrate current body- YES
effect parameter
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Pvag pvag Gate dependence of Early volt- YES
age
δ delta Effective Vds parameter YES
Ngate ngate poly gate doping concentration YES
α0 alpha0 The first parameter of impact YES
ionization current
β0 beta0 The second parameter of impact YES
ionization current
Rsh rsh Source drain sheet resistance in NO
ohm per square
Jso js Source drain junction saturation NO
current per unit area
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Xpart xpart Charge partitioning rate flag NO
CGS0 cgso Non LDD region source-gate NO
overlap capacitance per
channel length
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
CGD0 cgdo Non LDD region drain-gate NO
overlap capacitance per
channel length
CGB0 cgbo Gate bulk overlap capacitance NO
per unit channel length
Cj cj Bottom junction per unit area NO
Mj mj Bottom junction capacitance NO
grating coefficient
Mjsw mjsw Source/Drain side junction NO
capacitance grading coeffi-
cient
Cjsw cjsw Source/Drain side junction NO
capacitance per unit area
Pb pb Bottom built-in potential NO
Pbsw pbsw Source/Drain side junction NO
built-in potential
CGS1 cgs1 Light doped source-gate YES
region overlap capacitance
CGD1 cgd1 Light doped drain-gate region YES
overlap capacitance
CKAPPA ckappa Coefficient for lightly doped YES
region overlap
capacitance Fringing field
capacitance
Cf cf fringing field capacitance YES
CLC clc Constant term for the short YES
channel model
CLE cle Exponential term for the short YES
channel model
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
DLC dlc Length offset fitting parameter YES
from C-V
DWC dwc Width offset fitting parameter YES
from C-V
Vfb vfb Flat-band voltage parameter YES
(for capmod=0 only)
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Elm elm Elmore constant of the channel YES
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Wl wl Coefficient of length depen- NO
dence for width offset
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Tnom tnom Temperature at which parame- NO
ters are extracted
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Noia noia Noise parameter A NO
Noib noib Noise parameter B NO
Noic noic Noise parameter C NO
Em em Saturation field NO
Af af Frequency exponent NO
Ef ef Frequency exponent NO
Kf kf Flicker noise parameter NO
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Tox tox Gate oxide thickness NO
Xj xj Junction Depth YES
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Symbols Symbols
used in used in Description Can Be
equation SPICE Binned?
Lmin lmin Minimum channel length NO