QUESTIONS – SDH/PDH

1. Provide a comparison (of at least 5 features) between the two primary protocols
(PDH and SDH) in use today in transport networks.

The limitations of PDS multiplexing are:

- A hierarchy of multiplexers at either end of the link can lead to reduced reliability and
resilience.

- PDH links are generally limited to point-to-point configurations with full demultiplexing
at each switching or cross connection node.

- Incompatibilities at the optical interfaces of two different suppliers can cause system
integration problems.

- To add or drop an individual channel or add a lower rate branch to a backbone link a
complete hierarchy of MUXs is required

SDH transmission systems benefits over PDH:

- Software Control allows extensive use of intelligent network management software

for high flexibility, fast and easy re-configurability, and efficient network management.

- Survivability. With SDH, ring networks become practicable and their use enables
automatic reconfiguration and traffic rerouting when a link is damaged. End-to-end
monitoring will allow full management and maintenance of the whole network.

- Efficient drop and insert. SDH allows simple and efficient cross-connect without full
hierarchical multiplexing or de-multiplexing. A single E1 2.048Mbit/s tail can be dropped
or inserted with relative ease even on Gbit/s links.

- Standardisation enables the interconnection of equipment from different suppliers

through support of common digital and optical standards and interfaces.

- Robustness and resilience of installed networks is increased.

- Equipment size and operating costs are reduced by removing the need for banks
of multiplexers and de-multiplexers. Follow-on maintenance costs are also reduced.

- Backwards compatibly will enable SDH links to support PDH traffic.

- Future proof. SDH forms the basis, in partnership with ATM (asynchronous transfer
mode), of broad-band transmission, otherwise known as B-ISDN or the precursor of
this service in the form of Switched Multimegabit Data Service, (SMDS).
2. In digital multiplexers synchronization of tributary signals into the multiplex signal is
performed by means of justification. Describe the operation of the justification mechanism in
asynchronous multiplexing (PDH);

- Asynchronous multiplexing the clock signals of the tributary sources are

asynchronous, ie have same rate but independent bit rates within a given tolerance.

- The binary digits of each tributary are written into a buffer store, with the write
frequency equal to the tributary instantaneous bit rate.

- The buffer read frequency is the same for every tributary.

- Since the elastic stores are read faster than they are written to, they progressively
empty.

- Reading is inhibited when the buffer approaches depletion,

● at certain positions within the output multiplex signal justification bits rate
are inserted.
● one justification bit position is reserved per tributary in each multiplex
frame.

- The justification control scheme (negative bit justification);

● all C bits equal to ‘1’ mean that the justification digit (S bit) of the
corresponding tributary is a don’t care term.
● all C bits equal to ‘0’ mean that the justification digit (S bit) of the
corresponding tributary is an information bit.

- Majority voting is used to provide protection against errors in the C bits.

3. Describe the operation of the justification mechanism in synchronous multiplexing

(SDH);

- The AU-4 pointer designates the location of the byte (pointer value is in the range 0 to
782) where VC-4 begins.

- If there is a frequency offset between the frame rate of the AUG and that of the
incoming VC-4, then;

● The pointer is incremented (positive justification) or decremented (negative

justification) as necessary.

● Accompanied by a positive or negative byte justification.

- Consecutive pointer adjustments are separated by at least 3 frames in which the

pointer value remains constant.
4. Sketch the four consecutive STM-1 frames where negative justification is taking place
with the AU-4 pointer value updated from an initial value of n = 87. State the decimal value of
the 10 bits of the pointer word in all frames and highlight the position of the VC-4 with its Path
Overhead (POH).

Frame New Data flag 512 256 128 64 32 16 8 4 2 1

Status I D I D I D I D I D
Normal 0 1 1 0 X X 0 0 0 1 0 1 0 1 1 1
Frame
Invert D 0 1 1 0 X X 0 1 0 0 0 0 0 0 1 0
bits
New ptr 0 1 1 0 X X 0 0 0 1 0 1 0 1 1 0
value
New ptr 0 1 1 0 X X 0 0 0 1 0 1 0 1 1 0
value
New ptr 0 1 1 0 X X 0 0 0 1 0 1 0 1 1 0
value

= 87 x 3 = 261

= 258

= 86 x 3 = 258

=86 x 3 = 258

=86 x 3 = 258

The ‘D’ have been inverted therefore negative justification (If the ‘I’ had been inverted it would
have meant positive justification).

The true pointer value is 261.

 9 Bytes 261 Bytes

RSOH

n = 87 9 Bytes AU POINTER

MSOH

VC-4

RSOH

n = 87 9 Bytes AU POINTER

MSOH

VC-4

RSOH
3 bytes
3 bytes
n = 258 9 Bytes 261 bytes

MSOH

VC-4
RSOH

n = 86 9 Bytes AU POINTER

MSOH

5. In digital multiplexers synchronization of tributary signals into the multiplex signal is

performed by means of justification. Describe the operation of the justification mechanism in
asynchronous multiplexing (PDH);

- Asynchronous multiplexing the clock signals of the tributary sources are

asynchronous, ie have same rate but independent bit rates within a given tolerance.

- The binary digits of each tributary are written into a buffer store, with the write
frequency equal to the tributary instantaneous bit rate.

- The buffer read frequency is the same for every tributary.

- Since the elastic stores are read faster than they are written to, they progressively
empty.

- Reading is inhibited when the buffer approaches depletion,

- at certain positions within the output multiplex signal justification bits rate
are inserted.
- one justification bit position is reserved per tributary in each multiplex frame.
 - The justification control scheme (negative bit justification);
- all C bits equal to ‘1’ mean that the justification digit (S bit) of the corresponding
tributary is a don’t care term.
- all C bits equal to ‘0’ mean that the justification digit (S bit) of the corresponding
tributary is an information bit.

- Majority voting is used to provide protection against errors in the C bits.

6. Describe the operation of the justification mechanism in synchronous multiplexing

(PDH);

- The AU-4 pointer designates the location of the byte (pointer value is in the range 0 to
782) where VC-4 begins.

- If there is a frequency offset between the frame rate of the AUG and that of the
incoming VC-4, then the pointer is incremented (positive justification) or decremented
(negative justification) as necessary, accompanied by a positive or negative byte
justification.

- Consecutive pointer adjustments are separated by at least 3 frames in which the

pointer value remains constant.

7. Sketch the four consecutive STM-1 frames where negative justification is taking place
with the AU-4 pointer value updated from an initial value of n = 87. State the decimal value of
the 10 bits of the pointer word in all frames and highlight the position of the VC-4 with its Path
Overhead (POH).
 -ve justification

+ve justification

PDH/SDH

8. The reason for and the operation of the justification mechanism in:

a. PDH – In asynchronous digital multiplexing the clock signals of the tributary

sources are asynchronous, i.e. they have the same nominal rate but independent bit
rates within a given tolerance range.

PMUX

Data written

HMUX

Elastic memories at i/p

Tributaries
Different rates (+/- 50 ppm)
When the rate of the incoming flow of any of the tributaries is below the reading rate,
the PMUX can’t read any bits from the elastic memory, so it adds bits, so to make up
the aggregate signal (positive justification).

The reason that bits are only added and not taken away is that the tributaries are never
always running at the maximum clock rate, therefore one or more tributaries will require
‘bit stuffing’.

The binary digits of each tributary are written into a buffer store, with the ‘write’
frequency equal to the tributary bit rate. The buffer ‘read’ frequency is the same for
each tributary. Since the elastic stores are ‘read’ faster than they are ‘written’ to, they
tend to progressively empty.

Reading is inhibited when the buffer approaches depletion, and justification bits are
inserted at certain bit positions within the output multiplex signal. Usually, one
justification bit position is reserved per tributary in each PDH multiplex frame.

b. SDH – After the path overhead is added to form a Virtual Container (VC), the
VC is positioned in a Tributary Unit (TU) or and Administrative Unit (AU) with a pointer
indicating the start of the VC relative to the TU or AU.
The AU-n pointer indicates the position of the first byte of the corresponding VC-n
(n=3,4) which is free to float in the STM N frame.

In this case, the AU-4 pointer designates the location of the byte (bits 7 to 16 for AU-4
is 0 to 782 (the increment and decrement bits)) where the VC-4 begins. If there is a
frequency offset between the frame rate of the Administration Unit Group (AUG) and
that of the incoming VC-4, then the pointer value is incremented (positive justification)
or decremented (negative justification) as necessary. This is also accompanied by a
corresponding positive or negative byte justification.

No subsequent increment or decrement operation is allowed for at least three frames

following the operation.
 c. The AU-4 pointer value n=90 indicates that the VC-4 is aligned with an offset
90 x 3 = 270 bytes from the end of the SOH fourth row.

The AU-4 pointer with negative justification is illustrated in the table below.

Frame status New Data Flag (NDF) I D I D I D I D I D

Normal frame 0 1 1 0 x x 0 0 0 1 0 1 1 0 1 0
Invert D bits 0 1 1 0 x x 0 1 0 0 0 0 1 1 1 1
New ptr value 0 1 1 0 x x 0 0 0 1 0 1 1 0 0 1
New ptr value 0 1 1 0 x x 0 0 0 1 0 1 1 0 0 1
New ptr value 0 1 1 0 x x 0 0 0 1 0 1 1 0 0 1

Positive justification occurs when the bit rate of the VC is lower than that of the AU.
Negative justification occurs when the bit rate of the VC is higher than that of the AU.

-ve justification

+ve justification
9. Provide a comparison (of at least 5 features) between the two primary protocols
(PDH and SDH) in use today in transport networks.

10. In digital multiplexers synchronization of tributary signals into the multiplex signal is
performed by means of justification. Describe the operation of the justification mechanism in
asynchronous multiplexing (PDH);

11. Describe the operation of the justification mechanism in synchronous multiplexing

(SDH);

12. Sketch the four consecutive STM-1 frames where negative justification is taking place
with the AU-4 pointer value updated from an initial value of n = 87. State the decimal value of
the 10 bits of the pointer word in all frames and highlight the position of the VC-4 with its Path
Overhead (POH).

ASYNCHRONOUS TRANSFER MODE (ATM)

13. ATM is the international standard for cell relay and it provides a single network
technology to transport triple play services; video, voice and data services. Provide a
description of each field of a UNI cell header. Identift, the changes that are made to a UNI
header format in order to convert to a NNI cell header.

UNI Cell header

- GFC (Generic Flow Control) assists in control of the flow of traffic from ATM
connections of various QoS classes. The GFC field does not appear in the cell header
internal to the network but only at the User Network interface (UNI).
- VPI (Virtual path identifier) links, the different virtual path links multiplexed at the ATM
layer into the same physical layer connection are distinguished by the VPI.

- VCI (Virtual channel identifier) links, the different virtual channel links in a virtual path
connection (VPC) are distinguished by the VCI.
-