INTERRUPTS

• The difference between Hardware and Software Interrupts

(eg. BIOS/DOS calls) is that an external device, not
programmer, causes the hardware interrupt to occur. For
eg. There is a keyboard interrupt which causes the PC to
read a character typed.
• Types of Interrupts and Priorities
– Reset (Highest Priority)
– Internal Interrupts and Exceptions
– Software Interrupts: SWI (INT #)
– NonMaskable Interrupts (NMI): External Hardware
– External (maskable) Hardware (Lowest Priority)
 Interrupt Vectors
• All interrupts involve obtaining a vector (8
bit #) which is used by the MPU to fetch
the address of the Interrupt Service Routine
(ISR).
• The address of the ISRs are in a table in
memory beginning at 00h
• Each entry (4B) in the table contains IP &
CS of the corresponding ISR start address.
 Interrupt Vector Table
Mem addr Vector Sys Services
.
.
CS70h
70h*4 IP70h Vec 70h - CMOS Real Time Clock
.
.
CS9 Vec 9 - PC Keyboard OR
9*4 IP9 coprocessor seg overflow
CS8 Vec 8 - PC Sys Timer OR
8*4 IP8 interrupt table limit too small
.
.
CS2
08 IP2 Vec 2 - NMI
CS1
Vec 1 - debug
04 IP1
02 CS0 Vec 0 - divide error
00 IP0

Note: There is maximum of 256 vectors in Real Mode.

Hardware Requirements for Interrupts

RAM ROM

INTR
INT
Interrupt
io1 io7
MPU Controller
INTA# IR0
IR7 ...
reset NMI
 8259 Programmable Interrupt
Controller (PIC)
• The 8259 PIC functions as overall mgr of an interrupt
system environment.
• Each PIC has up to 8 interrupt request (IR) inputs
• Expandable up to 64 interrupt levels via cascading in a
Primary Secondary environment.
• Some Internal Registers are
– Interrupt Req. Reg (IRR): 8b reg storing 8 independent IRQs
– In-Service Reg (SR): 8b reg storing interrupt levels which are
being serviced
– Interrupt Mask Reg (IMR): 8b reg storing interrupt levels to be
masked. It operates on IRRs.
 PIC Details

Interrupt Request to MPU INT IR0 Interrupt

Interrupt ACK from MPU INTA#
IR1 Requests
Data Bus: interrupt vec, control, D7-D0 .
and status info sent on this bus .
Read RD# .
Write WR# IR7
Address: for selecting A0 8259
internal regs
Chip Select CS# PIC
CAS0
Cascade: Output from Pri
(goes to all Secs at same CAS1
time); Input to Sec. CAS2
SP#/EN#
Slave Prog/Enable Buffer
 Programming the PIC
• Initialization Command Words (ICWs)
– a series of initialization words in the order: ICW1,
ICW2, [ICW3], [ICW4]
• ICWs are identified as follows
cs# A0 ICW
0 0 ICW1
0 1 ICW2, ICW3, ICW4
1 x PIC disabled
• For eg. Master PIC in PC is at Port 20h. Thus addr of
ICW1=20h; ICW2, …ICW3=21h
 ICW1
• Indicates whether there’s more than one PIC and
whether ICW4 is needed
b7 b6 b5 b4 b3 b2 b1 bo

0 0 0 1 ltim 0 sngl icw4

• icw4=1==> ICW4 needed

• sngl (single) = 1=> single 8259; =0 => multiple (cascade)
• ltim (level timing) =1 => level input (IRi) to 8259; =0 =>
edge-triggered input.
• B4=1 indicates ICW1
 ICW2 (Interrupt Vector)
b7 b6 b5 b4 b3 b2 b1 bo

T7 T6 T5 T4 T3 T2 T1 T0

• T2 T1 T0 = 000 = Interrupt Vector for IR0.

• Interrupt Vectors for IR1, …, IR7 are derived automatically. For eg.
That of IR7=111
• Higher order bits (b7…b3)are fixed by programmer.
• In P/S mode, there is a separate ICW2 for Pri and Secondary using the
same format.
• In current PCs IRQ0 (on Pri) is assigned vector= 08h, …irq7 vec=0fh
• Sec PIC's IRQs are irq8=ir0=70h, …, irq15=1R7=77h
 ICW3 (Used in P/S Mode only)

• Separate ICW3 format for Pri and Sec. Master icw3 format follows

b7 b6 b5 b4 b3 b2 b1 bo

S7 S6 S5 S4 S3 S2 S1 S0

• Si =1 => IRQi input has a secondary (slave) connected to it

• Secondary ICW3 format

b7 b6 b5 b4 b3 b2 b1 bo

0 0 0 0 0 d2 d1 d0

D2D1D0= ID# of Pri’s IR input Sec is connected to. =000 => slave ID
=0, …, =111 => slave ID = 7.
 PIC Configuration in typical PC
Port 20h
Vector in icw2
=08h Vec 08h SP#/EN#
= Vcc=1
IRQ0 IR0 INT INTR
IRQ1 IR1
IR2 Pri PIC MPU
IRQ3 . IR3
IRQ7 . INTA#
IR7
Port A0h
CAS0-2
Vec 70h
IRQ8 IR0
INT
IRQ9 IR1
. CAS0-2
Sec PIC LOGIC
. INTA#
IRQ15 IR7

SP#/EN# = 0
 Examples
• In current PCs, • There is a single
– edge triggered inputs secondary connected
– 2 cascaded PICs to the Primary’s IR2
– ICW4 needed • Primary’s ICW3 =
• ICW1=00010001=11h 00000100=04h
mov al, 11h • Secondary’s ICW3=
out 20h, al 00000010=02h
 ICW4

b7 b6 b5 b4 b3 b2 b1 bo

T7 T6 T5 SFNM BUF MS AEOI PM

1=Special Fully
Nested Mode 0 X = nonbuffered
Note: There is
1 0 = buff mode sec a separate
ICW4 for Pri
1 1 = buff mode pri
and Sec using
the same
1=Auto EOI format
0=Manual EOI

Processor Mode: Must

be = 1 for 386 and later What is AutoEOI?
 ICW4 (Buffered Mode and SFNM)
• BUF=1, Buffered Mode
– Is used in large cascaded sys where data bus must be buffered and
with a bi-directional bus
– In this case BUF=1 means for PIC to send enable (EN#) signal on
SP#/EN#. Thus EN#=L=0 whenever data is output from PIC to
MPU
– Because SP#/EN# is used as Pri/Sec selector in Non-buffered
mode we have to find another way of specifying Pri/Sec in a
buffered mode.
• This is done in software by programming Bit2
• Bit2= MS = 0 for buffered mode Slave
= 1 for Buffered Mode Master
• SFNM=1 is a SPECIAL FULLY NESTED MODE also used in
cascaded systems. SFNM is enabled only for the Master and not
Slaves. Details on this later.
Operation Command Words (OCWs)

• These words are sent to 8259 after ICWs

have been sent.
• OCWs do not have to be sent in sequence.
• OCW Port Numbers
CS# A0 OCW Pri Sec
0 0 OCW2, OCW3 20h a0h
0 1 OCW1 21h a1h
OCW1 (Setting Interrupt Mask)

• The bits go to the Interrupt Mask Register

• The bits can also be Read to determine
mask register contents. Thus it is a R/W reg.
b7 b6 b5 b4 b3 b2 b1 bo

M7 M6 M5 M4 M3 M2 M1 M0

Mi = 1 => Interrupt i is Masked. Ie. Not recognized by PIC

 OCW2 (Assigns Specific Priority to IRQs
and Used for Specifying EOIs)

Format Follows :

b7 b6 b5 b4 b3 b2 b1 bo

R SL EOI 0 0 L2 L1 L0

Rotation
000 = Level 0
Specific Level
001 = Level 1
End-Of-Interrupt ...
111 = Level 7
 OCW2 DETAILS
R SL EOI Description
0 0 1 Non specific EOI cmd
0 1 1 *Specific EOI cmd
1 0 1 Rotate on Nonspec EOI cmd
1 0 0 Rotate in Auto EOI mode(set)
0 0 0 Rotate in Auto EOI mode(clr)
1 1 1 *Rotate on Specific EOI cmd
1 1 0 *Set Priority cmd
0 1 0 No Operation
*: L2L1L0 are used
 OCW3

• For reading Interrupt Request Reg (IRR)

• For reading In-Service Register (ISReg)

• For Issuing Poll Command

• For Enable/Disable Special Mask Mode

 OCW3 FORMAT

b7 b6 b5 b4 b3 b2 b1 bo

X ESMM SMM 0 1 P RR RIS

RST Special Mask = 10 0 x: No Action

Set Special Mask = 11 1 0: Read IRR on nxt RD pulse
Poll/No Poll 1 1: Read ISReg on nxt RD pulse
 POLL WORD FORMAT

b7 b6 b5 b4 b3 b2 b1 bo

I 0 1 W2 W1 W0

Interrupt Code of Highest

Occurred Priority Interrupt Req.

Note: Poll Word is issued by PIC in response to Poll from MPU via
OCW3