IN-PHASE SQUARE-TO-SINE WAVE CONVERTER

Author(s): Motorola TDB

Gary E. Mueller
James W. Dejmek
IP.com number: IPCOM000005825D
Original Publication Date: March 1, 1990
IP.com Electronic Publication: November 9, 2001

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m MOTOROLA Technical Developments Volume 10 March 1990

IN-PHASE SQUARE-TO-SINE WAVE CONVERTER

by Gary E. Mueller and James W. Dejmek

The conversion of a given square wave into a sinusoid of same fundamental frequency is usually, and easily, ac-
complished using basic filtering techniques. However, when it is required that the resultant sinusoid have very low distor-
tion and be in phase with the input square wave, basic filtering approaches prove not to be a viable solution. A finite
delay in response time due to an impulse or step function, is associated with conventional filtering techniques. This
response time delay results in a phase-shifted output waveform. The response time delay is also a function of the filter’s
rolloff. The higher the rolloff, the greater the delay from input to output will be. For a low distortion output, a sharp rolloff
is required and hence, a greater delay is added to the resultant output waveform. The scenario for an example of such
stringent requirements is demonstrated in its use for a multitransmitter simulcast transmission.

For multitransmitter simulcast of binary information, it has been shown 1 that by superimposing a sine wave of
specific amplitude, phase, and frequency on the data stream to be transmitted, a maximum-ratio combining diversity
effect can be realized in the overlapped region. This superimposing sine wave is to be derived from a clock input (square
wave) whose phase has been properly adjusted to achieve the aforementioned effect. The binary information will have
a specific phase relationship (i.e. difference) to the input, The integrity of this relationship is to be preserved while deriv-
ing the superimposing sine wave from the clock signal. The in-phase square-to-sine wave converter cirmcumvents the
delay problems associated with filtering while still providing a very low distortion output waveform.

The in-phase squareto-sine wave converter is illustrated in Figure 1. Its output is a sinusoidally-enveloped staircase
waveform that is in phase (zero degrees of shift) with the input clock signal. The summing amplifier does cause an
inversion. If this were not required nor desired, an inverter could be added to the data input of the first shift register.

Generically, an input square wave of frequency f is clocked through an N-bit shift register at a rate of 2N x f. The
outputs have weighted resistors on them and are then tied together and fed to a summing amplifier (to adjust for gain
purposes). The resistors are weighted such that the resulting waveform is a staircase closely approximating a sinusoid.
A smoothing filter will smooth this waveform while also superimposing it on the data. By superimposing the sine wave
on the data at this point, any delay introduced by the summing filter (with respect to the input clock) is subsequently
added to the data. The N-bit shift register would inherently cause a 90” phase shift. However, by inverting the last N/2
outputs, this phase shift is removed.

Specifically, our input square wave is a 1200Hz signal. The sampling frequency is at 364kHz (32 x 1200Hz) and
is generated by a phase-locked loop (PLL) so as to lock the leading edges of the sampling clock and input signal together.
The fixed delay accounts for the divider’s propagation time. Two shift registers are cascaded together to provide 16 bits
of resolution. Inverting the data input to the second shift register is equivalent to inverting the last N/2 outputs to remove
the inherent 90” phase shift. Figure 2 is a timing diagram which illustrates the resultant staircase waveform (without
the inversion of the summing amplifier).

lb achieve the unique and distinct quality of having zero degrees of phase shift between input and output waveforms,
various precautions had to be taken. The sampling clock had to be high enough to provide for a high degree of resolu-
tion. From a practical standpoint, recall that the higher the sampling frequency, more shift register outputs and properly
weighted resistors are required. Also, the point at which the input square wave is sampled (with respect to its rising
edge) can vary as much as the period of the sampling clock. This variation would then propagate through the rest of
the circuit causing a significant phase delay. To circumvent these problems, a phase-locked loop (PLL) was used to
generate the 36.4kHz sampling clock. This sampling frequency provides for 16 bits of resolution. Also, the phase com-
parator of the PLL is designed to operate on 0” of phase error between its inputs. Taking into account the propagation
delay of the divider, the rising edge of the 36.4kHz signal (sample point) would lead that of the 1200 Hz input signal
by this delay. This is not desirable as it results in the next sample point (the first sample during the high cycle of the
1200 Hz waveform) occurring almost a full period of the sample clock later. Hence, a fixed delay was added to set the
occurrence of the first sample point during the high cycle of the 1200Hz input signal. This was set to occur just after
the low-to-high transition. Note that the transition points of the input waveform represent the zero crossings of the sine
wave. It is thereby necessary ot ensure that our sample point occurs as close as possible just after this transition. Special
care also had to be taken with regards to the 90” phase shift normally induced by the shift registers. By inverting the
data input to the second shift register, this effectively simulates the inversion of the outputs which removes the potential
phase shift problem.

0 Motorola, Inc. 1990 4

 MOTOROLA Technical Developments Volume 10 March 1990
@

References

1. Takashi Hattori, Shigeaki Ogose, “A New Modulation Scheme for Multitransmitter Simulcast Digital Mobile Radio
Communication;’ EEE Pansactions on Vehicular Technology, volume m-29, ,No. 2, pp. 260-270, May 1960.

Figure 1: Square-To-Sine Wave Converter

0 Motorola, Inc. 1990

 M MOTOROLA Technical Developments Volume 10 March 1990
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0 Motorola, Inc. 1990 6