J. C. Huang
Department of Computer Science
University of Houston
memory elements
DB=xA'
B' D
B
A' D
A
B' J
B K
A' J
A K
JA = B
KA = Bx'
JB = x'
KB = A'x + Ax'
x
comb. KA
network JA
KB
JB JA = B
KA = Bx'
JB = x'
KB = A'x + Ax'
B' J
B K
A' J
A K
next state
present state x=0 x=1
A(t)B(t) A(t+1)B(t+1) A(t+1)B(t+1)
00 ? ?
01 ? ?
10 ? ?
11 ? ?
B' J
B K
A' J
A K
JA = B
KA = Bx'
JB = x'
KB = A'x + Ax'
x A B JA KA JB KB
0 0 0 0 0 1 0
0 0 1 1 1 1 0
0 1 0 0 0 1 1
0 1 1 1 1 1 1
1 0 0 0 0 0 1
1 0 1 1 0 0 1
1 1 0 0 0 0 0
1 1 1 1 0 0 0
x A B JA KA JB KB A(t+1) B(t+1)
0 0 0 0 0 1 0
0 0 1 1 1 1 0
0 1 0 0 0 1 1
0 1 1 1 1 1 1
1 0 0 0 0 0 1
1 0 1 1 0 0 1
1 1 0 0 0 0 0
1 1 1 1 0 0 0
x A B JA KA JB KB A(t+1) B(t+1)
0 0 0 0 0 1 0 0
0 0 1 1 1 1 0 1
0 1 0 0 0 1 1 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 1 0
1 0 1 1 0 0 1 1
1 1 0 0 0 0 0 1
1 1 1 1 0 0 0 1
JK Q(t+1)
00 Q(t) no change
01 0 reset
10 1 set
11 Q'(t) complement
x A B JA KA JB KB A(t+1) B(t+1)
0 0 0 0 0 1 0 0 1
0 0 1 1 1 1 0 1 1
0 1 0 0 0 1 1 1 1
0 1 1 1 1 1 1 0 0
1 0 0 0 0 0 1 0 0
1 0 1 1 0 0 1 1 0
1 1 0 0 0 0 0 1 0
1 1 1 1 0 0 0 1 1
JK Q(t+1)
00 Q(t) no change
01 0 reset
10 1 set
11 Q'(t) complement
x A B JA KA JB KB A(t+1) B(t+1)
0 0 0 0 0 1 0 0 1
0 0 1 1 1 1 0 1 1
0 1 0 0 0 1 1 1 1
0 1 1 1 1 1 1 0 0
1 0 0 0 0 0 1 0 0
1 0 1 1 0 0 1 1 0
1 1 0 0 0 0 0 1 0
1 1 1 1 0 0 0 1 1
Reconstruct the state table to yield
next state
present state x=0 x=1
A(t)B(t) A(t+1)B(t+1) A(t+1)B(t+1)
00 01 00
01 11 10
10 11 10
11 00 11
Mealy Model: the outputs are functions of both the present states and inputs.
Moore Model: the outputs are a function of the present state only.
Example:
Two states are said to be equivalent if, for each possible single input, they give
exactly the same output and send the circuit either to the same state or to an
equivalent state.
When two states are equivalent in this sense, one of them can be removed without
altering the input-output relations.
Suppose we are given a word description of the desired circuit behavior, and it is
translated into the following state table (Step 2):
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f g d 0 1
g g h 0 1
h g a 1 0
b d a 0 0
d f a 1 0
f f d 0 1
b d a 0 0
d f a 1 0
f f d 0 1
b d a 0 0
d f a 1 0
f f d 0 1
00 → a 01 → b 10 → d 11 → f
00 11 01 0 0
01 10 00 0 0
10 11 00 1 0
11 11 10 0 1
This state table can be implemented by a sequential circuit of the form depicted
below using D type flip-flops (Steps 5 and 6):
x y=?
comb.
network DA=?
DB=?
B' D
B
A' D
A
00 11 01 0 0
01 10 00 0 0
10 11 00 1 0
11 11 10 0 1
0 0 0 1 1 0
0 0 1 1 0 0
0 1 0 1 1 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 1 0 1
0 0 0 1 1 1 0
0 0 1 1 0 1 0
0 1 0 1 1 1 1
0 1 1 1 1 1 0
1 0 0 0 1 0 0
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 1 0 1 1
0 0 0 1 1 1 1 0
0 0 1 1 0 1 0 0
0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 0
1 0 1 0 0 0 0 0
1 1 0 0 0 0 0 0
1 1 1 1 0 1 0 1
x' 1 1 1 1
x 0 0 1 0 DA = x' + AB
x' 1 0 1 1
x 1 0 0 0 DB = x'A + A'B'
x' 0 0 0 1
x 0 0 1 0 y = x'AB' + xAB
This state table can be implemented by a sequential circuit of the form depicted
below using JK flip-flops (Steps 5 and 6):
x y=?
comb. KA=?
network JA=?
KB=?
JB=?
B' J
B K
A' J
A K
0 0 0 1 1 0
0 0 1 1 0 0
0 1 0 1 1 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 1 0 1
0 0 0 1 1 0
0 0 1 1 0 0
0 1 0 1 1 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 1 0 1
0 0 0 1 1 1 X 0
0 0 1 1 0 1 X 0
0 1 0 1 1 X 0 1
0 1 1 1 1 X 0 0
1 0 0 0 1 0 X 0
1 0 1 0 0 0 X 0
1 1 0 0 0 X 1 0
1 1 1 1 0 X 0 1
0 0 0 1 1 1 X 1 X 0
0 0 1 1 0 1 X X 1 0
0 1 0 1 1 X 0 1 X 1
0 1 1 1 1 X 0 X 0 0
1 0 0 0 1 0 X 1 X 0
1 0 1 0 0 0 X X 1 0
1 1 0 0 0 X 1 0 X 0
1 1 1 1 0 X 0 X 1 1
x' 1 1 X X
x 0 0 X X JA = x'
x' X X 0 0
x X X 0 1 KA = xB'
x' 1 X X 1
x 1 X X 0 JB = x' + A'
x' X 1 0 X
x X 1 1 X KB = x + A'
x' 0 0 0 1
x 0 0 1 0 y = x'AB' + xAB
present next
state state
(at time t) (at t+1)
A4 A3 A2 A1 A4 A3 A2 A1
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 1010
1010 1011
1011 1100
1100 1101
1101 1110
1110 1111
1111 0000
KA4
combinational
network
JA1
A1 J
A'1 K
A2 J
A'2 K
A3 J
A'3 K
A4 J
A'4 K
CP
present next
state state
(at time t) (at t+1) JA1 KA1 JA2 KA2 JA3 KA3 JA4 KA4
A4 A3 A2 A1 A4 A3 A2 A1
0000 0001 1 X 0 X 0 X 0 X
0001 0010 X 1 1 X 0 X 0 X
0010 0011 1 X X 0 0 X 0 X
0011 0100 X 1 X 1 1 X 0 X
0100 0101 1 X 0 X X 0 0 X
0101 0110 X 1 1 X X 0 0 X
0110 0111 1 X X 0 X 0 0 X
0111 1000 X 1 X 1 X 1 1 X
1000 1001 1 X 0 X 0 X X 0
1001 1010 X 1 1 X 0 X X 0
1010 1011 1 X X 0 0 X X 0
1011 1100 X 1 X 1 1 X X 0
1100 1101 1 X 0 X X 0 X 0
1101 1110 X 1 1 X X 0 X 0
1110 1111 1 X X 0 X 0 X 0
1111 0000 X 1 X 1 X 1 X 1
JA1 = 1
KA1= 1
JA2 = A1
KA2= A1
JA3 = A2A1
KA3= A2A1
JA4 = A3A2A1
KA4= A3A2A1
Note that if we let JA1 = KA1 = 0 then none of the flip-flop will change its state,
and therefore we can use it to stop (i.e., to disable) the counter.
present next
state state
(at time t) (at t+1)
A4 A3 A2 A1 A4 A3 A2 A1
0000 1111
0001 0000
0010 0001
0011 0010
0100 0011
0101 0100
0110 0101
0111 0110
1000 0111
1001 1000
1010 1001
1011 1010
1100 1011
1101 1100
1110 1101
1111 1110
present next
state state
(at time t) (at t+1) JA1 KA1 JA2 KA2 JA3 KA3 JA4 KA4
A4 A3 A2 A1 A4 A3 A2 A1
0000 1111 1 X 1 X 1 X 1 X
0001 0000 X 1 0 X 0 X 0 X
0010 0001 1 X X 1 0 X 0 X
0011 0010 X 1 X 0 0 X 0 X
0100 0011 1 X 1 X X 1 0 X
0101 0100 X 1 0 X X 0 0 X
0110 0101 1 X X 1 X 0 0 X
0111 0110 X 1 X 0 X 0 0 X
1000 0111 1 X 1 X 1 X X 1
1001 1000 X 1 0 X 0 X X 0
1010 1001 1 X X 1 0 X X 0
1011 1010 X 1 X 0 0 X X 0
1100 1011 1 X 1 X X 1 X 0
1101 1100 X 1 0 X X 0 X 0
1110 1101 1 X X 1 X 0 X 0
1111 1110 X 1 X 0 X 0 X 0
JA1 = 1
KA1= 1
JA2 = A'1
KA2= A'1
JA3 = A'2A'1
KA3= A'2A'1
JA4 = A'3A'2A'1
KA4= A'3A'2A'1
This is reflected in the logic diagram shown in Fig. 7-18. Note that this design can
be directly translated into a T flip-flop implementation because the J input to every
flip-flop is identical to its K input.