03LSMOS Model

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-1
LECTURE 090 – LARGE SIGNAL MOSFET MODEL

LECTURE ORGANIZATION
Outline
• Introduction to modeling
• Operation of the MOS transistor
• Simple large signal model (SAH model)
• Subthreshold model
• Short channel, strong inversion model
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 73-78 and 97-99
CMOS Analog Circuit Design © P.E. Allen - 2010
INTRODUCTION TO MODELING
Models Suitable for Understanding Analog Design
The model required for analog design with CMOS technology is one that leads to
understanding and insight as distinguished from accuracy.
Technology
Understanding
and Usage
Updating Model Thinking Model Updating Technology

Simple,
±10% to ±50% accuracy
Comparison of Design Decisions- Extraction of Simple

simulation with "What can I change to Model Parameters
expectations accomplish ....?" from Computer Models
Expectations
"Ballpark"
Computer Simulation
Refined and
optimized
design Fig.3.0-02
This lecture is devoted to the simple model suitable for design not using simulation.

Categorization of Electrical Models
Time Dependence
Time Independent Time Dependent
Linear Small-signal, midband Small-signal frequency

Rin, Av, Rout response-poles and zeros
Linearity (.TF) (.AC)
Nonlinear DC operating point Large-signal transient

iD = f(vD,vG,vS,vB) response - Slew rate
(.OP) (.TRAN)
Based on the simulation capabilities of SPICE.
OPERATION OF THE MOS TRANSISTOR

Formation of the Channel for an Enhancement MOS Transistor
;;;
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0
;; ;;;
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region
Threshold (VG=VT)
;;;;;;
;;;
VB = 0 VS = 0 VG =VT VD = 0
Polysilicon
p+
;; ;;;n+ n+
;;;
p- substrate Inverted Region
Strong Threshold (VG>VT)
;;;
VB = 0 VS = 0 VG >VT VD = 0
;;;;;;
;;;
Polysilicon
p+ n+ n+
Fig.3.1-02
Transconductance Characteristics of an Enhancement NMOSFET when VDS = 0.1V
;;;
VGS≤VT:
VB = 0 VS = 0 vG =VT VD = 0.1V iD
;; ;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region 0 vGS
0 VT 2VT 3VT
VGS=2VT:
;;;;
;; ;;;
VB = 0 VS = 0 VG = 2VT VD = 0.1V iD
iD
Polysilicon
p+
;; ;;; n+ n+
;;;
0 vGS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 0.1V iD
;;
;;;;
;;;
Polysilicon
p+ n+ n+

0 vGS
0 VT 2VT 3VT Fig.3.1-03
Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT
;;;
VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
;; ;;;
;;;;
iD
Polysilicon VGS = 2VT
;; ;;;
p+ n+ n+
;;;
0 vDS
0 0.5VT VT
VDS=0.5VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT
p+
;;
;;;;
;;;
n+ n+
;;;
p- substrate Channel current
0 vDS
0 0.5VT VT
VDS=VT:
;;;
VB = 0 VS = 0 VG = 2VT VD =VT iD
;;
;;;;
;;;
iD VGS = 2VT
Polysilicon
p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04

Output Characteristics of the Enhanced NMOS when vDS = 2VT
;;;
VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
;; ;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate VGS =VT
0 vDS
0 VT 2VT 3VT
VGS=2VT:
;;
;;;;;;;
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
;;;;;;;;;
VGS =2VT
p+ n+ n+
;;;
p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
;;;;;;
;;;
iD
Polysilicon
p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05
Output Characteristics of an Enhancement NMOS Transistor

2000
VGS = 3.0
1500
VGS = 2.5
iD(μA)
1000
VGS = 2.0
500
VGS = 1.5
SPICE Input File: VGS = 1.0

0
0 1 2 3 4 5
vDS (Volts) Fig. 3.1-6
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 +lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end

Transconductance Characteristics of an Enhancement NMOS Transistor

6000
VDS = 5V
5000
VDS = 4V
VDS = 3V
4000
iD(μA)
3000
VDS = 2V
2000
VDS = 1V
1000
0
SPICE Input File: 0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end
;;;
SIMPLE LARGE SIGNAL MODEL (SAH MODEL)
;;;
Large Signal Model Derivation +
vGS +
1.) Let the charge per unit area in the channel -
iD - vD
inversion layer be
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) n+ n+
v(y)
Source dy Drain
p- y
2.) Define sheet conductivity of the inversion 0 y y+dy L
layer per square as Fig.110-03

cm2
coulombs amps 1

S = μoQI(y) v·s cm2 = volt = /sq.
3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS = W = -SEy = -S dy dv = SW dy = μoQI(y)W iD dy = -WμoQI(y)dv
4.) Integrating along the channel for 0 to L gives
L vDS vDS

iDdy = - W μoQI(y)dv = W μoCox[vGS-v(y)-VT]dv

0 0 0
5.) Evaluating the limits gives
W μoCox v2(y)vDS W μoCox vDS2
iD = L (vGS-V T)v(y)-
2 0 iD= L (vGS-V T)vDS- 2


Saturation Voltage - VDS(sat) iD

Interpretation of the large vDS = vGS-VT
signal model:
Active Region Saturation Region
Increasing
values of vGS
vDS
The saturation voltage for Fig. 110-04
MOSFETs is the value of drain-source voltage at
the peak of the inverted parabolas. vDS
diD μoCoxW
dvDS = L [(vGS-V T) - vDS] = 0 Cutoff Saturation Active
T
V
S-
vDS(sat)=vGS-VT
vG
S=
Useful definitions:
vD
0 vGS
μoCoxW K’W 0 VT Fig. 3.2-4
L = L =
The Simple Large Signal MOSFET Model

Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents)
2.) Active Region Output Characteristics of the MOSFET:
0 < vDS < vGS - VT iD/ID0
vDS = vGS-VT
μoCoxW vGS-VT
= 1.0
iD = 2L 2(vGS-VT)-vDS vDS 1.0 Active
Saturation Region VGS0-VT
Region vGS-VT
= 0.86
3.) Saturation Region 0.75
Channel modulation effects
VGS0-VT
vGS-VT
0 < vGS - VT < vDS 0.5 VGS0-VT
= 0.70
vGS-VT
μoCoxW VGS0-VT
= 0.5
iD = 2
2L vGS-VT

0.25 vGS-VT
=0
Cutoff Region VGS0-VT
vDS
0
0 0.5 1.0 1.5 2.0 2.5 VGS0-VT
Fig. 110-05

Illustration of the Need to Account for the Influence of vDS on the Simple Sah Model
Compare the Simple Sah model to SPICE level 2:
25μA
2
K' = 44.8μA/V
20μA 2
k = 0, v DS(sat) K' = 44.8μA/V
= 1.0V k=0.5, v DS(sat)
= 1.0V
15μA
iD
10μA SPICE Level 2
K' = 29.6μA/V 2
5μA k = 0, vDS(sat)
= 1.0V
0μA
0 0.2 0.4 0.6 0.8 1
vDS (volts)
V GS = 2.0V, W/L = 100μm/100μm, and no mobility effects.
Modification of the Previous Model to Include the Effects of vDS on VT

From the previous derivation:
L vDS vDS

i dy = - W μoQI(y)dv = W μoCox[vGS-v(y)-VT]dv
D
0 0 0
Assume that the threshold voltage varies across the channel in the following way:
V T(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.
Integrating the above gives,
W μoCox v2(y)vDS
iD = L (vGS-V T)v(y)-(1+k) 2 0

or
W μoCox v2DS
iD = L (vGS-V T)vDS-(1+k) 2

To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS-VT
vDS(sat) = 1+k
Therefore, in the saturation region, the drain current is
W μoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8μA/V2, excellent correlation is achieved with SPICE 2
Influence of vDS on the Output Characteristics

Channel modulation effect:
;;;
VG > VT VD > VDS(sat)
As the value of vDS increases, the
effective L decreases causing the
;;;;;;;
B S
current to increase. Depletion
Polysilicon Region
Illustration:
Note that Leff = L - Xd

p+
;;;;;;;
eff
n+
L
n+
Therefore the model in saturation p- substrate Xd

becomes, Fig110-06
K’W diD K’W dLeff iD dXd

iD = 2Leff (vGS-V T)2 dvDS = - 2 (vGS - VT)2 dvDS = Leff dvDS iD
2Leff
Therefore, a good approximation to the influence of vDS on iD is
diD K’W
iD iD( = 0) + dvDS vDS = iD( = 0)(1 + vDS) = 2L (vGS-V T)2(1+vDS)
Channel Length Modulation Parameter,

Assume the MOS is transistor is saturated-
μCoxW
iD = 2L (vGS - VT)2(1 + vDS)
Define iD(0) = iD when vDS = 0V.
μCoxW
iD(0) = 2L (vGS- VT)2
Now,
iD = iD(0)[1 + vDS] = iD(0) + iD(0) vDS
Matching with y = mx + b gives the value of
iD
iD3(0) VGS3
iD2(0)
iD1(0) VGS2
VGS1
vDS
-1

Influence of Channel Length on

Note that the value of varies with channel length, L. The data below is from a 0.25μm
CMOS technology.
Channel Length Modulation (V-1)

0.6
0.5
0.4
PMOS
0.3
0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6
Most analog designers stay away from minimum channel length to get better gains and
matching at the sacrifice of speed.
Influence of the Bulk Voltage on the Large Signal MOSFET Model

The components of the threshold voltage V = 0: VGS
SB0 VBS0 = 0V
are: VD > 0
V T = Gate-bulk work function (MS) Polysilicon
iD
+ voltage to change the surface p+ n+ n+

potential (-2F)
p- substrate
+ voltage to offset the channel-bulk
depletion charge (-Qb/Cox) VSB1 > 0: VBS1 > 0V VGS
VD > 0
+ voltage to compensate the Polysilicon
iD
undesired interface charge
(-Qss/Cox) p+ n+ n+
We know that p- substrate
Qb = |2F|+|vBS| VSB2 >VSB1: VSB2 >VSB1: VGS

VD > 0
Therefore, as the bulk becomes more iD = 0
reverse biased with respect to the Polysilicon
source, the threshold voltage must p+ n+ n+

increase to offset the increased channel-
bulk depletion charge. p- substrate
060613-02

Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage
VBS = 0
ID
vDS > vGS-VT
VGS
vGS
VT0 VT1 VT2 VT3
060612-02
In general, the simple model incorporates the bulk effect into V T by the previously
developed relationship:
V T(vBS) = VT0 + 2|f|+|vBS| - 2|f|
Summary of the Simple Large Signal MOSFET Model D

+
N-channel reference convention: iD
G B
Non-saturation- + +
vDS

Wμ oCox vDS2 vGS vBS
iD = L
(v
GS -V )v
T DS - 2
(1 + v
DS ) - -
S Fig. 110-10
Saturation-

Wμ oCox vDS(sat)2 W μoCox
iD = (v -V )v (sat)- (1+v )= 2
L GS T DS 2 DS 2L (vGS-V T) (1+vDS)
where:
μo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
= channel-length modulation parameter (volts-1)

V T = VT0 + 2|f|+|vBS|- 2|f|

V T0 = zero bias threshold voltage
= bulk threshold parameter (volts-0.5)
2|f| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert
the current.

Silicon Constants
Constant Constant Description Value Units

Symbol
VG Silicon bandgap (27°C) 1.205 V
k Boltzmann’s constant 1.381x10-23 J/K
ni Intrinsic carrier concentration (27°C) 1.45x1010 cm-3
o Permittivity of free space 8.854x10-14 F/cm
si Permittivity of silicon 11.7 o F/cm
ox Permittivity of SiO2 3.9 o F/cm
MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.25μm CMOS n-well):
Parameter Typical Parameter Value Units

Parameter Description
Symbol N-Channel P-Channel
V T0 Threshold Voltage 0.5± 0.15 -0.5 ± 0.15 V
(VBS = 0)
K' Transconductance Para- 120.0 ± 10% 25.0 ± 10% μA/V2
meter (in saturation)
Bulk threshold 0.4 0.6 (V)1/2
parameter
Channel length 0.32 (L=Lmin) 0.56 (L=Lmin) (V)-1
modulation parameter 0.06 (L 2Lmin) 0.08 (L 2Lmin)
2|F| Surface potential at 0.7 0.8 V
strong inversion

SUBTHRESHOLD MODEL
Large-Signal Model for Weak Inversion
The electrons in the substrate at the source side can be expressed as,

s
np(0) = npoexp
V t
The electrons in the substrate at the drain side can be expressed as,

s-vDS
np(L) = npoexp
V t
Therefore, the drain current due to diffusion is,

np(L)-np(0) W s vDS
iD = qADn
L =
L qXDnnpoexp
V t 1-exp
- V t
where X is the thickness of the region in which iD flows.
In weak inversion, the changes in the surface potential, s are controlled by changes in
the gate-source voltage, vGS, through a voltage divider consisting of Cox and Cjs, the
depletion region capacitance.
ds Cox 1 vGS vGS-V T Poly
dvGS = Cox+Cjs = n s = n + k1 = n + k2 Oxide Cox vGS
Channel
where Dep. Cjs φs
VT
k2 = k1 + n
Substrate
CMOS Analog Circuit Design 060405-04
© P.E. Allen - 2010
Large-Signal Model for Weak Inversion – Continued

Substituting the above relationships back into the expression for iD gives,

W
k2
vGS-V T
vDS
iD = L qXDnnpo exp
V t exp
nVt 1-exp
- V t
Define It as

k2
It = qXDnnpo exp
V t
to get,

W
vGS-V T
vDS
iD = L It exp nVt 1-exp- V t

where n 1.5 – 3 iD
If vDS > 0, then VGS=VT
1μA
W

vGS-V T
vDS
iD = It L exp
nVt
1+VA
The boundary between nonsaturated VGS<VT
and saturated is found as,
V ov = VDS(sat) = VON = VGS -VT = 2nVt
0 vDS
0 1V
Fig. 140-03

SHORT CHANNEL, STRONG INVERSION MODEL

What is Velocity Saturation?
Electron Drift Velocity (m/s)

The most important short-channel 105
effect in MOSFETs is the velocity
saturation of carriers in the channel. 5x104
A plot of electron drift velocity
versus electric field is shown below. 2x104
104
An expression for the electron drift 5x103
velocity as a function of the electric 105 106 107
field is, Electric Field (V/m) Fig130-1
μnE
vd 1+E/E
c
where
vd = electron drift velocity (m/s)
μn = low-field mobility ( 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
Short-Channel Model Derivation

As before,
iD WQI(y)μnE

E
JD = JS = W = QI(y)vd(y) iD = WQI(y)vd(y) = 1+E/Ec iD
1+Ec = WQI(y)μnE
Replacing E by dv/dy gives,

1 dv dv
iD
1+Ecdy = WQI(y)μndy
Integrating along the channel gives,
L

1 dv vDS

i 1+Ecdy dy = WQI(y)μndv
D

0 0
The result of this integration is,
μnCox W μnCox W
2
iD =
1 vDS L [2(v -V )v -v
GS T DS DS ] = 21+vDS L [2(vGS-V T)vDS-vDS2]

2
1+Ec L
where = 1/(EcL) with dimensions of V-1.

Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,

1 (VGS-V T)
V’DS(sat) = 1+2(VGS-V T-1 (VGS-V T)1- 2 +···
if
(VGS-V T)
2 <1
Therefore,

(VGS-V T)

V’DS(sat) VDS(sat) 1- 2

+···
Note that the transistor will enter the saturation region for vDS < vGS - VT in the
presence of velocity saturation.
Large Signal Model for the Saturation Region

Assuming that
(VGS-V T)
2 <1
gives
V’DS(sat) (VGS-V T)
Therefore the large signal model in the saturation region becomes,

K’ W (VGS-V T)
iD = 2[1+(vGS-V T)] L [ vGS - VT]2, vDS (VGS-V T) 1-

2 +···


The Influence of Velocity Saturation on the Transconductance Characteristics

The following plot was made for K’ = 110μA/V2 and W/L = 1:
1000
θ=0
θ = 0.2
800
θ = 0.4
iD/W (μA/μm) 600

θ = 0.6
400
θ = 0.8
θ = 1.0
200
0
0.5 1 1.5 2 2.5 3
vGS (V) Fig130-2
Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.
Circuit Model for Velocity Saturation

A simple circuit model to include the influence of velocity saturation is
is shown:
We know that
K’W
iD = 2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX
or
vGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives,
K’W
iD = 2L (vGS - iDRSX -V T)2
Solving for iD results in,
K’ W
iD = W L (vGS - V T)2

21+K’ L RSX(vGS-V T)
Comparing with the previous result, we see that
W L 1
= K’ L RSX RSX = K’W = EcK’W
Therefore for K’ = 110μA/V2, W = 1μm and Ec = 1.5x106V/m, we get RSX = 6.06k.

SUMMARY
• The modeling of this lecture is devoted to understanding how the circuit works
• The two primary current-voltage characteristics of the MOSFET are the
transconductance characteristic and the output characteristic
• The simple Sah large signal model is good enough for most applications and technology
• The Sah model can be improved in the region of the knee and for the weak dependence
of drain current on drain-source voltage in the saturation region
• Most designers do not work at minimum channel length because of the channel length
modulation effect and because worse matching occurs for small areas
• The threshold voltage is increased as the bulk-source is reverse biased
• The subthreshold model accounts for very small currents that flow in the channel when
the gate-source voltage is smaller than the threshold voltage
• The subthreshold current is exponentially related to the gate-source voltage
• Velocity saturation occurs at minimum channel length and can be modeled by including
a source degeneration resistor with the simple large signal model

03LSMOS Model

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Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-1

LECTURE 090 – LARGE SIGNAL MOSFET MODEL

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-2

Updating Model Thinking Model Updating Technology

Comparison of Design Decisions- Extraction of Simple

CMOS Analog Circuit Design © P.E. Allen - 2010

Categorization of Electrical Models

Linear Small-signal, midband Small-signal frequency

Nonlinear DC operating point Large-signal transient

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-4

OPERATION OF THE MOS TRANSISTOR

Strong Threshold (VG>VT)

p- substrate Inverted Region

Transconductance Characteristics of an Enhancement NMOSFET when VDS = 0.1V

p- substrate Inverted Region

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-6

Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT

CMOS Analog Circuit Design © P.E. Allen - 2010

Output Characteristics of the Enhanced NMOS when vDS = 2VT

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-8

Output Characteristics of an Enhancement NMOS Transistor

SPICE Input File: VGS = 1.0

CMOS Analog Circuit Design © P.E. Allen - 2010

Transconductance Characteristics of an Enhancement NMOS Transistor

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-10

CMOS Analog Circuit Design © P.E. Allen - 2010

Saturation Voltage - VDS(sat) iD

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-12

The Simple Large Signal MOSFET Model

CMOS Analog Circuit Design © P.E. Allen - 2010

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-14

Modification of the Previous Model to Include the Effects of vDS on VT

Influence of vDS on the Output Characteristics

Note that Leff = L - Xd

Therefore the model in saturation p- substrate Xd

K’W diD K’W dLeff iD dXd

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-16

Channel Length Modulation Parameter,

Influence of Channel Length on

Channel Length Modulation (V-1)

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-18

Influence of the Bulk Voltage on the Large Signal MOSFET Model

+ voltage to change the surface p+ n+ n+

We know that p- substrate

Qb = |2F|+|vBS| VSB2 >VSB1: VSB2 >VSB1: VGS

source, the threshold voltage must p+ n+ n+

CMOS Analog Circuit Design © P.E. Allen - 2010

V T(vBS) = VT0 + 2|f|+|vBS| - 2|f|

CMOS Analog Circuit Design © P.E. Allen - 2010

Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-20

Summary of the Simple Large Signal MOSFET Model D

V T = VT0 + 2|f|+|vBS|- 2|f|

CMOS Analog Circuit Design © P.E. Allen - 2010

V T = VT0 + 2|f|+|vBS|- 2|f|