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„| 5-'6 
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„| 22$ 

„| 3.4 Para 
„| 3.5 1  ader
„| 3.6  -
„| 3.7 aWre
@| 4 Debugg g  erfaces
„| 4.1 debugWI
„| 4.2 JTAG
@| 5 Deve en s and evaua  n k s
„| 5.1 STK600 s ar er k
„| 5.2 STK500 s ar er k
„| 5.3 AV ISP and AV ISP mkII
„| 5.4 AV Dragon
„| 5.5 JTAGI' mkI
„| 5.6 JTAGI' mkII
„| 5.7 1u erf demo board
„| 5.8 AT90US1Key
„| 5.9 aven wreess k
„| 5.10 Thrd-par y programmers
@| 6 A me AV usage
@| 7 FPGA cones
@| 8 See aso
@| 9 eferences
@| 10 Fur her readng
@| 11 Ex erna nks

v   
  
The AV arch ec ure was conceved by wo s uden s a he Norwegan Ins  u e of
Technoogy (NTH) Af-Eg 1ogen and Vegard Woan.[1][2]

The orgna AV -'U was deveoped a a oca ASI' house n Trondhem, Norway caed
Nordc VLSI a he me, now Nordc Semconduc or, where he wo founders of A me
Norway were workng as s uden s[`  ]. I was known as a ȝIS' (-cro IS')[`  
]
and was avaabe as scon IP/budng bock from Nordc VLSI[`  ]. When he
echnoogy was sod o A me from Nordc VLSI[`   ], he n erna arch ec ure was
fur her deveoped by Af and Vegard a A me Norway, a subsdary of A me founded by he
wo arch ec s. The desgners worked cosey w h comper wr ers a IA Sys ems o ensure
ha he ns ruc on se provded for more effcen compa on of hgh-eve anguages.[3]
A me says ha he name AV s no an acronym and does no s and for any hng n
par cuar. The crea ors of he AV gve no defn ve answer as o wha he erm "AV"
s ands for.[2] However, s common accep ed ha AV s ands for cf (Eg 1ogen) and
egard (Woan) 's sc processor" [4]

No e ha he use of "AV" n hs ar ce generay refers o he 8-b IS' ne of A me
AV -crocon roers.

Among he frs of he AV ne was he AT90S8515, whch n a 40-pn DIP package has he
same pnou as an 8051 mcrocon roer, ncudng he ex erna mu pexed address and da a
bus. The poar y of he ESET ne was oppos e (8051's havng an ac ve-hgh ESET,
whe he AV has an ac ve-ow ESET), bu o her han ha , he pnou was den ca.

v      


The AV s a modfed Harvard arch ec ure machne w h program and da a s ored n
separa e physca memory sys ems ha appear n dfferen address spaces, bu havng he
ab y o read da a  ems from program memory usng speca ns ruc ons.

v 



AVs are generay cassfed n o fve broad groups

@|  c  ² he AT ny seres


„| 0.5±8 k1 program memory
„| 6±32-pn package
„| Lm ed perphera se

@|  c  ² he ATmega seres


„| 4±256 k1 program memory
„| 28±100-pn package
„| Ex ended ns ruc on se (-u py ns ruc ons and ns ruc ons for handng
arger program memores)
„| Ex ensve perphera se

@| Î c ² he ATxmega seres


„| 16±384 k1 program memory
„| 44±64±100-pn package (A4, A3, A1)
„| Ex ended performance fea ures, such as D-A, "Even Sys em", and
cryp ography suppor .
„| Ex ensve perphera se w h DA's

@| c 
 c 
„| megaAVs w h speca fea ures no found on he o her members of he AV
famy, such as L'D con roer, US1 con roer, advanced PW-, 'AN e c.

@| V c  V c


„| FPGA 5K o 40K ga es
„| SA- for he AV program code, unke a o her AVs
[5]
„| AV core can run a up o 50 -Hz

@|  c 

K  ` 
 
In 2006 A me reeased mcrocon roers based on he new, 32-b , AV32
arch ec ure. They ncude SI-D and DSP ns ruc ons, aong w h o her audo and
vdeo processng fea ures. Ths 32-b famy of devces s n ended o compe e w h
he A- based processors. The ns ruc on se s smar o o her IS' cores, bu s
no compa be w h he orgna AV or any of he varous A- cores.
v      

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In he X-EGA varan , he workng regs er fe s no mapped n o he da a address space; as
such,  s no possbe o rea any of he X-EGA's workng regs ers as hough hey were
SA-. Ins ead, he I/O regs ers are mapped n o he da a address space s ar ng a he very
begnnng of he address space. Add onay, he amoun of da a address space dedca ed o
I/O regs ers has grown subs an ay o 4096 by es (000016-0FFF16). As w h prevous
genera ons, however, he fas I/O manpua on ns ruc ons can ony reach he frs 64 I/O
regs er oca ons ( he frs 32 oca ons for b wse ns ruc ons). Foowng he I/O regs ers,
he X-EGA seres se s asde a 4096 by e range of he da a address space whch can be used
op onay for mappng he n erna EEPO- o he da a address space (100016-1FFF16). The
ac ua SA- s oca ed af er hese ranges, s ar ng a 200016.

v   

Amos a AV mcrocon roers have n erna EEPO- for sem-permanen da a s orage.
Lke fash memory, EEPO- can man an  s con en s when eec rca power s removed.

In mos varan s of he AV arch ec ure, hs n erna EEPO- memory s no mapped n o
he -'U's addressabe memory space. I can ony be accessed he same way an ex erna
perphera devce s, usng speca pon er regs ers and read/wr e ns ruc ons whch makes
EEPO- access much sower han o her n erna A-.

However, some devces n he SecureAV (AT90S') famy [6] use a speca EEPO-
mappng o he da a or program memory dependng on he confgura on. The X-EGA
famy aso aows he EEPO- o be mapped n o he da a address space.

Snce he number of wr es o EEPO- s no unm ed ² A me specfes 100,000 wr e


cyces n her da ashee s ² a we desgned EEPO- wr e rou ne shoud compare he
con en s of an EEPO- address w h desred con en s and ony perform an ac ua wr e f
con en s need o be changed.

v      

A me's AVs have a wo s age, snge eve ppene desgn. Ths means he nex machne
ns ruc on s fe ched as he curren one s execu ng. -os ns ruc ons ake jus one or wo
cock cyces, makng AVs rea vey fas among he egh -b mcrocon roers.

The AV famy of processors were desgned w h he effcen execu on of comped '
code n mnd and has severa bu -n pon ers for he ask.

v 
 


K  ` 
    ` 

The AV Ins ruc on Se s more or hogona han hose of mos egh -b mcrocon roers, n
par cuar he 8051 cones and PI' mcrocon roers w h whch AV compe es oday.
However,  s no compe ey reguar

@| Pon er regs ers X, Y, and Z have addressng capab es ha are dfferen from each
o her.
@| egs er oca ons 0 o 15 have dfferen addressng capab es han regs er
oca ons 16 o 31.
@| I/O por s 0 o 31 have dfferen addressng capab es han I/O por s 32 o 63.
@| 'L affec s fags, whe SE does no , even hough hey are compemen ary
ns ruc ons. 'L se a b s o zero and SE se s hem o one. (No e ha 'L s
pseudo-op for EO , ; and SE s shor for LDI ,$FF. -a h opera ons such as
EO modfy fags whe moves/oads/s ores/branches such as LDI do no .)
@| Accessng read-ony da a s ored n he program memory (fash) requres speca LP-
ns ruc ons; he fash bus s o herwse reserved for ns ruc on memory.

Add onay, some chp-specfc dfferences affec code genera on. 'ode pon ers (ncudng
re urn addresses on he s ack) are wo by es ong on chps w h up o 128 k1y es of fash
memory, bu hree by es ong on arger chps; no a chps have hardware mu pers; chps
w h over 8 k1y es of fash have branch and ca ns ruc ons w h onger ranges; and so for h.

The mos y-reguar ns ruc on se makes programmng  usng ' (or even Ada) compers
fary s ragh forward. G'' has ncuded AV suppor for qu e some me, and ha suppor
s wdey used. In fac , A me soc ed npu from major deveopers of compers for sma
mcrocon roers, o de ermne he ns ruc on se fea ures ha were mos usefu n a comper
for hgh-eve anguages.

v  
 

The AV ne can normay suppor cock speeds from 0-20 -Hz, w h some devces
reachng 32 -Hz. Lower powered opera on usuay requres a reduced cock speed. A
recen (Tny,-ega and Xmega, bu no 90S) AVs fea ure an on-chp osca or, removng
he need for ex erna cocks or resona or crcu ry. Some AVs aso have a sys em cock
prescaer ha can dvde down he sys em cock by up o 1024. Ths prescaer can be
reconfgured by sof ware durng run- me, aowng he cock speed o be op mzed.

Snce a opera ons (excudng  eras) on regs ers 0 - 31 are snge cyce, he AV can
acheve up o 1 -IPS per -Hz, .e. an 8 -Hz processor can acheve up o 8 -IPS. Loads
and s ores o/from memory ake 2 cyces, branchng akes 2 cyces. 1ranches n he a es "3-
by e P'" par s such as ATmega2560 are one cyce sower han on prevous devces.

v     

AVs have a arge foowng due o he free and nexpensve deveopmen oos avaabe,
ncudng reasonaby prced deveopmen boards and free deveopmen sof ware. The AVs
are sod under varous names ha share he same basc core bu w h dfferen perphera and
memory combna ons. 'ompa b y be ween chps n each famy s fary good, a hough
I/O con roer fea ures may vary.

See ex erna nks for s es rea ng o AV deveopmen .

v V 


'urren AVs offer a wde range of fea ures


@| -u func on, b-drec ona genera purpose I/O por s w h confgurabe, bu -n
pu-up ress ors
@| -u pe n erna osca ors, ncudng ' osca or w hou ex erna par s
@| In erna, sef-programmabe ns ruc on fash memory up o 256 k1 (384 k1 on
X-ega)
„| In-sys em programmabe usng sera/parae ow-vo age propre ary
n erfaces or JTAG
„| Op ona boo code sec on w h ndependen ock b s for pro ec on
@| On chp debuggng (O'D) suppor hrough JTAG or debugWIE on mos devces
„| The JTAG sgnas (T-S, TDI, TDO, and T'K) are mu pexed on GPIOs.
These pns can be confgured o func on as JTAG or GPIO dependng on he
se ng of a fuse b , whch can be programmed va ISP or HVSP. 1y defau ,
AVs w h JTAG come w h he JTAG n erface enabed.
„| debugWIE uses he /ESET pn as a b-drec ona communca on channe
o access on-chp debug crcu ry. I s presen on devces w h ower pn
coun s, as  ony requres one pn.
@| In erna da a EEPO- up o 4 k1
@| In erna SA- up o 16 k1 (32 k1 on X-ega)
@| Ex erna 64 k1  e endan da a space on cer an modes, ncudng he -ega8515
and -ega162.
„| The ex erna da a space s overad w h he n erna da a space, such ha he
fu 64 k1 address space does no appear on he ex erna bus. An accesses o
e.g. address 010016 w access n erna A-, no he ex erna bus.
„| In cer an members of he X-EGA seres, he ex erna da a space has been
enhanced o suppor bo h SA- and SDA-. As we, he da a addressng
modes have been expanded o aow up o 16 -1 of da a memory o be
drec y addressed.
„| AV's generay do no suppor execu ng code from ex erna memory. Some
ASSP's usng he AV core do suppor ex erna program memory.
@| 8-1 and 16-1 mers
„| PW- ou pu (some devces have an enhanced PW- perphera whch
ncudes a dead- me genera or)
„| Inpu cap ure
@| Anaog compara or
@| 10 or 12-1 A/D conver ers, w h mu pex of up o 16 channes
@| 12-b D/A conver ers
@| A vare y of sera n erfaces, ncudng
„| I ' compa be Two-Wre In erface (TWI)
„| Synchronous/asynchronous sera perpheras (UAT/USAT) (used w h S-
232, S-485, and more)
„| Sera Perphera In erface 1us (SPI)
„| Unversa Sera In erface (USI) for wo or hree-wre synchronous da a
ransfer
@| 1rownou de ec on
@| Wa chdog mer (WDT)
@| -u pe Power-Savng Seep -odes
@| Lgh ng and mo or con ro (PW- specfc) con roer modes
@| 'AN con roer suppor
@| US1 con roer suppor
„| #    8)-% /9
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ese pn for he cock npu (PDI_'LK), and he dedca ed pn for da a npu and ou pu
(PDI_DATA).[8]

v    

Hgh-Vo age programmng s mos y he backup mode on smaer AVs. An 8-pn AV
package doesn' eave many unque sgna combna ons o pace he AV n o a
programmng mode. A 12 vo sgna, however, s some hng he AV shoud ony see durng
programmng and never durng norma opera on.

v   

Parae programmng s consder he "fna resor " and may be he ony way o fx AV chps
w h bad fuse se ngs. Parae programmng may be fas er and benefca when programmng
many AV devces for produc on use.

v    

-os AV modes can reserve a boo oader regon, 256 1 o 2 K1, where re-programmng
code can resde. A rese , he boo oader runs frs , and does some user-programmed
de ermna on whe her o re-program, or jump o he man appca on. The code can re-
program hrough any n erface avaabe,  coud read an encryp ed bnary hrough an
E herne adap er f  fe ke  . A me has appca on no es and code per anng o many bus
n erfaces.[9][10][11][12]

v  

The AT90S' seres of AVs are avaabe w h a fac ory mask-O- ra her han fash for
program memory.[13] 1ecause of he arge up-fron cos and mnmum order quan  y, a mask-
O- s ony cos -effec ve for hgh produc on runs.

v  

aWre s a new one-wre debug n erface avaabe on he new U'3L AV32 devces.

v   



The AV offers severa op ons for debuggng, mos y nvovng on-chp debuggng whe
he chp s n he arge sys em.

v  

debugWIET- s A me's sou on for provdng on-chp debug capab es va a snge
mcrocon roer pn. I s par cuary usefu for ower pn coun par s whch canno provde
he four "spare" pns needed for JTAG. The JTAGI'E mkII and he AV Dragon suppor
debugWIE. debugWIE was deveoped af er he orgna JTAGI'E reease, and now
cones suppor  .
v c

JTAG provdes access o on-chp debuggng func ona y whe he chp s runnng n he
arge sys em.[14] JTAG aows accessng n erna memory and regs ers, se ng breakpon s
on code, and snge-s eppng execu on o observe sys em behavour.

A me provdes a seres of JTAG adap ers for he AV

1.| The JTAGI'E mkII repaces he JTAGI'E, and s smary prced. The JTAGI'E
mkII n erfaces o he P' va US1, and suppor s bo h JTAG and he newer
debugWIE n erface. Numerous 3rd-par y cones of he A me JTAGI'E mkII
devce s ar ed shppng af er A me reeased he communca on pro oco.[15]
2.| The AV Dragon s a ow-cos (approxma ey $50) subs  u e for he JTAGI'E mkII
for cer an arge par s. The AV Dragon provdes n-sys em sera programmng,
hgh-vo age sera programmng and parae programmng, as we as JTAG or
debugWIE emua on for par s w h 32 K1 of program memory or ess.
3.| The JTAGI'E adap er n erfaces o he P' va a s andard sera por . I s somewha
expensve by hobbys s andards a around US$300, a hough much more affordabe
han many o her mcron roer emua on sys ems. The JTAGI'E has been EOL'ed,
hough  s s  suppor ed n AV S udo and o her oos.

JTAG can aso be used o perform a 1oundary Scan es ,[16] whch es s he eec rca
connec ons be ween AVs and o her 1oundary Scan capabe chps n a sys em. 1oundary
scan s we-su ed for a produc on ne; he hobbys s probaby be er off es ng w h a
mu me er or oscoscope.

v      
  

Offca A me AV deveopmen oos and evaua on k s conss s of a number of s ar er
k s and debuggng oos w h suppor for mos AV devces

v 
 

The STK600 s ar er k and deveopmen sys em s an upda e o he STK500 [1]. The


STK600 uses a base board, a sgna rou ng board, and a arge board.

The base board s smar o he STK500, n ha  provdes a power suppy, cock, n-sys em
programmng, wo S-232 por s, and s ake pns for a of he GPIO sgnas from he arge
devce.

The arge boards have ZIF socke s for DIP, SOI', QFN, or QFP packages, dependng on he
board.

The sgna rou ng board s s be ween he base board and he arge board, and rou es he
sgnas o he proper pn on he devce board. There are many dfferen sgna rou ng boards
ha coud be used w h a snge arge board, dependng on wha devce s n he ZIF socke .

The STK600 n erfaces w h he P' va US1, eavng bo h S-232 por s avaabe for he
arge mcrocon roer.
v   
  

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The AV 1u erfy demons ra es L'D drvng by runnng a 14-segmen , sx apha-numerc
charac er dspay. However, he L'D n erface consumes many of he I/O pns.

The 1u erfy's ATmega169 'PU s capabe of speeds up o 8 -Hz, however  s fac ory se
by sof ware o 2 -Hz o preserve he bu on ba ery fe. A pre-ns aed boo oader program
aows he board o be re-programmed va a s andard S-232 sera pug w h new programs
ha users can wr e w h he free A me IDE oos.

v c! 

Ths sma board, abou haf he sze of a busness card, s prced a sgh y more han an
AV 1u erfy. I ncudes an AT90US11287 w h US1-On-The-Go (OTG) suppor , 16 -1
of Da aFash, LEDs, a sma joys ck, and a empera ure sensor. The board ncudes sof ware
whch e s  ac as a US1 -ass S orage devce ( s documen a on s shpped on he
Da aFash), a US1 joys ck, and more. To suppor he US1 hos capab y,  mus be
opera ed from a ba ery; bu when runnng as a US1 perphera,  ony needs he power
provded over US1.

Ony he JTAG por uses conven ona 2.54 mm pnou . A he o her AV I/O por s requre
more compac 1.27 mm headers.

The AV Dragon can bo h program and debug snce he 32 kb m a on was removed n
AV S udo 4.18, and he JTAGI'E mkII s capabe of bo h programmng and debuggng he
processor. The processor can aso be programmed hrough US1 from a Wndows or Lnux
hos , usng he US1 "Devce Frmware Upda e" pro ocos. A me shps propre ary (source
code ncuded bu ds rbu on res rc ed) exampe programs and a US1 pro oco s ack w h
he devce.

LUFA s a hrd par y free sof ware (-IT cense) US1 pro oco s ack for he US1Key and
o her 8-b US1 AVs.

v   



The AVEN k suppor s wreess deveopmen usng A me's IEEE 802.15.4 chpse s, for
Zg1ee and o her wreess s acks. I resembes a par of wreess more-powerfu 1u erfy
cards, pus a wreess US1Key; and cos ng abou ha much (under $US100). A hese
boards suppor JTAG based deveopmen .

The k ncudes wo AV aven boards, each w h 2.4 GHz ranscever suppor ng IEEE
802.15.4 (and a freey censed Zg1ee s ack). The rados are drven w h ATmega1284p
processors, whch are suppor ed by a cus om segmen ed L'D dspay drven by an
ATmega3290p processor. aven perpheras resembe he 1u erfy pezo speaker, Da aFash
(bgger), ex erna EEPO-, sensors, 32 kHz crys a for T', and so on. These are n ended
for use n deveopng remo e sensor nodes, o con ro reays, or wha ever s needed.

The US1 s ck uses an AT90US11287 for connec ons o a US1 hos and o he 2.4 GHz
wreess nks. These are n ended o mon or and con ro he remo e nodes, reyng on hos
power ra her han oca ba eres.

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