Two Mark questions

1.Define Critical Paths

It is the longest path in the Circuit which decides the most critical function,and
requires the attention to timing details.

2.What are the main levels that a critical paths affect a system?

1.The Architectural/micro-architectural Level

2.The Logical level

3.The circuit level

4.The Layout Level

3.Define RC Delay Model

It is an analytical method used to estimate the delay of Logic gates.The RC delay

model treats transistors as Swicthes in series with resistors.Once the delay in the
circuit is estimated the circuit can be modified to operate faster.

4.What is Intrinsic Delay?

The RC(Resistance and Capacitance)product of an Mos Transistor is called

intrinsic delay .

5.Define Elmore delay model?

It is an analytical method used to estimate the RC delay in a network. Elmore delay

model estimates the delay of a RC ladder as the sum over each node in the ladder
of the resistance Rn-1 between the node and a supply multiplied by the capacitor
on the nodes.

8.define linear delay.

It is the sum of effort delay and parasitic delay.

d=f+p
9.define effort delay.

The delay that depends on the load and on properties of the logic gate driving the
load.it is related in two terms: the logic effort of the logic gate and the electrical
effort h characteristics the load.

f=gh

10.define electrical effort

Electrical effort is the ratio of output capacitance to the input capacitance of the
gate.the electrical effort h describes how the environment of the logic gate affects
the performance and how the size of the transistors in the gate determines its load
driving capability.

11.define logical effort.

Logical effort of a gate is defined as the ratio of the input capacitance of the gate to
the input capacitance of an inverter that can deliver the same output current.

12.define parasitic delay.

The parasitic delay is the ratio of the parasitic capacitance to the input capacitance
of the inverter which is just Pinv.

13. define path logical effort

The logical effort along a path compounds by multiplying the logical efforts of all
the logic gates along the path.the path logical effort G is defined as

G=πgi

21.what is dynamic power dissipation

Power dissipation due to circuit switching to charge and discharge the output load
capacitance at a particular node at operating is called dynamic power dissipation.

The dynamic power dissipation at a particular output node is given by

22.define activity factor

The node transition activity factor is a statistical parameter and is data rate
dependent and defines the probability of the gate’s output to make logic trasition
during one clock cycle.

23.what is short circuit power dissipation

during switching both nMOS and pMOs transistor will conduct simultaneously and
provide a direct path between Vdd and the ground rail resulting in short circuit
power dissipation

25 what are the methods to reduce static power dissipation

1.by selecting multi threshold voltages on critical paths with low-vt transistors
while leakage on other paths with high vt transistors

2.By using two operating modes active and stanby for each blocks

3. By adjusting the body bias (i.e) adjusting FBB in active mode to increase
performance and RBB in standby mode to reduce leakage.

4.By using sleep transistors to isolate the supply from the block to achieve
significant leakage savings.