* Source: Instat/MDR
Ethernet
interface to
Image Workstation
Protocol GbE
Interface to
Imaging
device
PowerPC takes data from Imaging
device and transfers to remote
Workstation using TCP
Workstation stores image data and
performs post processing
TCP/IP
Internet
RS232
Network
• Memory Bandwidth
– Lots of memory bandwidth is required to support wire-speed
TCP/Ethernet plus processor instruction/data fetches with
reasonable latency
• CPU Performance
– PowerPC in Xilinx FPGA ~300MHz
– General Rule of thumb – 1 MHz of CPU per 1 Mbits of TCP
– PPC can’t touch payload data bytes
• PPC can not produce or consume TCP payload
• So… compression or any other byte touching operation is out
– Buffer Management
– Protocol Processing
• Per-Connection Overhead
16 Getting the most TCP/IP from your Embedded Processor
Per-Byte vs. Per-Packet Overheads
http://www.cs.duke.edu/ari/publications/tcpgig.pdf
17 Getting the most TCP/IP from your Embedded Processor
Per-Byte Overhead
• “Sockets” API uses buffer copying to queue user application
data (user-to-kernel space)
300
158
200
100
0
1500 Byte Packet 9000 Byte Packet (Jumbo Frames)
5000
Sendfile
Non-sendfile
4500
Poly. (Sendfile)
Log. (Non-sendfile)
4000
3500
Throughput ( Mbits/sec)
3000
2500
2000
1500
1000
500
0
0 10000 20000 30000 40000 50000 60000
Frame size ( bytes)
13 WINDOW CHECKSUM
15 PADDING DATA
16 ... . . .
– 2uS at 100MHz
TCP Seq Number
- increment by bytes sent
• FPGA Implementation
TCP Checksum
- calculate TCP csum
– FSM controlled data path
TCP Flags
- OR -
– Microprocessor in fabric
- update based on rules
i += frame_size;
• IEEE Paper
– Deferred Segmentation for Wire-Speed Transmission of
false Large TCP Frames over Standard GbE networks
i == CPU_MTU
RX STATUS RX
FIFO FIFO Protocol
Control
Engine
Protocol
Control
Engine
HEADER TX
FIFO FIFO
RX_GMAC_IF
HEADER STRIP
TX_GMAC_IF
ISOC
APU
• Can be used standalone or with Control APU
M
EMAC Statistics
embedded PPC405
I/F
ISPLB EMAC
405 Block
• Seamless connection to MGT DSPLB Core Host
Interface
EMAC Statistics
• Jumbo Frame Support DSOCM
DCR
I/F
I/F
Test
• Processor can control the EMAC via Reset &
Control
DSOCM
Control
50 +15
max Logic saved
by EM ACs
40
%
+16
Logic available in
device
30
%
20 +25
10
0
FX12 FX20 FX40 FX60
# of EMACs/device 2 2 4 4
** Comparison based on 1G PLB EMAC implementation; Higher savings realized when TEMAC features like Tri-speed, RGMII, SGMII, address
match, multicast address table lookup are used