Problem3a Counter design

1.0. INTRODUCTION

The n bits binary counters are the counters which upon receiving a pulse counts up from
zero to 2n - 1 then resets to one and the process then repeats. Actually they are the modulo
2n counters with n as the number of bits and 2n states as well.

The counter will increase by 1 for each input pulse. When the output reaches 2n – 1 then
the next state of the circuit will go low. Thus next state becomes zero and the process
repeats itself.

2.0. DESIGN THEORY

The four bits binary counter is the counter which counts from 0 and adds one to obtain
the next state value up to 24 – 1 when a pulse is received before reset back to zero and the
process repeats. During designing thus sixteen different states are available as four bits
are involved in the counter. And the following are the design steps towards obtaining the
4 binary bits counter. Since there are 16 states and four bits are involved, then four JK
flip flop are going to be required.

2.1. The state transitional diagram

1 2 3 4
0 5
1

1
6

1
7
1
1 8
1 9

2.2. State table

The following below is the state table of the transition diagram shown above. The table
showing the present state (P.S) and the next state (N.S)
 P.S N.S
S3 S2 S1 S0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0
1 0 1 0 1 0 1 1
1 0 1 1 1 1 0 0
1 1 0 0 1 1 0 1
1 1 0 1 1 1 1 0
1 1 1 0 1 1 1 1
1 1 1 1 0 0 0 0

2.3. Truth table

From the above state table, then the truth table was the obtained using the JK flip
flop as shown in the table below. The variable mean don’t care condition

S3 S2 S1 S0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 1 0 d 0 d 0 d 1 d
0 0 0 1 0 0 1 0 0 d 0 d 1 d d 1
0 0 1 0 0 0 1 1 0 d 0 d d 0 1 d
0 0 1 1 0 1 0 0 0 d 1 d d 1 d 1
0 1 0 0 0 1 0 1 0 d d 0 0 d 1 d
0 1 0 1 0 1 1 0 0 d d 0 1 d d 1
0 1 1 0 0 1 1 1 0 d d 0 d 0 1 d
0 1 1 1 1 0 0 0 1 d d 1 d 1 d 1
1 0 0 0 1 0 0 1 d 0 0 d 0 d 1 d
1 0 0 1 1 0 1 0 d 0 0 d 1 d d 1
1 0 1 0 1 0 1 1 d 0 0 d d 0 1 d
1 0 1 1 1 1 0 0 d 0 1 d d 1 d 1
1 1 0 0 1 1 0 1 d 0 d 0 0 d 1 d
1 1 0 1 1 1 1 0 d 0 d 0 1 d d 1
1 1 1 0 1 1 1 1 d 0 d 0 d 0 1 d
1 1 1 1 0 0 0 0 d 1 d 1 d 1 d 1
2.4. Minimization and simplification

For J3 For K3
00 01 11 10 00 01 11 10
00 0 0 0 0 00 d d d d
01 0 1 0 0 01 d d d d
11 d d d d 11 0 0 1 0
10 d d d d 10 0 0 0 0

J3=S2S1S0 K3=S2S1S0

For J2 For K2
00 01 11 10 00 01 11 10
00 0 0 1 0
01 d d d d 00 d d d d
01 0 0 1 0
11 d d d d
11 0 0 1 0
10 0 0 1 0
10 d d d d
J2=S1S0 K2=S1S0

For J1 For K1
00 01 11 10 00 01 11 10
00 0 1 d d 00 d d 1 0
01 0 1 d d 01 d d 1 0
11 0 1 d d 11 d d 1 0
10 0 1 d d 10 d d 1 0

J1=S0 K1=S0
 For J0 For K0
00 01 11 10 00 01 11 10
00 1 d d 1 00 d 1 1 d
01 1 d d 1 01 d 1 1 d
11 1 d d 1 11 d 1 1 d
10 1 d d 1 10 d 1 1 d
J0=1 K0=1

3.0. CIRCUIT AND WAVEFORMS

3.1. The circuit diagram

The following circuit diagram has been obtained from the above equations obtained after
minimization using the K-map.

output

Q3 Q2 Q1 Q0
4321

CLK S S S S
J Q J Q J Q J Q
CP Q3 _ CPQ2 _ CP Q1 _ CP Q0 _
K Q K Q K Q K Q
R R R R
CLK
CP1 Q1
CP2 Q2 key
5V

3.2. Simulation and waveforms

The circuit maker has been used to simulate the circuit shown above and the following
are the waveforms obtained.
 60 70 80 90 100 110
CLK

Q0
Q1

Q2

Q3

4.0. CONCLUSION AND RECOMMENDATION

From the waveform it can be noted that there is a delay for each output with respect to the
clock pulse. This delay is a result of internal gates delay and delays due to the JK flip flop
used.

Apart from that, the change of Q3 is much slow i.e. change slowly as compare with the
output Q0 which changes once after every two clock pulse (which is twice as much the
speed of output Q2 as can be seen from the wave forms ) despite a slight delay during
raising edge of the clock.