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SULIT ^mmm^m FKE/APR 2000/KEE322

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UNIVERSITI TEKNOLOGI WlARA
FAKULTI KEJURUTERAAN ELEKTRIK
PEPERIKSAAN SEMESTER DISEMBER 1999 - MEi 2000

DIPLOMA KEJURUTERAAN ELEKTRIK (ELEKTRONIK)

MAT A PELAJARAN : DIGITAL ELECTRONICS

KOD MAT A PELAJARAN : KEE322

TARIKH ; 15 APRIL 2000

MASA : 3 JAM (2-15 - 5,15 PETANG)

ARAHAN KEPADA CALON:

1 Jawab LIMA (5) soalan daripada enam soalan yang diberi. Sekiranya anda
menjawab lebih, hanya jawapan dari lima soalan terbaik akan dipilih.

2 Setiap soalan membawa 20 markah.

3. Sila rujuk lampiran sekiranya anda memerlukan data untuk menjawab soalan,

4 Calon-calon tidak dibenarkan membawa barang-barang masuk ke bilik peperiksaan


kecuali dengan kebenaran pengawas.

KEPERLUAN PEPERIKSAAN:

1. Lampiran 1 dan 2 - disertakan.

JANGAN BUKA KERTAS SOALAN SEBELUM ANDA DIARAH BERBUAT DEMIKIAN

Kertas soalan ini rnengandungi 9 halaman yang bercetak


SULIT
SULIT FKE/APR 2000/KEE322

QUESTION 1

VCC = 5V

Output

Figure Question 1a

a.) The circuit in Figure Question 1 a shows a basic structure of a TTL NAND gate. Analyze
the circuit operation when input A is LOW and input B is HIGH, In your answer, specify
the purpose of the diodes Dinpl,M , DinpUE and D^.

(8 marks)

b.) Describe each of the TTL series mentioned below. Indicate which has the best speed
and speed-power product:
74 series, 743 series, 74LS series, 74AS series, 74ALS series, 74F series.

(6 marks)

c.) Name the fastest logic family using bipolar gate structure. For this logic family,
i.) State the logic levels and the power supply required.
ii.) In what environment and why would the application of this logic family be unsuitable?
iii.) Give a reason why emitter followers are required at each output of its gate,

(6 marks)

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SULIT 3 FKE/APR 20QQMEE322

QUESTION 2

a.) Shamsudin designs a logic circuit using TTL Logic Family with Totem-Pole output
structure. He observes on the oscilloscope that there are current spikes and slight
variation on the Vcc line. He suspects that the current in the totem-pole structure is the
cause of the problem.

Support his suspicion with explanation on how the totem-pole output structure can cause
variation in the Vcc line.

To overcome the problem, he should do "power supply decoupling11. What sort of


capacitors should he use and how should it be connected?

(10 marks)

b.) In Sabariah's final year project design, she needs to use only 3 of the 4 input CMOS
NOR gate. Her supervisor says that she should not leave it "floating".

Give a reason why CMOS floating inputs should not be left unconnected.

Suggest two ways for her to handle the unused inputs. Verify that your suggestion does
not interfere with the 3 input NOR gate operation with truth tables.

(6 marks)

c.) As a digital circuit designer, give 2 reasons why you would opt for TTL Logic Family
instead of CMOS Logic Family in your design. Likewise, give 2 reasons why you would
opt for CMOS Logic Family instead of TTL.

(4 marks)

SULIT
SULIT FKE/APR 2000/KEE322

QUESTION 3

V DD

GM-
^
input A o-

output

inputs o—1»

Figure Question 3a

a.) The diagram in Figure Question 3a shows a basic CMOS NAND gate structure,

i.) Describe the circuit operation when the input A is HIGH and input B is LOW.

ii.) Give a reason why the CMOS NAND gate is generally faster than the CMOS NOR
gate,

(6 marks)

SULIT
SULIT FKE/APR 20QO/KEE322

QUESTION 3 (continued)

V DD

V input

OUtplll

Figure Question 3b

b.) Figure Question 3b shows a resistive model of a CMOS Inverter with a resistive model of
a load,

i.) Find the Thevenin Equivalent Circuit of the resistive load.

ii.) Calculate output voltage for both high and low. You are required to assume values for
RP and RN.

iii.) If the load were a CMOS load instead of resistive load, what values of output voltage
would you expect for HIGH and LOW?

iv.) If the input V,N to the CMOS inverter above is a non-ideal input, comment on the
values of RP(on), RN(on) and the effect on the output voltage you had calculated in part
ii.) above.

(14 marks)

SULIT
SULIT FKE/APR 2000/KEE322

QUESTION 4

Figure Question 4a

a.) The input to a CMOS inverter is slowly changing as shown in Vin vs, t in Figure Question
4a,

Name the input structure that the inverter should use in order to avoid rapidly changing
output.

i.) Comment on the difference of the input-output transfer characteristic of a typical


CMOS Inverter with a CMOS Inverter using the input structure you have mentioned
above. Illustrate your answer with Vout vs. Vjn graphs.

Given that the CMOS Inverter with the input structure you mentioned above switch states
to low at 2.1 V and high at 2.9 V.

ii,) On separate graphs, sketch the corresponding Vout vs. t graphs of both the typical
CMOS inverter and the CMOS Inverter using the input structure you have mentioned
above.

(10 marks)

SULIT
SULIT FKE/APR 2000/KEE322

QUESTION 4 (continued)

Figure Question 4b

b.) Figure Question 4b shows an inverter with an open-drain output structure driving an
LED.

i.) What should the input be in order to have the LED on?

Given that the LED needs 10 mA to light with an on voltage of 1,6 V,

ii.) From which CMOS series should the inverter be chosen?

iii.) Calculate the value of the pull up resistance required.

(10 marks)

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SULIT 8 FKE/APR 2000/KEE322

QUESTION 5

a.) Define the following terms found in Digital 1C terminology:


i.) Propagation Delay,
ii.) Average Power Dissipation,
iii.) Speed-Power Product, Does a low speed-power product reflect a good transistor?
{5 marks)

b.) Referring to the 74ALSOO data sheet in the appendix, calculate:


L) Average Propagation Delay.
iL) Average Power Dissipation,
iii.) Speed-Power Product of the 74ALSOO operating at 5 V,
(5 marks)

c.) i.) Investigate if there is a loading problem when a 74ALSOO drives 3 74S04 and 1 7402
input.

5V

A
B
74ALSOO
74ACOQ

Figure Question 5c

ii.) The diagram in Figure Question 5c shows a 74LS output driving a 74HC input. By
collecting data from the data sheets in the appendix, prove that there is a problem in the
voltage requirement of the circuit. What should be done to solve this problem?

(5 marks)

d.) How is it possible for a TTL gate supplied at 5 V to drive a CMOS gate supplied at iu V?

(5 marks)

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SULIT 9 FKE/APR 2000/KEE322

QUESTION 6

a.) Describe an illustrate with circuit diagram a crystal-controlled clock generator using TTL
inverters or CMOS inverters. In your description, mention why a designer might opt for
crystal-controlled clock generator instead of 555 timer used as an astable multivibrator.

(10 marks)

b.) Describe and illustrate how reflections on a TTL signal line changing from HIGH to LOW
can cause an undershoot.

How do the clamping diodes in the TTL input structure reduce the reflection back to the
sending end?

(10 marks)

KERTAS SOALAN TAMAT

SULIT
SULIT LAMPIRAN 1 FKE/APR 2000/KEE322

SN54ALSDDA, SM74ALSQQA
QUADRUPLE 2-tNPUT POSITIVE NAND GATES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voKsafi, VCG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . / v
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating freu 3ir leiviperature range: SN54ALSOOA . . . . . . . . . . . . . . . . . . . . . . 55"C to 125"C
EN74ALSQQA . . . . . . . . . . . . . . . . . . . . . . . . . 0°C t o 70"C
Storage tomperature ranrjt; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... — 65 DC In 1 50 "C

recommended Operating conditions


1
SN54AL5QO* 5N74ALSOOA
UNIT
MM NOM MAX MIN NPM MAX
V
CC Supply vnliagn 4.Ei 6 5.5 1.S Ti U.b V
VIH High-lfi^Hl Infiin i'1-jltagn 2 2 V
O.B
V|[_ Low-level input vOllfHju 0.8 1 V
0.7t
IOH High-lflunI output current -0.-) (J.fl mA
IQL Low-lwvSl CuHnUT currcm 4 e mA

"if. OpBfjt 1 ;:^ I.-tra-yir HP- -.:.r,i;ure -BE 1^5 [) 70 •c


h n
9! Li!i C TO 7Q C.
TfF l^ti^C, pcrMIL-STD-333. (iieihnd fiOO'j, sun-nroup 1 . 2 . turf 3. Siniir. TCST is performed at 25 ut:. 1 ^ 5 * C , anil - S 5 C C .

electrical charactBristlcs over recommBnded operating free-air tBmperature range (unless otherwise
noted]
SN54ALSQOA 3N74ALSuttA
PAnAMFTER TEST CONDITIONS UNIT
MIN TYP* MAX MJN TVP^ MAX
V'IK V ( - c - ~^.i, V, (( - - IB mA .. 1.!: - 1.5 V
V
VOH v
Ct ~ 4';' v ID 5
-- v
' 'OH ~ -0 4 niA VCC - 2
V
CC ~ •* 5 V. IQL - A nlft 0.25 CH 0.25 0.4
VQ, 0.3!> 0.5
Vcc - 4 - 5 V. Ifji -fl mA
0.1 0 1 mA
, ii Vr-;- - !:.!, V, V| - 7 V

hi 1 VGC - sr, v. v, ^. 2.7 v 2c; 20 llA


VCG ~ 5.5 V. V; - 0.<l V -0 i -0.1 mA
\ • :») -\\2 ... 30 - 112 mA
..... 'of VCC - 5.B V. V c j - 2.26 V
|_ ,'CCH .,. .... V f f - 5.!i V ' . V ( i- O V (J.!: O.B5 o.!. o.sr, mA

r 'CCL V C ... . (j .e ^ . V| - ^..p V 1.5 i 1 5 3 mA

' TtieOulpiii 00"diti'>'it 1'iSwe btjeii rhnsrn in oronuct a UUT&U ihd! Closftlv .ifinroitimBteB utte dal' Ol ih* ifnB snnn-arcuit uulpuluuir<?n:

switching characteristics (see Note 1)


V C C '* 5 V. V C c = 4-5 v tt> S.R v,
CL - 50 pF. CL - 50 iif.
TO R t - 500 P.. RL - soo n. UNIT
(INPUT) (OUTPUT! TA = ?s "L; T A * MIN 10 MAX
'ALSOQA BN54AL3C1UA SN74ALSUOA

.1. - •>•
TYP
7 •
MIN
:',
MAX
1 F.
MIPJ
:-t
MAX
11 nt
Y 5 ? S ? a •it-

Figure A..2 (Continued) (Reproduced by permission of


InstnimenLs. Copyright C? Texas Instruments.)

SULIT
SULIT LAMPIRAN2 FKE/APR 2000/KEE322

54ACT11000, 74ACT11QOQ
QUADRUPLE 2 INPUT POSITIVE-KAND GATES

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) t
Supply voltage range, VQC . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6 V
Input uoliage renge, V| (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCG ''0.5 V
Output voltage range, VQ (see MOTS 1} . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to VCC + O.B v
Input clamp currem. l(^ (V| < 0 ur V| > V££) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK ' V Q < ° or VU > V CC' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 0 mA
Continuous output current, IQ (VQ - 0 to Vccl . . . . . . . - • • •• ••. . . . . . . . ±50 mA
Continuous ouireni through \/cc f" GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65"C t o IDO^C
' Hirrsscs bevond thus* tijiet) ufi<3iii "Jljsolule ITIHKI'TIIJIVI ranngs" mnv cause pnrmnnr-m damage tn the device. These are stress ratinni
only snfl lunctional operation ul lli« Uevice at these or any OThft. r.nn(<iiion£ fiflyQrxi Thrive indicated under "racommc-ndc-a operating
vdrtfllnonB" is not implied. Cxpusure ID ansoluTe-moximunvisieO ccirtdl'mnij-lui BxiefitferJ per/oOs may atrtiri iJe^iCS rcliabilirv.
NOTFJ ^: The input aild ciDrpiii uoliaqr: rnTiiuji umv- h* fi-xcecOcd if the incur rmd OUTPUT current rutinys are absRrved.

recommended operating conditions


54ACT110DO >4ACT11000
UNIT
MIM hi AX Mini MAX
V V
C1C; Jiupplv unltagc •1.5 5 5 1.5 5S
VIH Hif|r>-lPwfll input vohagc 2 2 V
V|[_ Luw-lhu/fl FfipSi vnlisge 0.0 0.6 V
V| Inpu! vultaun c v cc O VQC V
VQ Output voltaut fl vt:f: 0 V CC V
Hl
Inu 9h lcwc ' cutout current 21 -2."
mA

IQL L.O^-lflUftl ni'ipiiT r.nrrnm 1i 2^1 .iiM


•;_.>' liiuui [reiisi^fii'i MHH 01 M1 iSl<: 0 10 0 10 na'V
TA OorrotmH frwe-ar temperature 50 1 ^ •> 4O H F: ••r:
electrical characteristics over recommended operating free-air temperature range {unless otherwise
noted)
T A - 2&°C 54ACT1100D V4ACT11000
Ttal CONDITIONS vcc UNIT
MIN TVP MAX MIN MAX Mlftl MAX
4.5 V •4.1 4.4 4.4
IDH - • so ,,A LJ.!F V fi.a 5 4 5 4
VOM 4. Li V ^.64 3.7 3.8
I 0h j = - 2 4 "i*
ri.ri v 4 !K 4.7 4.0

ION - - 50 mA 1 5.5 V a. a*,


l r)K " '''.' r v > A ' £>.b v 3 yt
i.fi V 0 1 O.i O.I
IOL - ^ ,.A F> 5 V 0 1 0.1 0.1
V0!
1 5 V [).:«; 0.!. Q.44

i5 V 0 ?e 0.5 0.44

i^L - 50 mA* :i L V 1.65


IQL • 76 mA ^ f> !i V 1. 65
i V; •• VCC °r GND 5 ? V -ti i r 1 ^1 nA
4 40 ,iA
'cc V| - VCL" Qr GwLl. ]
0 • Cl 55V HO
On* iririni AI :-i 1 '-
: 5.5 V 0 3 1 1 ITlA
-ilCC
OUi*r inputs Hi GND I.T V ( ; L:

c. u
i - Vcc ur GWD
. ... f :.\ H !. p"

fju1. inyrt ititjri u»(f riLiipiJi dfbOiil'l ftrt ai a Lime, and the durslm" uf the tesl slmiiln nni
• "Inii is thp increase ir biitipiy (.'jrr tsf^l" inpui in.ii is a: onr ot the sncciticcl T TL ^uilouf li rather tha" 0 V

switching characteristics. - 5 V ±0.5 V (see Figure 1)


FRfJW TO it, - ac^c 6d ACT 11 OOP 7dACT11000
1 PARAMETER
(INPUTI (HUTPUT] MIN TYP MAX MtM MAX MIN MAX
if-LH 1 h 7 -j 10 ^ i i- i3.:j I.E. 12.2
i 'PHL 1.5 5P S i 5 a.Fi 1.5. H f!

operating characteristics, Vcc - 5 V, TA - 25 °C


PARAMETER TEST CONDITIONS TVP | UNIT
-nti knwc' 0 ssiDation capsf.nanc (iff! gate C.:L - 5O pf. ( " 1 MH: 23 ] BF#

Figure A.2 (Continued) (Repmd^ted by permission of Texas


Instrumentsi. Copyrighl © Texas Instruments.)

SULIT