Organic Electronics 7 (2006) 528–536

www.elsevier.com/locate/orgel

Field-induced mobility degradation in pentacene

thin-film transistors
Mohammad Mottaghi, Gilles Horowitz *

ITODYS, CNRS-UMR 7086, University Denis-Diderot, 1 rue Guy de la Brosse, 75005 Paris, France

Received 15 June 2006; received in revised form 21 July 2006; accepted 26 July 2006
Available online 22 August 2006

Abstract

Pentacene-based organic thin-field transistors (OTFTs) with bottom-gate, top-contact architecture were fabricated on
alumina substrates. The devices were divided into two sets, depending on whether pentacene was deposited on bare alu-
mina or on alumina modified with a fatty acid self-assembled monolayer (SAM). Previous analysis have shown that the
modification of alumina with SAMs result in a substantial decrease of the size of the grains in hte polycrystalline films.
Careful parameters extraction, including an original determination of the threshold voltage, and contact resistance extrac-
tion through the transfer line method (TLM), allowed us to estimate the gate-voltage dependent mobility in both series.
The mobility is found to first increase at low bias, and then decrease at higher gate voltage (mobility degradation). The
latter behavior is explained through an estimation of the distribution of charges across the accumulation layer, in which
the pentacene film is modeled as a stack of dielectric layers, the distribution being calculated using basic equations of elec-
trostatics and thermodynamics. A good agreement was found when the mobility in the layer next to the insulator was
assumed to be negligible as compared to that in the bulk of the film. The initial rise of the mobility is interpreted in terms
of multiple trap and release (MTR) with a distribution of traps located in the grain boundaries. Interestingly, the mobility
corrected for both contact resistance and mobility degradation is found around 3 cm2/V s for pentacene deposited on bare
alumina, and 5 cm2/V s when pentacene is deposited on SAM modified alumina. We conclude that the smaller grains
grown on modified alumina are more regular, and hence less defective, than the larger grains deposited on bare alumina.
 2006 Elsevier B.V. All rights reserved.

PACS: 72.20.Jv; 73.40.c; 73.61.Ph; 85.30.Tv; 68.55.Ln

Keywords: Organic field-effect transistors; Self-assembled monolayers; Mobility extraction; Transfer line method; Multiple trapping and
release

1. Introduction (OTFTs) [1–4]. Most usually, mobility is found to

Gate-voltage dependent mobility is now a well-
recognized feature in organic thin-film transistors
*
Corresponding author.
E-mail address: horowitz@paris7.jussieu.fr (G. Horowitz).
increase with gate voltage. Two useful models for
accounting for this are the multiple trapping and
release (MTR) and variable range hopping (VRH).
The basic assumption of MTR [3,4] is a distribution
of states localized in the energy gap close to the
transport band edge. These states are liable to trap

1566-1199/$ - see front matter  2006 Elsevier B.V. All rights reserved.
doi:10.1016/j.orgel.2006.07.011
 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536
the charge carriers injected into the channel of the
transistor, thus reducing the current. When increas-
ing the gate voltage, the Fermi level moves towards
band edge as more of the empty traps are filled by
injected charge. Accordingly, the ratio of free to
trapped carriers increases, and so does the channel
conductivity, which is interpreted in term of an
increase of the effective mobility. The VRH model
[2] also assumes a distribution of localized levels;
it proposes that transport occurs via hopping in that
distribution. Like with the MTR model, the gate-
voltage dependent mobility is explained through
the filling of the lower energy states, so additional
carriers occupy higher energy states, which demand
lower activation energy to hop to the next site.
More recently, a reverse behavior has been
reported, where the mobility decreases with gate
voltage [5–7]. It is worth pointing out that a similar
trend has been identified for long in conventional
silicon-based metal-oxide-semiconductor field-effect
transistors (MOSFETs) [8], where it is attributed
to various scattering agents in the vicinity of the
insulator interface, namely charged centers, surface
phonons and surface roughness. A usual way to
describe this behavior is to introduce the so-called
‘‘mobility degradation factor’’ h, which in its sim-
plest formulation leads to a mobility that looks like
l0
l¼ ; ð1Þ
1 þ hðV G  V T Þ
where VG is the gate voltage and VT the threshold
voltage.
We have previously shown [5] that the structure
of pentacene films vapor deposited on alumina
(Al2O3) is drastically changed by modifying the sur-
face of the oxide with a self-assembled monolayer
(SAM). On bare alumina, we observed a two-
dimensional growth of the first monolayer followed
by a three-dimensional process with larger grains,
while films on SAM-modified alumina were made
of grains of smaller dimension. In this paper, we
report on new gate-voltage dependent measure-
ments that bring evidence for field-induced mobility
degradation on pentacene deposited on both sub-
strates. A model for charge distribution in the chan-
nel, based on the layered structure of the pentacene
film, is developed to account for this feature. It is
found that the mobility in the molecular layer close
to the insulator–semiconductor interface is substan-
tially lower than that in the bulk of the pentacene
film. For the latter, the mobility is interpreted in
terms of the MTR model. The respective trap-free
529
mobility and trap distribution in bare and SAM-
modified devices are discussed under the perspective
of the corresponding structure of the films.
2. Experimental
The OTFTs where fabricated on highly doped
p-type silicon wafers that acted as the gate electrode
of the device. The insulator (Al2O3) was grown in a
homemade vacuum chamber by bombarding an alu-
minum target with oxygen ions under reduced pres-
sure (1 Pa). The growth rate in this unusual
deposition technique is very low, thus resulting in
highly dense and smooth films, with a root-mean
square (RMS) roughness, as measure by atomic force
microscopy (AFM) profiling, comparable to that of
the underneath silicon substrate (0.2 nm). The thick-
ness of the Al2O3 layer was 100 nm and its capaci-
tance 75 nF/cm2. Before pentacene deposition or
modification, the alumina substrates were cleaned
in pure sulfuric acid, rinsed in deionized water and
blown dry in a flux of argon. Self-assembled mono-
layers of eicosanoic acid CH3(CH2)18COOH were
deposited by dipping the substrate during 45 min.
into a solution in benzene. Silanes (e.g., octadecyltri-
chlorosilane OTS) are commonly used on silicon oxi-
des. However, a fatty acid (in our case, eicosanoic
acid) was preferred to silanes because it more readily
assembles on alumina. We note that, because the
length of the alkyl chain is comparable in OTS and
eicosanoic acid (18 and 19 carbon atoms, respec-
tively), the robustness of the corresponding SAMs
is equivalent, as was checked by contact angle mea-
surement and surface IR spectroscopy [5]. 30 nm of
pentacene (Aldrich, used as received) was vapor
deposited at a base pressure of 105 Pa at a rate of
0.01 nm/s on substrates kept at room temperature.
Source and drain electrodes were made of 20 nm
thick gold evaporated through a shadow mask with
channel lengths ranging between 5 and 40 lm. The
current–voltage characteristics were recorded under
ambient condition with a Karl Suss manual probe
station and a Keithley 4200 semiconductor charac-
terization system.
3. Multi-layer model
The multi-layer model takes advantage of the
layer structure of vapor deposited molecular films
with rigid molecules like pentacene or the oligothi-
ophenes. A first version of the model has been pub-
lished recently [9]. However, we discovered that this
530 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536
first version contained an inappropriate formulation
of Gauss’s law (see Eq. (A.2)), which is corrected
here. Note that this initial mistake only resulted in
quantitative changes, while the general conclusions
of the model were preserved.
Pentacene molecules can be viewed as rigid rods,
which in the solid state assemble parallel to each
other, thus forming parallel layers, the thickness of
which equals the length of the molecule (minus a
small correction to account for a tilt angle). Because
Fig. 1. Distribution of charge carriers in a 30 nm (20 ML) thick
pentacene film with an insulator capacitance of 75 nF/cm2. From
top down: VG = 1 V, 5 V and 25 V.
(1) each molecule cannot bear more than one ele-
mental charge carrier and (2) the charge practically
extends all over the molecule [10], we assimilate the
pentacene film to a stack of n dielectric layers of
thickness d, each layer carrying a uniform density
of carriers ni. The layers are numbered starting from
the insulator side. The calculation of the charge dis-
tribution is detailed in the Appendix. It does not
lead to an analytical expression, but rather to Eq.
(A.10) that relates the charge in layer i to that in lay-
ers (i + 1) to n.
Two additional equations were used to perform
the numerical calculation. The first one derives from
a product of Eq. (A.9) and gives the potential at the
insulator–semiconductor interface
kT n1
V0 ¼ ln ; ð2Þ
q nn
while the second one gives the total charge in the
film.
X
n
qntot ¼ q ni ¼ C i ðV G  V 0 Þ: ð3Þ
1
Here, we have assumed VT = 0. In pentacene, the
thickness of a monolayer, as determined by X-ray
diffraction, is 1.54 nm [11], so a 30 nm thick layer
roughly contains 20 monolayers. Fig. 1 shows the
distribution of charge carriers at three different gate
voltages: 1, 5 and 25 V. It clearly appears that as VG
increases, the charge concentrates in the first layer.
At this stage, it is worth pointing out that our
calculation only refers to the distribution of the
total (free and trapped) charge in the semiconduc-
tor. No assumption was made on how these charge
moves; in particular, we stress that the presence in
the insulator of charges (fixed and mobile) and
dipoles only acts on the mobility and threshold volt-
age, not on the charge distribution.
4. Results
4.1. Structure of the evaporated films
The effect of the eicosanoic acid SAM on the
structure of the pentacene layer has been extensively
studied in our previous works [5]. It appeared that
on bare Al2O3, the growth starts two dimensional
and then turns to three-dimensional with larger,
though loosely connected grains, while on SAM
modified substrates, the growth is three-dimensional
all along, with much smaller grains. The situation is
schematically depicted in Fig. 2. Note that the
 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536 531

Fig. 2. These cartoons are schematic view of the structure of

vapor deposited pentacene on (a) bare and (b) eicosanoic acid
SAM modified Al2O3. In (a), a two-dimensional layer of medium-
sized (200 nm) grains is topped by larger three-dimensional
islands (average diameter 1 lm). In (b) the size of the grains is
reduced to 50 to 100 nm, while the growth process is three-
dimensional all along.

actual number of layers in our films is significantly

higher than what drawn in the figure, so that the dis-
ruption between grains only occurs far from the
insulator–semiconductor interface.

4.2. Parameters extraction

Extracting the mobility and threshold voltage of

an OTFT from its current–voltage characteristics is
a crucial step for any modeling of the device opera-
tion. The most widespread technique uses the satu-
ration current, which is predicted by simple models
to be proportional to (VG  VT)2, so that plotting
the square root of the current as a function of the
gate voltage would give a straight line from which
both parameters can be estimated. However, this
method presents two major drawback: It cannot
be corrected for contact resistance, and it is blind
to gate-voltage dependence.
Another common method uses the first deriva-
tive of the linear-regime current Eq. (4) as a func-
tion of gate voltage (the so-called linear-regime
transconductance.)
W
ID ¼ lC i ðV G  V T ÞV D : ð4Þ
L
However, for a gate-voltage dependent mobility the
Fig. 3. These curves are representative of the linear-regime in our
exact expression of the linear-regime transconduc- devices. Top panel: drain current vs. gate voltage at a drain
tance is voltage of 0.2 V. Middle panel: first derivative (linear trans-
  conductance); this curve is often claimed to be proportional to
oI D W ol
¼ C i V D l þ ðV G  V T Þ ; ð5Þ the mobility. The lower panel illustrates the method used to
oV G L oV G estimate the threshold voltage. It shows the second derivative of
the drain current. The threshold voltage corresponds to the first
so that the method is only valid when the second peak (VT = 1.0 V).
term in brackets can be neglected, that is, for a
slowly varying mobility (which seems to be only
the case with single crystals [12].) Be this condition can be seen that the linear transconductance pre-
not fulfilled, the resulting mobility would be overes- sents strong variations, and eventually becomes neg-
timated when mobility increases with gate voltage, ative at high gate bias.
and underestimated when it decreases. The problem Our method includes a separate extraction of the
is illustrated in the middle panel in Fig. 3, where it threshold voltage from the linear regime, which then
532 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536
allows for estimating the mobility without any der-
ivation step. The sequential steps of the method are
detailed as follows.
4.2.1. Threshold voltage
The threshold voltage is defined as the point
above which significant drain current flows. In con-
ventional MOSFETs, it is understood as the transi-
tion point between weak and strong inversion. In
the OTFT, which operates in the accumulation
regime, the change is between depletion and accu-
mulation. As the threshold voltage is of fundamen-
tal importance for circuit modeling, numerous
methods have been developed to extract its value
in conventional MOSFETs [13]. Interestingly,
extraction is mostly done at low drain voltages,
where the device operates in the linear regime. The
technique we have selected for this work determines
VT from a double derivation of the drain current at
low drain voltage with respect to the gate voltage
[14]. This method was preferred because it was
claimed to be insensitive to both mobility degrada-
tion and contact resistance. A representative exam-
ple is given in Fig. 3 for a SAM modified device.
With this method, VT could be extracted for each
device. Of the 12 devices without SAM and 13
devices with SAM used in this work, we obtained
a threshold voltage of (1.2 ± 0.4) V in the former
series and (1.2 ± 0.1) V in the latter one. We note
that VT is shifted by around 2.4 V by the presence
of the SAM, and that the dispersion of the data is
less pronounced in SAM modified devices, which
can be explained by stating that, owing to its
reduced surface energy, SAM-modified alumina is
less liable to contamination than bare alumina.
Once VT is known, the gate-voltage dependent
mobility is directly calculated from Eq. (4), which
does not requires any derivation. The result is
shown in Fig. 4. for the same sample as in Fig. 3.
4.2.2. Contact resistance
Contact resistance Rs is becoming a major issue
as the performance of OTFTs improves. There are
two main methods for extracting Rs: Four-point
measurements [6,15,7] and the transfer line method
(TLM) [16–19]. Although the latter is less reliable
because it requires measurements on different
devices, the contact resistance of which may vary
from sample to sample, we used this second method
because it is less technologically demanding. We
used four channel lengths L (5, 10, 25, and
40 lm), and two to four devices for each channel
Fig. 4. Gate voltage dependent mobility of the same device as in
Fig. 3. The mobility is calculated form Eq. (4) where VT is
estimated with the second derivative method illustrated in the
bottom panel of Fig. 3.
length. The width normalized resistance in the linear
regime is given by
L
RW ¼ Rs W þ : ð6Þ
lC i ðV G  V T Þ
Because the threshold voltage was independently
known for each device, Eq. (6) could give both the
contact resistance and gate-voltage dependent
mobility. In practice, we measured the transfer char-
acteristic of each sample at low drain voltage
(VD = 0.2 V) and then used a linear regression
method to estimate the gate-voltage dependent Rs
and l. Data are shown in Fig. 5; we recall that they
result of 12 different devices for the bare alumina
series and 13 devices for the SAM-modified series.
Note that the contact resistance is very similar for
both series, which is consistent with the fact that
we used a top-contact geometry, so that the contacts
are little affected by the nature of the insulator–
semiconductor interface.
It is worth pointing out that, while the data of the
SAM-modified devices are in good agreement with
our earlier report [5], there is some discrepancy as
for the devices made on bare alumina. In our earlier
work, we reported a significantly lower mobility
that tended to increase all along with the gate volt-
age. The discrepancy was identified as coming from
a defective surface cleaning, as was checked by com-
paring devices prepared according to the old clean-
ing process to the new one. In the latter case, the
alumina substrates were introduced in the evapora-
tion chamber immediately after etching with pure
sulfuric acid; waiting for roughly one hour (as was
the case in the old process) resulted in a substantial
degradation of the characteristics.
 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536
Fig. 5. Gate-voltage dependent mobility (a) and contact resis-
tance (b) as deduced from the transfer line method on pentacene
films deposited on bare and SAM-modified alumina. The upper x
axis in (a) shows the surface density of injected charge.
4.3. Estimation of the bulk mobility
In all cases, the gate-voltage dependent mobility
shows a decrease at high gate voltage. To account
for this effect, we assume that the mobility is sub-
stantially lower in the region close to the insula-
tor–semiconductor interface than in the bulk of
the film. The above developed multi-layer model
was used to account for this degradation of the
mobility. The effective mobility of the semiconduc-
tor is derived by identifying the film to parallels lay-
ers of mobility li:
X n
ni
leff ¼ li : ð7Þ
ntot
1
If the mobility in the first layer can be neglected in
front of that in the bulk of the film, we have
 
n1
leff ’ lb 1  ; ð8Þ
ntot
where lb is the bulk mobility.
533
Fig. 6. Variation of the bulk mobility as a function of gate
voltage.
In practice, the steps of the calculation were as fol-
lows: (1) from Eqs. (A.10), (2) and (3), the density of
charges ni in each layer of a 20 layer-thick pentacene
film (permittivity: e = 3e0, room temperature, thick-
ness of a layer d = 1.5 nm, insulator capacitance
Ci = 75 nF/cm2) was numerically calculated as a
function of gate voltage; (2) The variation of
(1  n1/ntot) as a function of gate voltage was found
to be nicely fitted to an empirical function of the form
(1 + VG)C where C = 0.71; (3) The resulting gate-
voltage dependent bulk mobility is shown in Fig. 6.
These curves will be discussed in the next section.
5. Discussion
The most prominent finding of our modeling is
that the mobility in the layer next to the insulator
is significantly lower than that in the bulk of the
film. We note that this is in agreement with what
found by measuring the mobility as a function of
the thickness of the film; it was reported that the
mobility steadily increases with film thickness, with
bulk mobility only occurring above six layers [20].
The first point to discuss is: Why is mobility degra-
dation so rarely observed in organic transistors [6,5]?
The answer is in the amount of charge induced in the
channel. Most OTFTs use gate dielectrics with a typ-
ical capacitance of 10 nF/cm2, and gate voltages up
to a few tens of volts, which represents a maximum
density of charge carriers of a few 1012 cm2; this is
almost one order of magnitude lower than the magni-
tude used in this work (up to 1.3 · 1013 cm2, see
upper x-axis in Fig. 4). Devices with high gate dielec-
tric capacitance are usually designed to work at low
voltage, so that here too the density of charge in
the channel remains moderate [21–23]. The reason
534 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536
why mobility degradation is only observed in few
occasions is thus simply that the gate voltage is not
(or cannot be, because of, e.g., limitation due to
dielectric strength) pushed up to values where the
phenomenon occurs.
A second important question is the origin of low
mobility in the first layer. A likely explanation stems
from the nature of our gate dielectric, namely, alu-
mina. There is now strong evidence for that mobility
in OTFTs depends on the material used as gate
dielectric. In particular, mobility decreases when
the dielectric constant increases [24,12], so alumina
(dielectric constant 8–9) is not favorable in that
respect. What our result suggests is that the decrease
of the mobility is the more important as one gets
closer to the insulator–semiconductor interface; this
seems in good agreement with the model of Veres
and coworkers that invokes the role of dipole
moments in the insulator [24], the effect of which
decreases when getting farther from the insulator.
It is worth pointing out that the thickness of a
SAM does not appear sufficient to weaken mobility
degradation, in contrast to what reported with
ultra-thin polymer layers [25]. Accordingly, it can
be expected that mobility degradation will be of les-
ser extent in devices involving low dielectric con-
stant insulators.
As for the bulk mobility, Fig. 6, we note that it
first increases with gate voltage, and then levels off
at a magnitude that can be viewed as the grain (sin-
gle crystalline) mobility. According to the MTR
model, the initial increase corresponds to the filling
of the traps in the grain boundaries. The fact that it
takes longer to fill the traps in the SAM modified
devices is consistent with smaller grains (average
diameter ranging between 50 and 100 nm, as com-
pared to around 1 lm on bare alumina). That is,
grain boundaries occupy a larger part of the film.
On the other hand, the grain mobility is higher in
smaller grains (ca. 5 cm2/V s) than in larger ones
(ca. 3 cm2/V s), meaning that large grains are more
defective than small ones. Such a conclusion could
account for the now well-documented fact that the
mobility of pentacene decreases when grain size
increases [26,27], which is at variance with what usu-
ally found in polycrystalline semiconductors.
6. Conclusion
We have determined the gate-voltage dependent
mobility in pentacene films vapor deposited on bare
and SAM-modified alumina. Raw data were cor-
rected for contact resistance and mobility degrada-
tion. This was done with the help of an original
parameter extraction method, and the use of a
model to estimate the distribution of charge in the
conducting channel, in which the pentacene film is
depicted as a stack of dielectric layers. The thus
extracted bulk mobility was found to first increase,
then level off at a value that is interpreted as the
grain mobility. Following the MTR model, the ini-
tial increase is attributed to the filling of traps
located in grain boundaries. In films deposited on
SAMs, made of small grains, the density of traps
associated to grain boundaries is higher, while the
mobility within the grains is larger than in the large
grains found in films grown on bare alumina. In
other words, large grains present more defects than
small ones, which is in agreement with the well-doc-
umented fact that high mobility in pentacene is
associated with small grains.
Acknowledgements
We thank Dr. Hervé Aubin and Mr. Hatem Diaf
for the deposition of alumina, and Dr. Philippe Lang
for the elaboration of the self-assembled monolayers.
The multi-layer model was initiated with Prof. Libero
Zuppiroli and Prof. Marie-Noëlle Bussac, and devel-
oped during a stay at Bologne, Italy, under the invi-
tation of Dr. Fabio Biscarini. Financial support for
this stay by the Italian CNR is acknowledged.
Appendix A. The multi-layer model
The organic semiconductor film is modeled as a
stack of n dielectric layers of thickness d, where
the density of charge ni is assumed to be uniform.
This is valid in the low injection regime because
(1) no more than one charge per molecule is injected
and (2) the injected charge practically extends all
over the molecule [10]. Let Fi and Vi be the value
of the electric field and potential at the borderline
between the ith and (i + 1)th layers. Because ni is
constant, F varies linearly with distance:
x x
F ¼ ai þ bi ; i 6 6 i þ 1: ðA:1Þ
d d
Applying Gauss’s law to the ith layer gives
qn
F i1  F i ¼ i : ðA:2Þ
e
where q is the elemental charge and e the permittiv-
ity of the semiconductor. Summing up Eq. (A.2)
from i + 1 to n and setting Fn = 0 leads to
 M. Mottaghi, G. Horowitz / Organic Electronics 7 (2006) 528–536 535

qX n [5] W. Kalb, P. Lang, M. Mottaghi, H. Aubin, G. Horowitz, M.

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 dV ¼ d F d ; Phys. 119 (23) (2003) 12563–12568.
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