Hardware Description Language

-- Logic Design using Verilog

Tsung-Chu Huang

Dept. of Electronic Eng.

National Changhua University of Ed.
Email: tch@cc.ncue.edu.tw

2004/09/14

HDL T.-C. Huang / NCUE Fall 2004 1

 Brief Syllabus
¾ Visit http://163.23.223.30/tch for Details
¾ Not Programming Only But Also Logic Design
¾ Major Content:
1. External and Internal Data Structures of HDLs
2. Logic Design using Verilog
3. Introduction to Rapid Prototyping
4. Introduction to SOPC
5. Introduction to Cell-Base Design
6. Introduction to CPU Design using Verilog

HDL T.-C. Huang / NCUE Fall 2004 2

 Overview on HDL
¾ Introduction to General HDL including NETLIST
¾ Competition btw VHDL and Verilog
¾ HDL Tools
¾ Application of VLSI HDL
¾ Y-Chart: Level and Views
¾ Modeling
¾ Quick Tutorial using 1 or 2 Tools
1. Gate-Level
2. Behavioral Mode
¾ Preparation for Next Course

HDL T.-C. Huang / NCUE Fall 2004 3

 Usual Applications of HDLs
¾ Logic Simulation and Verification
¾ Synthesis for FPGA/SoPC Prototyping
¾ Synthesis for Cell-base VLSI Design
¾ Soft Intellectual Property (IP) Design
¾ Modeling Low or Equal Level Circuit

HDL T.-C. Huang / NCUE Fall 2004 4

 HDL in General Sense
Gate-Level Above Transistor-Level Schematic/Graph Text Language

module adder(A, B, C, S);

input [31:0] A, B;

SCHEMATICS
output [31:0] S;
output C; HDL
…
ends

VDD
VDD V 0 3V
M1 Z IN 0 0 NCH
M2 Z IN V V PCH
A IN Z NETLIST
R1 A IN 15
C1 Z 0 1P
VIN A 0 PWL(0 0 1N 3V)

HDL T.-C. Huang / NCUE Fall 2004 5

 HDL in Common Sense

System Level

SystemC Verilog
Industry VHDL
Academic
VHDL
RTL Verilog
Verilog

Gate Level
Transistor Level

HDL T.-C. Huang / NCUE Fall 2004 6

 Popular HDL/Debugger Packages
¾ VerilogXL, LeapForm, LDV, NCV /Cadence
¾ ModelSim /Mentor
¾ VSS /Synopsys
¾ Vantage /ViewLogic
¾ Silos /SimuCAD
¾ Verilogger Pro /SynaptiCAD
¾ ActiveHDL /Aldec IEEE Standard 1364, 1995
¾ VeriBest /VeriBest
¾ VeriWell /VeriWell
¾ Debussy /SpringSoft
¾ VCS /Chronologic
¾ FrontLine /FrontLine
¾ Silos /SimuCAD
¾ HDL Entry in FPGA Co., e.g., Max/Quartus(Altera), ISE(Xilinx)

HDL T.-C. Huang / NCUE Fall 2004 7

 Preparation for Next Courses
¾ Download at least one evaluation-edition Verilog
package introduced in last page.
¾ Some packages can be downloaded from my web.
¾ Install it and follow up my demo examples in the
following quick tutorials.
¾ Exercise Schematics by Yourself (E.g.,
OrCAD/Schematic may be the most popular and basic
tool)
¾ Verilogger (for small systems) & Quartus II (with
ModelSim PE 6.0 for larger systems) are suggested.
¾ Licensing for corresponding software form CIC.
¾ We will do practice at classroom 31214 next week.

HDL T.-C. Huang / NCUE Fall 2004 8

 Levels & Views
Functional-View Structural-View Physical-View
Behavioral-View
System-Level

Board-Level

Register-Level

Logic-Level

Circuit-Level

Transistor-Level

Physics-Level
HDL T.-C. Huang / NCUE Fall 2004 9
 Y-Chart
Gajski transferred the level-view table into a sphere chart:

if(c) then
Behaviorial p<=a*b; Structural
View
View

UDP
Symbol

Spec

HDL T.-C. Huang / NCUE Fall 2004

Physical View 10
 SoC EDA
modularization
Behavioral partitioning Structural

library
sim
ver synthesize

Physical
HDL T.-C. Huang / NCUE Fall 2004 11
 Usual Levels & Views
Behavioral-View Structural-View Physical-View

System-Level
“Behavioral Mode”

Register-Level “RTL Mode”

“Gate-Level”
Logic-Level

HDL T.-C. Huang / NCUE Fall 2004 12

 Internal & External Models

Program
||
Algorithm
+
Data Structure

HDL T.-C. Huang / NCUE Fall 2004 13

 Structural & Functional Models

if(c) then
Behaviorial p<=a*b; Structural
View
View

UDP
Symbol

Spec

HDL T.-C. Huang / NCUE Fall 2004

Physical View 14
 Structural Models
Recursive Definition

1. Symbol View: A system or circuit can be represented

by a symbol with its function.
2. A Structural View of a system (or circuit) is a
representation or model that consists nodes for
subsystems (or subcircuits) and elements (or
components) represented by some symbol view, and
arcs for their input/output relations.
3. Usually hierarchical.
4. The bottom-level boxes (components) are called
primitive elements, which functional model is assumed
to be known such as and, nand, or, nor, not, etc.

HDL T.-C. Huang / NCUE Fall 2004 15

 Structural Modeling at Logic Level

1. External Representation
2. Structural Properties
3. Hardware Descriptive Languages
4. Internal Representation
5. Example: A Simple Verilog Parser in
C Language.

HDL T.-C. Huang / NCUE Fall 2004 16

 External Representation

1. Text or schematic for human.

Connectivity specifies I/O, components with
signals.
2. Text or Language:
HDL: VHDL, Verilog, C, etc.
Netlist: SPICE, gat, tdl, etc.
3. Schematics:
Cadence Schedmatics
OrCAD Schedmatics, ..etc.

HDL T.-C. Huang / NCUE Fall 2004 17

 Structural Properties in Logic Level

1. Branches/Fanout
2. Stem
3. Fanout-free
4. Reconvergent Fanout
5. Gate Type
6. Inversion
7. Inversion Parity
8. Level of a Gate in Circuit

HDL T.-C. Huang / NCUE Fall 2004 18

 Structural Properties in Logic Level
Example

G1 G4

G3
G2 G5

G7

G6

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 Structural Properties in Logic Level
Example: s27 in ISCAS89 benchmark

17

11 10
16
0 14
8 9
15
1 12
2 13

3 7
6

HDL T.-C. Huang / NCUE Fall 2004 20

 Internal Representation
Example: My Simple Verilog Parser

Top
module
Instance Net
List
module module module

Pin List
Port List
Instance Pin List
module module
Port List

Instance Instance

HDL T.-C. Huang / NCUE Fall 2004 21

 Structure-Oriented Design Methodology

Top 1. Top-Down Design

2. Bottom-Up
A B 3. Middle-Out
4. Ends-In
5. Hybrid (Greedy)
C D E

HDL T.-C. Huang / NCUE Fall 2004 22

 Functional Modeling at Logic Level

1. Truth Table & Primitive Cubes.

2. State Table & Flow Table.
3. Binary Decision Diagrams.
4. Programs as Functional Models.

HDL T.-C. Huang / NCUE Fall 2004 23

 Truth Table & Primitive Cubes

A B C F A B C F
0 0 0 1 X 1 0 0
0 0 1 1 1 1 X 0
0 1 0 0 X 0 X 1
0 1 1 1 0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0 F = B + ABC
1 1 1 0

HDL T.-C. Huang / NCUE Fall 2004 24

 Huffman Model for a Finite State Machine
Single Clock, Synchronous, DFF-based

PI: PO:
Primary Inputs N Primary Outputs
X L
Combinational Z
Circuit
PPI: PPO:
Pseudo PI Pseudo PO

M Q Q
Q
D
D D M
Q D
Q D
PS: Present State y Y NS: Next State
Clk State Count S ≤ 2 M

HDL T.-C. Huang / NCUE Fall 2004 25

 State Diagram
Example: A Lock with Password 1101

0/0 Waiting for 1/0 Waiting for

1011 011 1/0

00 01
1/1 0/0 0/0

Waiting for 0/0 Waiting for

1 1/0 11

11 10
HDL T.-C. Huang / NCUE Fall 2004 26
 State Table & Flow Table
K-map or
Q X D Z McKlusky Method:
Q1 Q0 X0 D1 D0 Z0 D1 = Q1 X + Q1Q0 X + Q1 Q0 X
0 0 0 0 0 0 D0 = X
0 0 1 0 1 0 Z = Q1Q0 X
0 1 0 1 0 0 X
0 1 1 0 1 0 Z

1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 1 0 0
Q0D
1 1 1 0 1 1
Q1D
HDL T.-C. Huang / NCUE Fall 2004 27
 Binary Decision Diagrams
1. A Binary Decision Diagram (BDD) is a graph
model of the function of a circuit.
F = AC + BC F

A C
0 1 0 1

B B B A
1 0
0
C 1 C 1 Reduced Ordered BDD
0 1
0

0 1
HDL T.-C. Huang / NCUE Fall 2004 28
 Programs as Functional Models
1. Assembly-Like: 3. C-Code is the
LDA A direct and fast
AND B
INV
simulator.
OR C
C=A+B;
STA F A=R1*R2;
B=~B;
2. C-Like:
main(F, A, B, C)
{ int F, A, B, C;
F = ~ ( A && B ) || C;
}

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 Functional Modeling at Register Level

1. Basic RTL Constructs

2. Timing Modeling in RTLs
3. Internal RTL Models (See Internal
structural model)

HDL T.-C. Huang / NCUE Fall 2004 30

 Basic RTL Constructs
1. RTL (Register-Transfer Language in Register-Transfer Level)
PC←PC+1; A←A+B+C
PC←PC+1; if C=1 PC←#FA07
R3←A – R4; A←0

2. C or Verilog-like Language:
module Adder(Co, Sum, A, B, Ci);
Input [15:0] A, B;
Input Ci;
output Co;
output [15:0] Sum;
assign {Co, Sum} = A + B + Ci;
endmodule

HDL T.-C. Huang / NCUE Fall 2004 31

 Timing Modeling in RTLs

1. Verilog-like Code:
Sum = #20 A+B;
initial
begin
A=1; B=0;
#10 B=1; A=0;
#40 B=0;
#10 $stop;
end

HDL T.-C. Huang / NCUE Fall 2004 32

 Quick Tutorial on Verilog
1. Usual version:
1. VerilogXL/Cadence
2. Verilog/Altera
3. Verilog/Xilinx
4. Verilog/MyCAD
5. SynaptiCAD Verilogger
6. VeriWell
7. e.t.c.
2. Structural View Gate Level;
3. Behavorial View RTL Level;
4. Finite State Machine
5. Memory Module

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