Monolithic Architectures for Image

Processing and Compression

Konstantinos Konstantinides and Vasudev Bhaskaran
Hewlett-Packard Laboratories

To meet the demands of I n emerging applications such as desktop publishing, medical imaging,
and multimedia, hardware support for image processing is vital. In the
image-intensive past, custom, complex, and expensive image processing architectures satis-
applications like desktop fied computational needs for intensive image processing tasks like pattern
recognition and analysis of satellite data.'.* However, the increasing power
publishing, medical of computing ICs and the opportunity to attract new markets prompted
imaging, and multimedia, many developers to provide some image processing support. Present im-
researchers are refining age processing accelerators are based mostly on general-purpose micro-
processors or digital signal processors (DSPs), such as the i860 from Intel
programmable ICs for or the TMS320 family from Texas Instruments.
image processing . Emphasizing image-processor ICs, we survey many of the current IC
designs. No single article can cover all existing designs. Hence, we present
a selection of chips, application-specific circuits (ASICs), and pro-
grammable image processors that cover the current design trends in imag-
ing acceleration.

Challenges for imaging

New areas of applications, such as high-definition TV and video tele-
conferencing, demand processing power that existing general-purpose
DSPs cannot provide. Until recently, commercially available image pro-
cessing ICs performed only low-level imaging operations like convolution.
These ICs had limited programming capability, if any, because of the well-
defined operation and data representation of the low-level imaging func-
tions and the integration limits in VLSI circuits.
Emerging standards (like JPEG and MPEG for image and video com-
pression), advances in submicron integration technology, and the opening
of new market areas (like multimedia) encourage manufacturers to invest
in the design and development of new image processing ICs. Image com-
pression ICs, for example, are now becoming widely available. With these
design and development efforts, a new generation of general-purpose im-

November 1992 0272 17-16/92/1100-0075$0300 0 1992 IEEE 15

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Features JPEG MPEG-I MPEG-I1
Full-color still images Yes __
Full-motion video
____________
Yes Yes Yes
Real-time video capture Yes
and playback
Broadcast-quality Yes Yes
full-motion video
Image size 64K x 64K 360 x 240 640 x 480
(max) -~ - they usually consist of memory, a video
Compression ratios 10 to 80: 1 200:l 100:l
(max) (max)
Data rates (compressed) 1.5 Mbps 5-10 Mbps 64 Kbps - 2 Mbps
________~___~ ~ _ _ _ ~ _ _ _
age processors will emerge to extend the capabilities of gen- floating-point arithmetic and have a bus-based architecture.'
eral-purpose DSPs.
Image processing is one of computing's broadest fields. It
includes document image processing, machine vision, geo-
physical imaging, multimedia, graphic arts, and medical imag-
ing. In general, we can separate image processing operations
into low, intermediate, and high levels of complexity. In low-
level processing (filtering, scaling, and thresholding), after
some operations, a one-to-one mapping occurs between in-
put and output data, and output data is again in the form of a
pixel array. In intermediate-level processing (like edge detec-
tion), the system can no longer express the transformed input
data as just an image-sized pixel array. Finally, high-level
processing (like feature extraction and pattern recognition)
attempts to interpret this data to describe the image content.
Because of this large range of operations, it seems that de-
velopers have applied every conceivable type of computer ar-
chitecture at one time or another to image processing.* But
so far, no single architecture can efficiently address all possi-
ble problems. For example, single instruction, multiple data
(SIMD) architectures are well suited for low-level image pro-
cessing algorithms, but because of their limited local control,
they can't address complex, high-level algorithms.3 Multiple
instruction, multiple data (MIMD) architectures are better
suited for high-level algorithms, but they require expensive
support for efficient interprocessor communication, data
management, and programming. Regardless of the specifics,
every image processing architecture must address the follow-
ing requirements: processing power, efficient data address-
ing, and support for data management and I/O.
We can divide image processing architectures into the fol-
lowing broad categories: dedicated image processors, image
processing accelerators, and image-processor ICs. The dedi-
cated image-processor systems usually include a host con-
troller and an imaging subsystem that embodies memory,
custom processing ICs, and custom or commercially available
math processing units, connected in a SIMD, MIMD, o r
mixed-type architecture. Researchers are developing most of
these systems either at universities for study in image pro-
76
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cessing architectures or at corporate lab-
Px64 oratories for in-house use or for specific
customers and applications.3"
- Developers usually design image pro-
Yes cessing accelerators as attached boards
Yes or subsystems for commercially-available
personal computers or technical worksta-
tions. These accelerators use standard
buses (VME, EISA, Nubus, and so forth)
360 x 288 to communicate with the main host, and
100:l to 2,000:l port, a frame buffer, and o n e t o four
commercially available DSPs (such as the
TMS320C40 from Texas Instruments) or
~
high-performance microprocessors (such
as the Intel 860). Most accelerators use
Application-specific image ICs
You can implement most image processing functions on a
general-purpose digital signal processor, and several vendors
offer such solutions today. Such solutions are generally not
amenable to real-time applications because of the processing
requirements and the resulting high cost associated with using
multiple DSPs per system. Let's look at several chip sets that
you can use for image and video compression and for tradi-
tional image processing systems like computer-vision systems.
ICs for image and video compression
Workstations today possess significant capabilities, includ-
ing high-performance CPUs (70 to 100 million instructions
per second), high-performance display subsystems, and ex-
tensive networking and storage support. Such workstations
offer a viable platform for multimedia applications requiring
images and video. However, the bandwidth and computation
power of these workstations is not adequate for the compres-
sion functions needed for video and image data. A single 24-
bit image at 1K x 768 resolution requires 2.3 Mbytes of
storage, and an animation sequence with 15 minutes of ani-
mation would require 60 Gbytes. For imaging and video ap-
plications (and multimedia computing in general), recent
research has focused on image and video compression. This
research has progressed along two fronts-the standardiza-
tion of compression techniques and the development of ICs
that can perform the compression functions these standards
require. As shown in Table 1, the image and video compres-
sion standards now being developed fall in four classes:
JPEG, MPEG-I, MPEG-11, and Px64.
IC vendors offer single-chip solutions for JPEG, Px64, and
MPEG. The JPEG standard' is intended for still images. How-
ever, researchers are also using it in edit-level video applications,
where there is a need for frame-by-frame processing. The
MPEG (I and 11) standard applies to full-motion video and was
originally intended for CD-ROM applications wherein encoding
IEEE Computer Graphics & Applications
 -~ - - ~- - - ~

configuration, the broad-

Table 2. Image and \ideo compression IC vendors.
casters are attempting to in-
11

Vendor ~ Part Number Standard

~ ~ Speed 1 Comments /1
corporate up to four video
channels in the present 6
C-Cube 1 CL550 JPEG IO m d 27 M H / MHz single-channel band-
Microsystems ~ CL450 1 MPEG-I 3 0 franicsisec Decode only width. The increased chan-
CL950 MPEG-I 30 framesisec Can be used
~

nel capacity has significant

at MPEGII
resolutions business implications.
_c The Px64 (H.261) stan-
AT&T AVP-I300E JPEGIMPEG-I/ 30 franiesisec Encodct- only. dard is intended for video
Px64 Data rates conferencing applications.
up to 4 Mhps
~~
This technology is mature.
A V P -1400D JPEGiMPECi-I/ 1 30 frame\isec Decoder only. hut the devices available to
Px64 Spatial resolution accomplish video confer-
uptolKx1K cncing have bccn multi-
-~
board level products until
NEC JPEGIMPEG-I/ 30 framesisec 352 x 240 encoding at
PX64 30 framesisec. now. As CPU capabilities
JPEG solution require.; increase. we expect some
only two chips o f these functions to mi-
-- -~ - -
prate to the CPIJ. How-
~~ ~ ~~ ~

Integrated VP JPEGiMPECi-I/ 30 framcsisec MPEG-I encoding ever, a calculation of the

Information Px64 at non-real time.
Technology Kcal-time decoding speed (generally measured
at 352 x 288 spatial in MIPS. million instruc-
resolution tions per second) require
I compression schemes indi-
Intel 82750 JPEGIMPEGII 3 0 fr‘imesiwc Real-time decoding at cates that such an eventual-
Pxh4 352 x 288 spatial
rewlution MPEG-I i t y is at least five years
encoding c,ipabiltty away. For example. the
n o t known Px64 compression scheme
- -
requires more than 1.000
LSI Logic , LS647xx JPEGIMPEGII 3 0 trmiesiscc Requircs u p to 7 ICs MIPS for encoding a n d
Px64 f o r ti1 u I t ih t md,ird
comprewon about 200 MIPS for decod-
I
---____
t - ing.‘ The 1.000 MIPS re-
SGS- STV3200 JPEGIMPEG Pei forms 8 x 8 and quirement for encoding
Thompson I 6 x 16 D<’T for JPEG will not be achievable
and MPEG core cheaply on a desktop in the
-- ~~

STV3208 JPEGiMPEG Performs 8 x 8 DCT near future. On the other

lor JPEG and hand, MPEG decoding
I MPbG core should become feasible on
a desktop by 1994. Thus,
STI3220
~ Perfoinis motion
estimation for application-specific ICs
MPEG “I Px64 seem to be the only viable
encoding near-term solution. For still
~-

images. we can optimize

Matsushita 15 tramesisec 64 Khps encoder out-
the JPEG algorithms to ac-
put r,ite 352 x 288
s p i t i d resolution complish interactive pro-
- ~-
cessing on a desktop
workstation. However, if
we use J P E G for motion
would be done less frequently than decoding. MPEG-1’ offers sequences. a desktop system cannot easily support the 30
VHS quality decompressed video, whereas the intent of MPEG- frames per second data rates, and in such cases, a chip-based
11 is to offer improved video quality suitable for broadcast appli- solution is appropriate.
cations. Recently, video broadcast companies proposed video In Table 2. we list representative image and video compres-
transmission schemes that would use an MPEG decoder and a sion chips offered by various IC vendors. The chip designs
modem in each home. By optimizing the decoder and modem from Matsushita and NEC have been disclosed, but they are

November 1992 77

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 not yet commercially available. The remaining designs are ei-
ther available now or will be by the end of this year.
Designers optimized these chips for a core set of four com-
pression-related functions:
1. spatial-to-frequency domain transformations,
2. quantization of frequency-domain signals,
3. entropy coding of the quantized data, and
4. motion compensation.
For compression of motion sequences, these chips also em-
ploy additional processing in the temporal domain. Let's look
briefly at the processing steps for the JPEG, MPEG, and
Px64 compression schemes.
Spatial-to-frequency domain transformation. The chips
accomplish spatial-to-frequency domain transformation via an
8 x 8 2D discrete cosine transform (DCT) performed on the
spatial domain data. Often the chips first convert RGB (red,
green, blue) spatial domain data into a color space suitable for
image compression. The system uses the YCrCb space (a
commonly used color space) for this purpose. The 2D DCT
can be performed as straightforward matrix multiplication, as
matrix-vector multiplication (on 16 vectors), or via a fast DCT
algorithm. A hardware implementation would use straightfor-
ward matrix-vector multiplication methods or fast DCT algo-
rithms with a regular structure, whereas a programmable
image computing engine (like a DSP) would use only a fast
DCT implementation that has a small multiply count.
Quantization. The system quantizes frequency domain
samples to eliminate some of the frequency components.
This results in a loss of detail that worsens as the compres-
sion ratio is increased. The quantization function is a point-
wise divide (and rounding) operation.
Entropy-coding. The quantized data has few values, and
there is usually a run of zero-valued samples between non-
zero-valued samples. Developers usually use a Huffman cod-
ing method employed on the run (for example, a baseline
JPEG standard). For decoding, a lookup-table-based approach
is faster and more efficient for software implementations.
Motion compensation. In CD-ROM applications, since
CDs output data at a 1 to 1.5 Mbits per second rate and digi-
tized NTSC rates are at 80 to 130 Mbits per second, developers
need compression ratios around 1OO:l for CD-ROM based
video. When developing the MPEG standard, designers ex-
pected that many video applications would be CD-ROM
based. To achieve such high compression ratios, developers
need to exploit both intraframe and temporal redundancies.
This is accomplished through motion compensation. We find
this technique in MPEG and F'x64 encoding; frame-to-frame
changes are determined and only the changes are transmitted.
In most motion estimation implementations, the system per-
forms some form of block matching between blocks compris-
ing frames. This feature is highly parallelizable and is exploited
in some of the MPEG and Px64 encoders.
78
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Let's turn from explaining the ICs' image-compression
functions to examining the chips themselves. We briefly de-
scribe the JPEG and MPEG ICs offered by various vendors.
CL550
The CL550 is a single-chip JPEG compression and decom-
pression engine offered by C-Cube Microsystems." It con-
sists of a pixel-bus and a host-bus interface for data IIO,
control registers, and a JPEG core unit with a DCT coeffi-
cient register, a quantizer, and Huffman tables. Compression
ratios can range from 8:l to 100:l and are controlled by the
quantization tables within the chip. The chip has on-chip
video and host-bus interfaces and thus minimizes the glue
logic needed to interface the chip to the computer's or dis-
play subsystem's bus.
The CL550 chip can handle up to four color channels, and
thus we can use it either for printing (images are handled as
CMYK-yan, magenta, yellow, black) or for image display
and scanning (images are handled as RGB). This chip also
provides memory interface signals and can process data at a
27 MHz rate. Thus, we can use it in full-motion video appli-
cations that need frame-to-frame access. (MPEG uses inter-
frame coding methods that require several frames to be
decoded to access a specific frame.) Similar chips will soon be
offered (or proposed) by SGS-Thompson and LSI Logic.
CL450
The CL450 is a single-chip MPEG-I decoder from C-Cube
Microsystems. Compact disc systems (such as the Philips CD-
I player) that play back audio and video use such a chip for
video playback. As with the CL-550, designers minimized the
glue logic required for interfacing to buses and other chips by
providing bus logic and memory control signals within the
chip. In a small system, we might need to add up to one
megabyte of dynamic RAM for MPEG decoding.
The CL950 is similar to this chip. However, it can support
data rates and spatial resolutions proposed for MPEG-11.
Combined chip sets
Multimedia computing systems will deal with JPEG, MPEG,
and Px64 compressed data. For cost-effective solutions on the
desktop, it is highly unlikely that designers will use separate
chips for each standard. Thus, several IC vendors have devel-
oped (or proposed) JPEGIMPEGIPx64 chip designs that can
handle all three of the major multimedia compression, de-
compression, and transmission standards.
AT&T multistandard chip set
The AT&T chip set" includes the AVP-1400C system con-
troller, the AVP-1300E encoder, and the AVP-1400D de-
coder. The system controller addresses the issue of trans-
mission of multimedia data (this is a key differentiator in
AT&T's multimedia chip set offering). The controller pro-
vides the usual multiplexing and demultiplexing of MPEG or
Px64 streams and performs error correction. Furthermore,
IEEE Computer Graphics & Applications
 exhaustively over a range of 532 pixels with half-pixel
Address
generator ~
accuracy. Users can select the channel bit rate from 40
Kbits per second to 4 Mbits per second (the latter is
Static closer to the proposed MPEG-I I specifications) using a
RAM
Pod
---A---
PlJ0 DCT
constant bit rate or a constant quantization step size.
Spatial resolution can go up to 720 pixels x 576 lines.
You can use the 1300-E in the intraframe mode and thus
perform JPEG-like encoding.
The encoder contains several functional blocks:
1. a host bus interface,
2. FIFO to hold unconipressed data.
3. memory controller to interface to external dynamic
I24 x 24 register1
window
~ 1 x8 18
1 window
register^ 1 Memory RAMS,
4. motion estimator.
3 5. quantization processor to determine quantizer step-
size and output frame rate,
6. signal processor comprised of six SIMD engines that
perform DCT, quantization, and zigzag scanning,
7. global controller to sequence the operation of the
blocks,
8. entropy coder t o generate data compliant with
64-word FlFOs A1 r44-1
Memory-A Memory-B I MPEG and H.261 standards, and

RAM
- . _-
- ~ -

I (128-word x 4 ) l (128-word)
9. output FIFO to hold compressed data.

I The decoder is less computation-intensive (primarily

I because it need not estimate motion). The AVP-1400D
I 44 I performs decoding up to 4 Mbits per second compressed
DSP I
unit I
I
[ Four multipliers
(16-bit)
r ~ ---
1 data stream rate and can support frame rates up to 30
frames per second. The AVP-1400D can support spatial
resolutions up to 1,024 lines x 1,024 pixels (the larger
spatial resolutions are useful in JPEG still-image applica-
tions). The decoder has an on-chip color space con-
b L verter, so you can convert the decompressed YCbCr
data directly to RGB.

NEC multistandard chip set

registers The NEC multistandard chip set" can encode and de-
Address ' StatlC RAM code MPEG video in real time. Like the AT&T chip set,
generator +address this chip can support all three compression standards.
I 1 I '
Unlike the AT&T chip set. the encoding and decoding
Entropy algorithms are split across several chips. The first chip
encoder, decoder
performs interframe prediction, the second executes the
DCT transform and quantization, and the third one does
Figure 1. The NEC multistandard chip set. (a) Interframe predic-
entropy coding. We depict these chips in Figure 1. The
tion, (b) DCT and quantization, and (c) variable length coding.
chip set estimates motion in the prediction engine, but
unlike AT&T's encoder, the motion search strategy is a
two-step process. In NEC's motion estimation algorithm,
the concentration highway interface provides an interface to the first search step is over a one-fourth subsampled area,
channels like T l and ISDN. This interface also supports the and the second search step occurs over a 18 x 18 window and
synchronization of audio and video streams, an important yields half-pixel accuracy. The DCT and quantization engine
feature in multimedia systems. In a JPEG-only system, this is a DSP unit that has four 16-bit multiply and accumulate
chip is not required. (MAC) units and 24-bit arithmetic logic units (ALUs). The
The AVP 1300-E performs single-chip MPEG-I encoding. entropy coding engine has a RISC core, performs all the bit-
The 1400-E version supports MPEG-I and Px64 compression stream coding functions, and provides control for basic play-
and uses a fixed motion-estimation processor that searches back functions like stop, play, and random access.

November 1992 79

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 IIT multistandard chip set
The IIT multistandard chip set" takes a different approach
from the AT&T chip set. It offers a programmable chip (re-
ferred to as the Vision Processor), and the microcode-based
engine of this chip can execute JPEG, MPEG, and Px64 com-
pression and decompression algorithms. This chip has a
RISC processing core, a direct memory access port (DMA)
for data access, and a command port. You can also connect
this chip set to optional microcode static RAM. This chip can
perform JPEG, MPEG, and Px64 decoding at 30 frames per
second at spatial resolutions of 352 x 240. For MPEG encod-
ing in real time, you will need two Vision Processors. For
MPEG and Px64 applications, the Vision Processor is com-
bined with a vision controller chip that handles the pixel in-
terface and frame buffer control functions.
Intel 82750
This is Intel's third-generation design of the 827.50 family.
Earlier versions were designed primarily to decode Digital
Video Interactive (DVI) compressed data. This chip offers
1,000 MOPS (million operations per second) and operates at
50 MHz. Because of the MOPS requirements for MPEG en-
coding, the 827.50 with this MOPS rating might not be suit-
able for MPEG encoding. However, it can easily accomplish
MPEG decoding. Furthermore, a system can decode multiple
MPEG streams with a single 82750, and thus in a desktop en-
vironment you could view several video sources simultane-
ously. The programmable nature of the 827.50 allows for
JPEG and Px64 encoding and decoding. (At this time. we are
not aware of the availability of this processor.)
Other vendors
Zoran14 offers a two-chip solution for use in still-image
compression applications where the encoder bit rate needs to
be a fixed rate. This is essential in applications like digital
still-video cameras. The Zoran chip set achieves the fixed
rate via a two-pass process. During the first pass, the chip es-
timates bit rate from the DCT values. The chip actually codes
during the second pass by controlling quantization based on
information derived from the first pass.
Since many of the compression and decompression pro-
cesses resemble DSP methods, traditional DSP IC vendors
such as Texas Instruments, Motorola, and Analog Devices
will probably announce JPEG and MPEG solutions based on
an optimized DSP core. In fact, Matsushita" recently dis-
closed that, according to their estimates, the DSP engine that
they specially designed for 2 giga-operations per second
(COPS) can provide decoding of Px64 compressed video at
15 frames per second.
From the graphics side, IC vendors like Brooktree and In-
mos will have compression and decompression chip sets
based on an optimization of the graphics core in their current
offerings. For a multimedia computer, we believe that a chip
set with a high level of integration and support for host bus
80
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interface and dynamic RAM control logic would probably be
preferable.
ICs for generic image processing
In computer vision and most traditional image processing
systems, the computer performs a significant amount of pro-
cessing with low-level image processing functions. For exam-
ple, in computer vision systems, you might want to perform a
semi-automated PC board inspection. T o do this, the system
must image a PC board at video rates (256 x 256 x 8 bits per
pixel acquired at 30 frames per second), detect the edges of the
digital image, and make a binary bitmap of the edge-detected
image. Then the system might perform a template-matching
function on the binary image to determine faulty traces on the
board. The above-mentioned tasks require at least 120 MOPS
of processing capability. Most general-purpose DSPs cannot
deliver such fast processing at sustained rates. To make appli-
cations like these feasible, IC vendors offer single-chip solu-
tions for many of these image processing tasks.
ICs for image filtering
LSI Logic'' offers the L64240, a multibit, finite impulse re-
sponse filter (MFIR). This chip is a transversal filter consist-
ing of two 32-tap sections. Each 32-tap section contains four
separate eighth-order finite impulse response filter sections.
Each filter cell within a filter section consists of a multiplier
and an adder that adds the multiplier output and the adder
output of the preceding filter cell. This chip can generate out-
put at a 20 MHz sample rate with 24-bit precision. This device
is suitable for both adaptive filtering and cross-correlations,
since the convolution kernel can be loaded synchronously
with the device clock.
The L64240 has a format-adjust block that provides the ca-
pability to scale (with saturation), threshold, clip negative
values, invert, or take absolute value of the output (these
functions are useful in image enhancement and in image dis-
play). The chip is reconfigurable and can perform l D , 2D,
and 3D filtering. With the incorporation of a frame delay,
you can configure it as a 3D filter in which a 4 x 8 convolu-
tion is performed across two frames.
ICs for image enhancement
In many imaging applications, users acquire the image data
from a noisy source, such as a scanned image from a photo-
copy. Users must apply some noise reduction function to this
image. One such technique is rank-value filtering, such as me-
dian filtering. An IC that does this at a 20 MHz rate is the
L64220 from LSI Logic. Like the MFIR, this is a 64-tap recon-
figurable filter. However, the output is from a sorted list of the
input and not a weighted sum of the input values, like the
MFIR's filtering function. You can configure the filter to per-
form rank-value operations on 8 x 8, 4 x 16, 2 x 32, or 1 x 64
masks. The rank-value functions include min, max, and median.
In many image processing applications, users need to en-
hance the acquired image to incorporate it into an electronic
IEEE Computer Graphics & Applications
 image. For each contour, it returns the (.U, y ) coordinates, dis-
crete curvature. bounding box. area. and perimeter. In an
OCR application, the system can use this data as part of a fea-
ture set for template matching in feature space. Thus, the sys-
tem can recognize a character (whose 128 x 128 imagc is input
to the contour tracker). In conventional computer-vision ap-
plications. you can use the contour tracker as a component in
a system t o identify objects. This could be the front-end sig-
k- - a nal-processing component of a robot. For an n x m image. the

L+
-

Histogram contour tracker takes 4.5 nnz cycles to generate the contours.
New ““%x
11 ADDR
(512 ~ 2 4 )
I
Counter DI LUT RAM DO +-t
f Transformed
data
You can also use this IC to compress black-and-white im-
ages in which the contour information will represent the
Counter compressed data. For most textual documents, this could
New frame,-- 0 yield high compression ratios compared with the traditional
Figure 2. The L64250 chip: histogram and Hough-transform IC. Group 111 and Group IV fax-compression methods.
You can use an IC‘ such as the Lh4230 (also from LSI
Logic) for template matching and binary niorphological opera-

I 4’
1
AA AB
‘ $ 4
_L-1
h oiic
M - U U I..
)
I tions. These processing functions are usually required in the
preprocessing stage of an image recognition system. By chang-
XSYNCdTimingl 1 Address I ing the setup and filter corfficients. this IC can perform FIR
control generation1 filtering, templatc matching, erosion. and dilation functions.
Y SYNC-’ unit ~ unit

General-purpose image ICs

I
i 0-BUS
Figure 3. A block diagram of the Video Image Signal Proces-
sor (VISP).
document. A popular image enhancement technique is his-
togram equalization.” To do this, you compute the histogram
of the input image and then apply a function to the input that
equalizes the histogram. In Figure 2 we show a simplified
block diagram of LSI Logic’s L64250, which can equaliie his-
tograms at a 20 MHz rate on data sets as large as 4K x 4K.
The accumulation memory ( “ A C C RAM” in the figure)
holds the histogram for the input data (DI). and this memory
is updated for each set of input data. After processing a
frame of data, the chip can use the accumulation memory’s
contents to compute an equalization transfer function that
can then be transferred to the lookup table RAM. The chip
then uses the image data to index the lookup table RAM,
and the output is the histogram-equalized image. You can
also reconfigure the L64250 chip to compute the Hough
transform of an image, a common preprocessing operation in
many computer vision tasks.
ICs for computer vision
A n IC useful for computer vision and optical character
recognition (OCR) is the object contour tracer (L64290 from
LSI Logic). This chip locates contours of objects in a binary
Designs for general-purpose image processors (IPS) must
combine the flexibility and cost eficctiveness of a program-
mable processor with the high performance of an ASIC.
Therefore, it is no surprise that one class of programmable
image processors are extensions of general-purpose DSP
chips. We call them zitziprocc‘ssor IPS.They include one multi-
ply and accumulate (MAC) unit. separate buses for instruc-
tion and data. and independent address generation units.
Depending on the target applications, they also include spe-
cial arithmetic function units. on-chip DMA, and special data-
addressing capabilities (for example. dual arithmetic units for
computing absolute values or L 2 norms in one cycle).
Another class of image processors have an internal multi-
processing architecture. We call them nzultiprocessor IPS. Re-
searchers develop almost all these chips for in-house use. and
they are targeted to specific applications (video processing,
machine vision, data compression. and so forth). Multipro-
cessor I Ps don’t seem to be commercially available.
Uniprocessor IPS
Let’s look at these two categories of ICs-uniprocessor
and multiprocessor-more closely. We begin with uniproces-
sor IPS.
VISP
Figure 3 shows a block diagram of the Video Image Signal
Processor (VISP) from NEC.I8 This design is representative
of most programmable, uniprocessor IPS that can be consid-
ered extensions of general-purpose DSPs. VISP is a 16-bit
video processor developed for real-time picture encoding in
TV conference systems. I t has two input and one output data

November 1992 81

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 A-BUS last stage is a minimum value de-
B-BUS tector (MMD) that codes motion
pictures efficiently.
In similar designs, Toshiba’s
A-BUS IP2’ has dual ALUs to compute
I I
I I
an absolute value in one cycle, Hi-
tachi’s IP has special hardware to
I
.... . search for minimum and maxi-
64/ mum values,’’ and Matsushita’s
Real-time Image Signal Processor
B-BUS 22
(RISP) processor has a multi-
plier and divider unit and a spe-
8x8 8x8 8x8 8x8 8x8 8x8 8x8 8x8
cial flag c o u n t e r t o average
operations fast.
Instead of on-chip D M A and
data memories (as in VISP, DISP,
and Hitachi’s IP), Toshiba’s IP has
hardware support for direct access
to three external memories, and
RISP has an array of 25 local im-
Figure 4. A block diagram of the Figure 5. A block diagram of ViTec’s age registers and buffers with a 25
Video Image Signal Processor (VISP) Pipelined Image Processor. to 1 selector. This feature lets
processing unit. RISP freeze and operate on a 5 x
5 array of image pixels at a time.
RISP addresses the data by set-
ting the multiplexers’ select code.
buses, two local RAMS (128 x 16-bit each in the data memory The VISP processor has a 25 nanosecond cycle time, and, like
unit (DMU)), an instruction sequencer, a 16-bit ALU, a 16 x most of the other image processors, you can use it in a multi-
16-bit multiplier, a 20-bit accumulator, a timing control unit, processor array.
an address generation unit, and a host interface unit. For effi-
cient IIO, the processor has a built-in DMA controller in the Multiprocessor IPS
host interface unit. The address generation unit can support The latest designs of image processing ICs combine fea-
up to three external buffer memories. Like Hitachi’s IP” and tures from both DSP architectures and classical SIMD and
the Digital Image Signal Processor (DISP) processor from MIMD designs. Advances in integration now allow multiple
Mitsubishi?’ VISP has hardware support to translate a 2D processing units on a single chip. Thus, these designs com-
logical address to a 1D physical memory address. This feature bine the power of parallel architectures with the advantages
is important in image processing applications, where we can of monolithic designs.
describe many of the low-level algorithms by
ViTec’s PIP
P 4
cc
Y ( i , j ) =m=l n=l cmnx(i- m, i- n) Figure 5 shows a block diagram of ViTec’s Parallel Image
Processor The PIP chip is the core of ViTec’s multipro-
where x and y are the input and output images, and c is a p x cessor imaging systems.24It is probably the first image-proces-
q matrix (kernel) of algorithm-dependent coefficients. For ef- sor chip that employs an on-chip parallel architecture. Each
ficient addressing, special pointers are required to move the chip has eight 8-bit ALUs and eight 8 x 8 bit parallel multipli-
kernel of coefficients within an image and to access the data ers. A nine-way 32-bit adder combines the results out of the
within a kernel window.’’ multipliers. This architecture is highly efficient for convolu-
VISP’s A L U is specially designed to compute pattern tion operations. The chip uses a special replicator to replicate
matching operations in a pipelined manner. It can compute zooming. This architecture has limited local control, but it can
either L1 or L2 norms for vector quantization and motion provide up to 114 MOPS, assuming an 8-bit wide data path.
compensation operations. Figure 4 shows a block diagram of Communication with an image memory occurs via a 64-bit
the ALU. The first stage has two shifters (SFT) for scaling bidirectional bus. A separate 32-bit bus allows interprocessor
the input video data. The second to fourth stages are for the communication in multichip systems. As in Hitachi’s IP,” the
ALU and the multiplier. The output of the multiplier is ex- PIP chip uses two levels of internal control. A 4-bit instruction
tended to 20 bits by the Expand module in the fifth stage. combined with a 6-bit address selects a 64-bit micro-instruc-
Data is further scaled by a 16-bit barrel shifter (BSF). The tion contained in an on-chip writable control store.

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 Pipeline IP

We can consider the Pipe-

line IP chip from Matsushita"
a variation of the ViTec de-
sign. It consists of nine pro-
cessing elements positioned
side by side. However, in this
design (shown in Figure 6).
you can reconfigure t h e
neighbor interconnections be- I
tween t h e processing ele- I I
I D I
ments. E a c h subprocessor I
consists of a 13 x 16-bit multi- I
I
plier, a 24-bit accumulator. I I I c
pipeline registers. and multi- l I I ACC
plexers. The multiplexers al-
low different interconnection
a -d
I
< D
+-
topologies a m o n g t h e pro-
cessing elements, and the sys-
tem c o m p u t e s image p r o -
cess ing o p e r a t i o n s sy s t o I i -
cally. The processor has three
input and one output ports Figure 6. A block diagram of the Pipeline Image Processor.
and several pipeline-shift reg-
isters. This architecture is very efficient for matrix-type and I 300 lmaae bus
filtering operations and can compute an eight-tap DC'T using
a brute-force technique (matrix-vector multiplication).
Image
data
in Shifter $
Image 1 r - l Data'nput
-{-- i/
bus- - l

ISMP
Figure 7 shows the block diagram of ISMP,"' a digital im-
age signal multiprocessor version of the RISP" architecture
I l l
we referred to earlier. Also manufactured by Matsushita. I l l
ISMP has a main controller, an arithmetic unit, and four 12- I l l
bit processor elements. Each processor element has a local
I 1 _ _ _ _ _PEA1 PE-BLPE-CLPE-D
t 1 Dataoutput us
- -

image register, a 24-bit ALU and a 13 x 12-bit multiplier. 0 Jf

ISMP also has its own instruction RAM and local controller. p r o g r a m data bus I l l
You can use this chip to either operatc at different locations
Figure 7. A black diagram of ISMP.
of the image or on the same location, but with
four different feature extraction programs.
ISMP chips can also operate in a multiproces-
Ji
sor array. 1 Address generation unit I
To resolve the problem of feeding four dif-
ferent processors with data, the ISMP has a
Program
~

i memory 1
and
-1-
Work
~

Cache
+ Cache
7-
sequencer memory memory 1 memory
global image register and four local image reg-
isters. The global register consists of five 12-
bit-wide shift registers, each with a 12-bit
input port, and drives a n image bus of 300
lines. The local image registers, located in
each processor element, receive a 5 x 5 pixel
window from the image bus. This window is
latched at the falling edge of a "start" signal
that starts the execution of each processor ele- ~~ ~ - ~-

ment. The processor has a 20 nanosecond cy- Protram bu f f f

Program load bus I
cle time and can compute a 32-level histogram
of a 256 x 256 pixel image in 23.6 milliseconds. Figure 8. A block diagram of IDSP.
November 1992 83

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 i System

Toshiba
CMOS
Table 3. Programmable image processing ICs.
-
Clock
(ns)
50
Instruction
RAM

6 4 x 16
16 x 99
None
I

P E s , B S
32 x 32 MPY
I

~ 32

I Hitachi

ViTec’s
;T---
1987
CMOS

CMOS
50

~-

20

70
~
1,024 x 48
64x 16

32 x 128

64 x 64
64 x 16
~

8X5X5
_ _

Divider

Pipeline
I
30 None

25 512 x 32

Normalizer
____

1990 1
CMOS

1.2CMOS
50

20
512 x 48

40 x 128/IP
5 1 2 x 2 4 ~ 2 ALU
64 x 24-
userstack

12 X?
~MPY
BS

4 RISP IPS
I
~
24

1991 0.8 BiCMOS 40 512 x 32 5 x 512 x 16 4 DPUs

~.
I/

I
Year denotes the year of publication of the corresponding reference. MPY denotes multiply unit,
MAC stands for multiply and accumulate unit, and BS denotes a barrel shifter. On the bit field, a dual
number such as AIB denotes that the chip uses A bits for input, but output or internal
results might also be available with B bits of precision.

IDSP Texas Instrument‘s video processor

Figure 8 shows NTT’s Image Digital Signal Processor
(IDSP), another parallel architecture of a video signal pro-
27
cessor. This processor has three parallel I/O ports and four
pipelined processing units. Each processing unit has a 16-bit
ALU, a 16 x 16-bit multiplier, and a 24-bit adderhbtracter.
Each I/O port has a 20-bit address generation unit, DMA
control processor, and U0 control circuitry. Data transfers
and program execution occur in parallel.
Each data processing unit (DPU) unit has a local data
cache memory and also shares a work memory. All memories
are configured as 512-word x 16-bit dual-port RAMS. The
system transfers data via ten 16-bit vector data buses and a
16-bit scalar data bus. As in other architectures, where con-
ventional VLIW (very large instruction word) would require
hundreds of bits, the IDSP uses two levels of instruction de-
coding. IDSP has a 40 nanosecond instruction cycle time.
Texas Instruments is working on an advanced processing
chip for imaging, graphics, video, and audio processing.”” It
will support all the major imaging and graphics standards
(like JPEG, MPEG, PEX, and MS Windows). It will have
both floating-point and pixel-processing capabilities for 2 0
image processing and 3D graphics.
The proposed product will have multiple processors on a
single chip. One of these will be a RISC floating-point pro-
cessor. The remaining processors will have a mixture of DSP
and pixel-manipulation capabilities. The on-chip processors
will be fully programmable and have instruction caches, thus
each of the processors will be able to run independently in a
MIMD fashion. The processors and on-chip main memory
will be connected via a crossbar. Texas Instruments estimates
that performance will be in the range of 3 billion “RISC-like”
operations per second.

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 Table 3 summarizes the major features of the image-pro-
cessor ICs. Table 4 shows benchmark results for two classes
of algorithms for which data for most of the above ICs is
available: a block type algorithm, such as the FFT or DCT,
and a spatial filtering algorithm with a 3 x 3 kernel.
Imaging and graphics
An area of special interest to both computer workstation
manufacturers and IC developers is the integration of image
processing with computer graphics. Traditionally, developers
considered these separate fields and designed acceleration
engines specifically for imaging or graphics. However, the
proliferation of window-based user interfaces (which can
benefit from graphics acceleration), the combination of tradi-
tional image processing operations (like texture mapping and
warping) with graphics techniques, and the emergence of
multimedia applications have motivated manufacturers and
developers to work on systems that integrate graphics, imag-
ing, audio, and video.
In general, requirements for graphics architectures differ
from those in image processing. Most graphics accelerators
follow the well established graphics pipeline: Host, transfor-
mation unit, clipping, illumination, scan conversion and shad-
ing, a n d display.2y In graphics, systems p e r f o r m most
operations on polygons or vectors. Regardless of the front-
end operations (transformations, lighting, and so forth), the
back-end operations are always scan conversion and z-buffer
interpolation. The regularity of the graphics pipeline makes it
easier for hardware designers to decide which part of the
pipeline needs t o be accelerated by special processors. In
contrast, image processing applications always operate at the
pixel level and do not usually follow a single computational
path. Furthermore, most front-end operations in graphics re-
quire floating-point arithmetic. In contrast, only high-level
imaging operations require floating-point accuracy.
be determined for each scan line. However, this type of oper-
ation is also well suited for an image processor.
High-end graphics workstations will always require appli-
cation-specific ICs. However, the new image and video pro-
cessors should provide adequate performance t o satisfy the
needs of most users. The latest designs from Intel and Texas
Instruments claim to support both imaging and graphics.
Such systems should assist in making the integration of
graphics and imaging a reality.
Conclusions and predictions
Circuitry that accelerates image processing will be an inte-
grated part of future personal computers and scientific work-
stations. In this article, we reviewed recent architectures for
image processing ICs. Application specific processors are
available for image and video compression and low-level im-
age processing functions. Programmable image processing
ICs are either modified extensions of general-purpose DSPs
or incorporate multiple processing units in an integrated par-
allel architecture. Because of the iterative nature of low-level
imaging, such parallel architectures are ideal for fast image
processing.
A new generation of programmable video processors will
soon emerge to accommodate the special needs of real-time
video processing. They will consist of multiple computing
Table 4. Benchmarking results for programmable
image processing ICs.
Filtering
Processor Transform (256 x 256 data,
3 x 3 mask)
ms
1

i
T h e s e diverse requirements and t h e absence of pro- Toshiba FFT, 1,024 points
grammable image processors forced most developers to use 1.0 ms
general purpose processors (such as Intel’s i860 or the TI ~~

TMS32040) to provide an integrated solution.’ However, the Hitachi FlT, 512 points 39.3
new generation of image and video processors might allow 1.5 ms
___________ -
for more efficient solutions. The high performance of the lat-
RISP 11.8
est RISC processors lets us shift most of the computational -~
load, especially the floating-point operations, t o the main FFT, 512 points 26.9
DISP
CPU unit. Then the image processors can execute both imag- 0.91 ms
ing and the last stages of the graphics pipeline.
For example, perspective and z-buffer interpolation are two VISP 2D DCT, 256 x 256 14.8
common graphics tasks usually performed by custom ICs. 26.3 ms
You can describe the pixel arithmetic in those functions by ~~

where 4 , is the quantity t o be interpolated (for example,

RGB specular, or z value z,) for pixel i. which lies in the scan 2DDCT,8x8 1
line between pixels s and e, and S is a scaling factor that must 41.8 ks

November 1992 8f

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units, some of them application specific 2D-data-address-
generation units, and efficient I/O ports. As video compres-
sion standards reach their final form, new image compression
chips will appear for applications like video-teleconferencing
and HDTV. These chips will probably include support for in-
terfacing to digital networks like the fiber distributed data in-
terface (FDDI), will possess computer power in the range of
2 to 4 GOPS, and will include dynamic RAM control for
glueless interfacing to display memory. To smoothly inte-
grate audio applications, these ICs will also include a conven-
tional DSP core for audio processing. 0 Custom Integrated Circuits Con$, 1989, CS Press, Los Alamitos, Calif.,
Acknowledgment
W e thank Alex Drukarev for his helpful comments and suggestions.
19. K. Kaneko et al., “A 50 ns DSP with Parallel Processing Architecture,”
IEEE ISSCC 87, CS Press, Los Alamitos, Calif., 1987, pp. 158-159.
20. T. Murakami et al., “A DSP Architectural Design for Low Bit-rate
Motion Video Codec,” IEEE Trans. Circuits and Systems, Vol. 36,
No. 10, Oct. 1989, pp. 1,267-1,274.
21. A. Kanuma et al., “A 20 MHz 32b Pipelined CMOS Image Processor,”
IEEE lSSCC86, CS Press, Los Alamitos, Calif., 1986, pp. 102-103.
22. H. Yamada et al., “A Microprogrammable Real-Time Image Proces-
sor,” IEEE J. Solid State Circuitry, Vol. 23, No. 1, Jan. 1988, pp. 216-
223.
23. J.P. Norsworthy et al., “A Parallel Image Processing Chip,” IEEE
ISSCC88, 1988, CS Press, Los Alamitos, Calif., pp. 158-159.
24. D. Pfeiffer, “Integrating Image Processing with Standard Workstation
Platforms,” Computer Technology Review, Summer 1991, pp. 103-107.
25. K. Aono, M. Toyokura, and T. Araki, “A 30 ns (600 MOPS) Image
Processor with a Reconfigurable Pipeline Architecture,” IEEE I989
pp. 24.4.1 -24.4.4.
26. M. Maruyama et al., “An Image Signal Multiprocessor on a Single
Chip.” I E E E J . Solid-State Circuits, Vol. 25, No. 6, Dec. 1990, pp.
1,476-1,483.
27. T. Minami et al.. “A 300-MOPS Video Signal Processor with a Paral-
lel Architecture,” IEEE J. Solid-state Circuits, Vol. 26, No. 12, Dec.
91, pp. 1,868-1,875.
28. R.J. Gove, “Architectures for Single-Chip Image Computing,” SPIE
Electronic Imaging in Science and Technology Conf on Image Process-
ing and Interchange, Vol. 1659, SPIE, San Jose, Calif., 1992, pp. 30-40.
29. H.K. Reghbati and A.C. Lee, Computer Graphics Hardware: Image
Generation and Display, CS Press, Los Alamitos, Calif., 1988.

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-- - -
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