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APPLICATION NOTE
ABSTRACT Obviously, a high end electronic lamp ballast will
With a continuous growth rate of 20% per year, electronic certainly include other features like dimming capability,
lamp ballasts are widely spread over the world. Even though lamp wear out monitoring, and remote control, but these are
the light out of a fluorescent tube has a discontinuous optional and will be analyzed separately.
spectrum, the higher efficiency brought by the electronic
control of these lamps make them the best choice to save the Fluorescent Lamp Operation
energy absorbed by the lighting systems. When the lamp is off, no current flows and the apparent
A few years ago, the lack of reliable and efficient power impedance is nearly infinite. When the voltage across the
transistors made the design of such circuits difficult! Today, electrodes reaches the Vtrig value, the gas mixture is highly
thanks to the technology improvements carried out by ON ionized and an arc is generated across the two terminals of
Semiconductor, design engineers can handle all of the the lamp. This behavior is depicted by the typical operating
problems linked with the power semiconductors without curve shown in Figure 1.
sacrificing the global efficiency of their circuits.
I
This Application Note reviews basic electronic lamp
ballast concepts and gives the design rules to build industrial
circuits.
SUMMARY Inom
1. MAIN PURPOSE
− Fluorescent tube basic operation
− Standard electromagnetic ballast
V
− Electronic circuits
Von
2. HALF BRIDGE CIRCUIT DESIGN
3. DIMMABLE CIRCUIT
4. NEW POWER SEMICONDUCTORS Vstrike
5. CONCLUSIONS
6. APPENDIX
Main Purpose
To generate the light out of a low pressure fluorescent
Figure 1. Typical Low Pressure Fluorescent
lamp, the electronic circuit must perform four main
Tube I/V Characteristic
functions:
a. Provide a start−up voltage across the end electrodes of
the lamp. The value of Vstrike is a function of several parameters:
b. Maintain a constant current when the lamp is operating − gas filling mixture
in the steady state. − gas pressure and temperature
c. Assure that the circuit will remain stable, even under − tube length
fault conditions. − tube diameter
d. Comply with the applicable domestic and international
− kind of electrodes: cold or hot
regulations (PFC, THD, RFI, and safety).
Typical values of Vstrike range from 500 V to 1200 V. The most commonly used network is built around a large
Once the tube is on, the voltage across it drops to the inductor, connected in series with the lamp, and associated
on−state voltage (Von), its magnitude being dependent upon with a bi−metallic switch generally named “the starter”.
the characteristics of the tube. Typical Von ranges from 40 V Figure 3 gives the typical electrical schematic diagram for
to 110 V. the standard, line operated, fluorescent tube control.
The value of Von will vary during the operation of the lamp
but, in order to simplify the analysis, we will assume, in a L
first approximation, that the on−state voltage is constant
when the tube is running in steady state.
Consequently, the equivalent steady state circuit can be
described by two back to back zener diodes as shown in TUBE T
S
Figure 2, the start−up network being far more complex, C BI-METALLIC
MAINS TRIGGER
particularly during the gas ionization. This is a consequence 220 V− 50 Hz
of the negative impedance exhibited by the lamp when the
voltage across its electrodes collapses from Vstrike to Von.
Figure 3. Standard Ballast Circuit for Fluorescent Tube
BALLAST
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in a standard circuit. It’s an important problem which can 4, as soon as the current through the lamp runs above a few
lead to visual problems due to the stroboscopic effect on any kiloHertz.
rotating machines or computer terminals.
To take care of this phenomena, the fluorescent tubes, at
η%
least those used in industrial plants, are always set on a dual
basis in a single light spreader, and are fed from two different
phases (real or virtual via a capacitor) in order to eliminate
the flickering.
The value of the inductor L is a function of the input line
frequency (50 Hz or 60 Hz), together with the characteristics
of the lamp.
The impedance of L is given by Equation 1:
ZL = L*ω (1)
with: ω = 2*π*F
F = in Herz L = in Henry Z = in Ohm F
50 Hz 10 kHz 1 MHz
Computing the value of L is straightforward. Assuming a
European line (230 V/50 Hz) and a 55 W tube (Von = 100 V, Figure 4. Typical Fluorescent Lamp Efficiency as a
Vtrig = 800 V), then: Function of the Operating Frequency
P
IRMS + tube (2)
The electronic circuit one can use to build a fluorescent
Von
lamp controller can be divided into two main groups:
IRMS + 55ń100 + 0.55 A
A. Single switch topology, with unipolar AC current,
To limit the steady state current, the impedance must be
(unless the circuit operates in the parallel resonant
equal to:
mode).
LineVon (3) B. Dual switch circuit, with a bipolar AC output current.
Z +
IRMS
The manufacturers of the fluorescent lamps highly
Z + (230100)ń0.55 + 238 W recommend operating the tubes with a bipolar AC current.
Therefore, the inductor must have a value of (assuming This avoids the constant bias of the electrodes as an
the pure Ohmic resistance of the total circuit being Anode−Cathode pair which, in turn, decreases the expected
negligible): lifetime of the lamp.
Z In fact, when a unipolar AC current flows into the tube, the
L +
2*p*F electrodes behave like a diode and the material of the
cathode side is absorbed by the electron flow, yielding a
L + 238ń(2 * p * 50) + 0.75 H rapid wear out of the filaments.
In order to minimize the losses generated into the inductor As a consequence, all of the line operated electronic lamp
by Joule’s effect, the DC resistance must be kept as low as ballasts are designed with either a dual switch circuit (the
possible: this is achieved by selecting a current density of 4 only one used in Europe), or a single switch, parallel
A/mm2 maximum for the copper. resonant configuration (mainly used in countries with 110 V
However, the end value of the wire diameter used to lines), providing an AC current to the tubes.
manufacture the inductor will be limited by the cost, the size A few low power, battery operated fluorescent tubes are
and the weight expected for a given inductor. driven with a single switch flyback topology. But, the output
The trigger switch S is a standard device. transformer is coupled to the tube by a capacitive network
The electromechanical ballast has two main drawbacks: and the current through the lamp is alternating. However, the
a. Ignition of the lamp is not controlled. filaments (if any) cannot be automatically turned off by this
b. Light out of the lamp flickers at the same frequency as simple configuration and the global efficiency is
the AC line voltage. downgraded accordingly.
But, on the other hand, the magnetic ballast provides a The dual switch circuits are divided into two main
very low cost solution for driving a low pressure fluorescent topologies:
tube. A1 Half
− bridge, series resonant.
To overcome the flickering phenomenon and the poor A2 Current
− fed push−pull converter.
start−up behavior, the engineers have endeavored to design
electronic circuits to control the lamp operation at a much The half bridge is, by far, the most widely used in Europe
higher frequency. The efficiency (Pin/Lux) of the (100% of the so−called Energy Saving Lamps and Industrial
fluorescent lamp increases significantly as shown in Figure applications are based on this topology), while the push−pull
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is the preferred solution in the USA with around 80% of the electronic lamp ballasts using this scheme today (see typical
schematic diagram Figure 5).
T1
Q1
C2
DRIVER Lp
C3
NETWORK Q2 Von Itube
LINE
FILTER
C1
LINE
220 V
FLUORESCENT
TUBE
Figure 5. Typical Current Fed, Push−Pull Converter
Both of these topologies have their advantages and Push Pull Topology
drawbacks, the consequence for the associated power The main advantage of the current fed push−pull
transistors being not at all negligible as shown by Table 1. converter, besides the common grounded Emitter structure,
is the ruggedness of this topology since it can sustain a short
Table 1.Main Characteristics of the Dual Switches circuit of the load without any damage to the
Topologies semiconductors (assuming they were sized to cope with the
level of current and voltage generated during such a fault
Parameters Half Bridge Push−Pull
condition). This is a direct benefit of the current mode
V(BR)CER 700 V* 1100 V to 1600 V* brought by the inductor in series with the VCC line.
Inrush Current 3 to 4 times Inom** 2 to 3 times Inom** However, the imbalance in both the power transistors and
tsi window 2.60 μs −3.60 μs 1.90 μs −2.30 μs the magnetic circuit leads to high voltage spikes that make
Drive High & Low side Low side only this topology difficult to use for line voltage above 120 V.
Intrinsic Galvanic no yes
Additionally, it is not practical to dim the fluorescent tubes
Isolation
when they are driven from a push−pull circuit, the half
Notes:* numbers are typical for operation on a 230 V line. bridge, series resonant topology being a far better solution.
** Inom: current into the transistors in steady state. The push−pull converter can be designed with either one
single transformer, as shown in Figure 6, or by using a
separate core to build the oscillator (see Figure 7).
T1 Q1 T1
Q1
T2
Np Np
VCC VCC Nb
Nb
Np Np
LOAD LOAD
Q2
R1 Q2
Nb
VFB
Nb
Figure 6. Basic Single Transformer Circuit Figure 7. Basic Two Transformer Circuit
Single Transformer Basic Operation saturation of the core when the magnetic flux exceeds the
The circuit uses the same core to drive the transistors and maximum value the core can sustain. Although this is a very
to supply the power to the load. Operation is based on the low cost solution, it is not commonly used for power above
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T1
Q1
C1
VCC
R2 Nb
C3 Nb
IC
C2
Q1 100 nF
R2 Itube 400 V
R1
330 kΩ
D2
1N4937
C5 INPUT C6
D1 T1
RECTIFIER
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voltage VBB is negative for the upper switch and positive for Out of resonance, the impedance of the RLC series circuit
the lower one. This forward biases Q2 and the Collector is given by Equation 11:
Ǹƪ
current of this transistor keeps rising until the core of T1
saturates . Z + R2 ) ǒLw Cw
Ǔƫ
1 2 (11)
From electromagnetic circuit theory, the magnitude of the
current in the secondaries of T1 is given by Equation 4: At resonance, the Lω term equals the 1/Cω and cancel
Np each other:
IB + IC * (4)
Ns 1
Lw + (12)
Of course, the value of IB must be large enough to fully Cw
saturate the transistor, even under worst case conditions: Therefore, the impedance is minimum and equals the DC
I (5) resistance:
IB w C Z = ΣR (13)
b
with β = intrinsic current gain of the transistor At resonance, the current in the circuit is maximum and
On the other hand, the VBB voltage developed across the follows Ohm’s law:
secondaries must be limited to a value lower than the
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VCC ΣR Lp Itube
I + (14)
SR
At the same time, the voltage across the capacitor is
maximum as stated by Equation 15:
VC = VCC*Q (15) HALF FLUORESCENT
VPP BRIDGE TUBE Von
The behavior of an R/L/C resonant circuit is depicted by
Figure 12 Depending upon the L/R ratio, the curve is more
or less flattened. This is described as the selectivity of the
R/L/C network. Pout = Von*Itube
L low
Z(Ω) R Figure 13. Basic Equivalent Circuit in Steady−State
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IB1 COLLECTOR
H = 5 μs/DIV
STORAGE TIME CURRENT
V = 500 mA/DIV
tsi
ZERO
H = 5 μs/DIV
V = 100 mA/DIV
IB2
Figure 15. Typical Base Current Waveform Figure 16. Typical IC Waveform
Therefore, the practical operating frequency will be The factor 2 stands for the half bridge topology used.
dependent upon the core used to build the saturable The design of a saturable transformer is bounded by
transformer T1, and the absolute value of the Collector several parameters:
current storage time (tsi). This is shown by Equation 17: a. Magnetic material availability
F + 1 ) 1 (17) b. Core shapes available (Toroids are preferred because
T 2 * tsi they have the highest μr and square BH characteristic)
c. Manufacturing costs
with T = period depending upon core T1
: tsi = storage time
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The typical B/H curves given in Figure 17 are provided by to saturate the core because, in this case, the current will be
the manufacturers of cores for the different material they much higher than the expected one. On the other hand, it’s not
may propose in their portfolio of products. Most of the time, very easy to anticipate all of the tolerance at this point of the
the data sheets show the upper side of the curves, the design; therefore, as a rule of thumb, the first pass can be
characteristic being absolutely symmetrical on the X axis. made by using IP/2 to compute the oscillator.
On the other hand, the shape of the curve, i.e. the Bsat From the toroid data book provided by LCC, let us try the
value, can be controlled by using an air gap to increase the FT6.3 toroid (external diameter = 6.30 mm) with IP = half
reluctance of the core. Of course, this is not possible for the IC peak:
toroidal cores. IE * HS
NP +
IP
B 1.60 * 0.40
NP +
0.35
NP + 1.82 turn
NON SATURABLE MATERIAL: Using the next available toroid, a FT10 (external diameter
MAINLY USED TO BUILD = 10 mm)
OUTPUT TRANSFORMERS. 2.50 * 0.40
H NP +
0.35
NP + 2.85 turns
SATURABLE MATERIAL, WITH A
SQUARE B/H CHARACTERISTIC, The selection of a core from the ‘off the shelf’ standard
USEFUL TO BUILD OSCILLATORS. products (see the preferred models given in Table 2, depends
upon the expected frequency, the cost, and the availability.
Note:Drawing is not to scale. As an example, let us select the T10 toroid with the A4
ferrite material, the μr being higher than 6000. To simplify
Figure 17. Typical B/H Curves
the manufacture of this transformer we will make a first
iteration with NP = 3 turns, assuming VP = 1 V across the
To build the transformer, one can either use the data
primary.
provided by the manufacturers of the cores, using the
The characteristic curves of this core show that the
B=f(H) curves, or pre−define the type of core that would best
saturation flux is 510 mT at room temperature (T = +25°C),
fit the application.
the cross sectional area being 0.08 cm2.
This can be derived from Equation 18, which gives the
These parameters yield a theoretical operating frequency
minimum electromagnetic field needed to saturate a given
of:
core:
1 * 104
NP * IP F +
HS + (18) 4 * 3 * 0.51 * 0.08
IE
F + 20424 Hz
with HS = saturation field in A/cm Using, as a first analysis, a storage time of 5.5 μs for the
: NP = number of turns on the primary
IP = current into NP power transistors, as given by the data sheet, the practical
IE = effective core perimeter in cm ON time (ton) per switch will be:
ton + 1 ) 5.5 * 106
Since HS must be higher than HO (the intrinsic field 2 * 20424
sustainable by the material as defined by the data sheet), then
ton = 29.98 μs
one can compute the perimeter of the core, assuming a given
number of turns, by rearranging Equation 8: yielding a typical operating frequency of:
NP * IP
IE + (18a) F = 1/(2*ton)
HS
Of course, in order to end up with lower cost, it’s F = 1/(2*29.98*10−6) = 16677 Hz
preferable to use a standard core and to run several iterations This is below the expected operating frequency as
of the above equation, using NP as a variable. specified above.
Since the current keeps increasing during the storage time Performing the same analysis with the FT6.3 toroid yields
of the transistor, one cannot use the calculated IC peak value a typical operating frequency of 53 kHz, with NP = 2 turns,
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a value well within the expected range. This toroid will be For a 220 V nominal line, this yields:
the final choice for this design.
V(BR)CEO u 230 * 1.15 * Ǹ2 (The 1.15 factor stands for
the normalized
V(BR)CEO > 374 V European line variation).
Table 2.Popular Available Toroids
Since such a value is not available as a standard device, it
Ext. Dia. IE A is recommended that the designer use a 400 V rated
Toroid mm cm cm2
transistor.
FT6.3 6.30 1.60 0.032 It is worthwhile to point out that, assuming the
FT10 10.00 2.50 0.08 freewheeling diodes are properly selected (fast or ultra−fast
FT16 16 4.00 0.20
type), the voltage across Collector−Emitter junction of each
transistor shall not exceed the VCC supply, limiting the
RBSOA(2) operation within this voltage limit.
However, a simple low cost converter doesn’t provide a
Based on Equation 17, it’s clear that the storage time (tsi) well regulated VCC supply and, under transient conditions,
of the power transistors plays a significant role in defining the DC voltage can rise well above the expected maximum
the electronic lamp ballast. This dynamic parameter has two value. Depending upon the input network, the VCC can be as
main impacts on the design: high as 600 V, yielding unexpected stresses into the
a. operating frequency of the converter, hence the semiconductors. Consequently, the power transistors must
power delivered to the load as derived from be sized to sustain the high FBSOA(3) and RBSOA
Equations 1 and 3, will not be constant from one generated by this VCC transient.
module to another. Fortunately, as stated above, the Base−Emitter network is
b. the output inductor (L) can be driven with other than a not open and, due to its low impedance during these
50% Duty Cycle, yielding a risk of saturating the core. transients, the transistors have a breakdown voltage
The capacitive side of the half bridge helps to prevent the capability extended to the V(BR)CER(4) or V(BR)CES(5)
saturation of the inductor if the D.C. is not 50% (point −b−). region. Figure 18 gives the typical voltage capability of a
The mid point can float around half the VCC value, but modern high voltage transistor, as a function of the
cannot compensate for the large variations one will have by Base−Emitter impedance.
using transistors not specifically designed for this circuit. Curves show the typical values for a BUL44 product at
On the other hand, some low cost designs use a single Tcase = +25°C.
capacitor to close the loop, yielding a high risk of saturation
which, in turn, can lead to the destruction of the power 1000
switches by the resulting current under fault conditions.
Point (a) is worse for low power modules, particularly 900
when the line voltage is 120 V, because even a small
800
variation in frequency can either over or under drive the
BVCER (VOLTS)
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few hundredths of a millisecond, there is no need to select Table 4.Preferred MOSFET Devices for
a transistor with this inrush current value as a nominal IC Lamp Ballast Applications
capability. The designer will preferably use the steady state
Devices V(BR)DSS RDS(on) Package
condition to define the power semiconductor.
In steady state, the rms current into the lamp will be: MTD3N25E 250 V 2.00 Ω DPAK
MTD5N25E 250 V 1.10 Ω DPAK
Irms = Pout/Von
MTD1N50E 500 V 8.50 Ω DPAK
Irms = 55/100 = 550 mA MTD2N60E 600 V 3.80 Ω DPAK
The peak current is: MTP3N50 500 V 3.00 Ω TO−220
IP + Irms * Ǹ2 MTP6N60E 600 V 1.20 Ω TO−220
MTP8N50 500 V 0.80 Ω TO−220
IP + 550 * Ǹ2 + 770 mA
During the start up, the Is current will be (assuming Q = 3):
IS = IP*Q Based on the BUL44D2 data sheet, we will set the forced
IS = 0.77*3 = 2.31 A gain (βf) at 5 as a reference value in steady state. With a
collector current of 800 mA, this βf yields a Base current of
The selected transistor must have an operating current
160 mA minimum. The freewheeling diodes will be the
between 0.80 A and 1.00 A, and must be able to sustain a peak
MUR150, an UltraFast rectifier.
value in the 2.50 A to 3.00 A range, the HFE being high
The Base drive of the transistors can be achieved under
enough to saturate the transistor even during the start up.
one of two modes:
To keep the Base drive simple, and to minimize the ON
losses, the HFE at 0.80 A must be as high as possible. On the a. current source
other hand, one must remember the influence of this b. voltage source
parameter on the dynamic behavior of any bipolar power Using a current source is a straightforward solution
transistor, and make compromises accordingly. (Figure 19a): the saturable transformer T1 is designed to
As this point, we can make a pre−selection among the lamp yield the Base current, according to Equation 20:
ballast dedicated transistors developed by ON Semiconductor. NP*IP = NS*IS (20)
From the preferred devices listed in Table 3, we’ll select the Since the values of IP, IS and NP are already defined, one
BUL44D2, at a 1 A nominal operating current, for this design. can compute the number of turns for each of the secondaries:
IP
Table 3.Preferred Bipolar Power Devices for NS + NP *
Lamp Ballast Applications IS
IC IC
Devices V(BR)CEO V(BR)CES Nom Peak Package 800
NS + 2 * + 10 turns
160
BUL35 250 V 400 V 2A 4A TO−220
BUL43B 350 V 650 V 1A 2A TO−220 It must be pointed out that such a circuit will keep the
BUD43B 350 V 650 V 1A 2A TO−220 forced gain at the value defined by the designer (in this case
BUL44 400 V 700 V 1A 2A TO−220 βf = 5), whatever the Collector current may be. Therefore,
BUL44D2 400 V 700 V 1A 2A TO−220 as already stated, one must make sure that the transistor has
BUD44D2 400 V 700 V 1A 2A DPAK
BUL45 400 V 700 V 2A 4A TO−220
an intrinsic hFE higher than the βf, even under the high
BUL146 400 V 700 V 3A 5A TO−220 start−up current condition. On the other hand, it is difficult
BUL147 400 V 700 V 4A 6A TO−220 to improve the dynamic behavior of the transistor when the
MJE18002 450 V 1000 V 1A 2A TO−220 Base is driven from such a simple current source. A voltage
MJE18002D2 450 V 1000 V 1A 2A TO−220 mode will be preferred to improve the global efficiency.
MJE18004 450 V 1000 V 2A 4A TO−220
MJE18004D2 450 V 1000 V 2A 4A TO−220
Driving the device from a voltage source is achieved by
MJE18006 450 V 1000 V 3A 5A TO−220 using a capacitor to load the secondary, the Base having been
MJE18204 500 V 1200 V 2A 4A TO−220 fed through a series resistor as depicted in Figure 19b.
MJE18604D2 800 V 1600 V 1A 3A TO−220
MJE18605D2 800 V 1600 V 2A 4A TO−220
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The windings are derived from the general Equation 21 This value is well below the minimum guaranteed
used for transformers: V(BR)EBO, so we can round it up to 5.0 V to design the
VP V transformer:
+ BB (21)
NP NS VBB
NB + NP *
The value of VBB is bound on the high end by the VP
Base/Emitter breakdown voltage, and by the amount of
NB = 10 turns
feedback, associated to the VBE(on), in the Base/Emitter
network on the low end. The wire diameter can be derived from the maximum
Assuming a VBE(on) of 1.10 V max and a 1.0 V drop in the current density of 4.50 A/mm2, or can be selected from the
Emitter resistor (VEE), the VBB value must be within the table given in the appendix.
limits given here below: The main advantage associated with voltage mode control
RB*IB + VBE(on) + VEE < VBB < V(BR)EBO (22) is the capability to design a more efficient Base drive, thus
The value of RB must be as small as possible to minimize improving the switching performance of the transistors.
the losses in the drive network, but must be high enough to This is particularly useful for high power converters where
provide a feedback for the oscillator. A simple rule for the losses in the silicon must be minimized.
selecting this resistor is to make it higher than the apparent
dynamic impedance of the Base input:
VBE(on)
ZB + (23)
IB
then: ZB = 1.10/0.18 = 6 Ω
Let us select RB = 15 Ω, then:
VBB ≥ 15*0.18+1.10+1
VBB ≥ 4.80 V
IB Rb
Rb Q1
Q1
Nb Cb Ri VBT
Nb VBB Re
Re VEE
VEE
Figure 19. (a) Typical Current Mode Drive Figure 19.(b) Typical Voltage Mode Drive Circuit
At this point, the oscillator is nearly completed, but it will This represents the impedance of the R/L/C circuit,
be necessary to refine the design based on the first results according to Equation 11 given on Page 7. Depending upon
coming from the prototype. the values of L and C, assuming the DC resistance R is
As already stated, the steady state current in the negligible and the operating frequency is nominal, the
fluorescent tube is limited by the external inductance, LP. current waveform will be truncated at either the peak value
The value of LP is derived from the impedance one must set of the sine (worst case) or during the negative going slope.
in series with the lamp to get the right output power: Obviously, in the second case, the turn off switching losses
VCC Von will be lower. The dynamic behavior of the transistor must
Z + (24) be stable to make sure that the frequency stays within the
2 * IP
310 100 predicted limits. Consequently, the power semiconductors
Z + + 300 W
2 * 0.35
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must have a tightly specified, low dispersion of the storage T1. As a rule of thumb, the time constant shall be 5% of the
time from lot to lot . ON time, in our case around 500 ns, yielding C1 = 22 nF.
Since C3 and C4 are assumed to have a negligible
impedance, we can use Z to derive LP: Freewheeling Diodes
Across Q1 and Q2 are the freewheeling diodes D2 and D3.
Z By providing a path for the inductive current, these devices
LP + (25)
2*p*F clamp the spike voltage, as stated by the Lenz’s law, to VCC
+ VF and −VF when Q1 or Q2 switches off. Of course, since
300 the dV/dt can be pretty high, D2 and D3 must have a fast
LP + + 1.60 mH
2 * p * 30000 turn−on time to make sure that the peak voltage will be
On top of limiting the current in steady state, the clamped to a safe value. On the other hand, if these diodes
inductance, associated to the capacitor CP, builds the are not used, then the negative going current flows into the
resonant circuit during the start−up sequence. Prior to Collector/Base junction of Q1/Q2, yielding uncontrolled
computing the value CP, one must make two assumptions: charges. Moreover, if the voltage drop across the B/E
a. The storage time will be shorter during start−up, as a network is higher than the V(BR)EBO, the Base/Emitter
consequence of lower hFE at high current. junction will be avalanched and the associated current will
b. The toroid will saturate more rapidly due to the higher generate extra losses into the silicon as stated by Equation
dl/dt. 27:
Consequently, the operating frequency will be higher, and PB = V(BR)EBO*IA*dt*F (27)
the resonant network computed accordingly. Assuming that
The worst case condition will occur when Q2 switches off.
the start−up frequency is 60 kHz, then the value of CP can be
When the voltage at node A (see Figure 6) is negative and
derived by rearranging Equation 8:
the B/E network time constant large enough, the
CP + 1 (26) Base/Emitter junction of the top transistor can be forward
4 * p2 * F2 * LP biased and a short circuit may be generated through Q1/Q2.
1 This instantaneous power can be much higher than the
CP + + 4.39 nF
4 * p2 * 600002 * 1.6 * 103 transistors can sustain (the FBSOA characteristic) and both
transistors can be destroyed in a few microseconds.
This value not being standard, we will use 4.7 nF/1000 V.
To avoid the risks described above, it is highly
The resonant frequency is then:
recommended that designers use the freewheeling diodes
F + 1 + 58 kHz across each transistor.
2 * p * Ǹ(1.6 * 103 * 4.7 * 109)
The capacitors C3 and C4, used to build the passive side Safety Circuit
of the half−bridge, associated with LP, must yield a resonant EEC and UL regulations not withstanding, once the
frequency well below the one used in steady state. converter is running in steady state, the safety circuit can be
Let us make fo′ < 5*F, then limited to a single fuse to switch off the line if an overload
occurs. A more sophisticated, but much more expensive
C+ 1
way, is to use a self resetting thermal switch to open the DC
4 * p2 * foȀ2 * LP
line if the temperature inside the module becomes higher
From an AC point of view, C3 and C4 are in parallel, thus than a safe limit, usually between 85°C to 100°C.
C = C3+C4: However, during the start−up sequence, one must make
C+ 1 + 4.39 nF sure that the fluorescent tube turns on, otherwise the
4 * p2 * 60000 * 1.6 * 103 converter can be damaged by continuously operating in the
We will use the closest normalized value for C3 and C4: resonant mode. As stated on Page 7, the current can be very
C3 = C4 = C/2 = 220 nF high and the losses in the silicon will rapidly exceed the
maximum ratings of the power transistors used in the
The start−up network, built around R1/C1/D1/R4, must
converter. Of course, a delay must be provided to yield
perform two main functions:
enough time to warm up the filaments and trigger the tube.
a. Provide enough Base current to Q1 to turn on the Basically, the self oscillant circuit is turned off by
transistor. grounding the Base drive of the bottom transistor. This is
b. Minimize the losses into this circuit. accomplished by using an SCR, or a small signal transistor,
To minimize the losses, let R1 = 330 kΩ , yielding 330 to sink the Base current to ground as depicted in Figure 20.
mW by Joule’s effect into this resistor. The Base drive can also be disconnected by using an extra
The Base current is given by the discharge of capacitor C1 winding across the drive transformer (T1, Figure 11), the
into the Base/Emitter network. Since this is a low impedance SCR shunting all of the available current to ground: this
circuit, the capacitor C1 must be sized to yield a pulse width technique switches off both Q1 and Q2 and the SCR can
large enough to get a significant current into the primary of
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AN1543/D
memorize the failure mode until the user switches off the Another way is to open the Emitter to Ground path of the
mains (see Figure 21). bottom transistor as depicted in Figure 22, but this is
relatively complex and not cost effective.
Q1 Cp Q1
Cp
Lp I > IH Lp
TUBE
TUBE
Q2
R1 Q2
D1 R1
Q3 Q3 D1
R3 R2 C1 R2 R3 C1
DIAGNOSTIC CIRCUIT
DIAGNOSTIC CIRCUIT
Figure 20. Turning Off the Converter by Sinking Figure 21. Fault Memorization
the Base Current to Ground
Q1
Cp
Lp
Q2 TUBE
+VCC
R1
D1
Q3
R3 R2 C1
DIAGNOSTIC CIRCUIT
Power Factor Correction circuit built around a boost converter. The passive Power
All electronic lamp ballasts use a large bulk reservoir Factor Correction (PFC) is economical, but bulky (because
capacitor associated with a bridge rectifier, and therefore, it operates at line frequency) and not very efficient with a
can only draw power from the line when the instantaneous typical cosΦ of 0.80.
AC voltage exceeds the charge on the capacitor. As a result, Using an active PFC brings, in addition to a high cosΦ and
the power factor is low (cosΦ around 0.50) and the harmonic low THD, a constant DC voltage across the electronic ballast
content of the input current is very high. The European which yields a constant power to the load, regardless of the
regulation EEC555−2 specifies both the minimum expected line voltage. For example, let us point out that the European
cosΦ value and the maximum harmonic content curve line voltage ranges from 185 V to 265 V, this is a ±15%
acceptable for any kind of electronic circuit connected to the variation from the nominal values. This can cause a change
AC mains. To cope with this regulation, one can use either in light intensity large enough to be sensed by the human
a passive network (basically a large inductor together with eye.
a combination of rectifiers and capacitors) or an active
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Circuit Description takes care of the 50 Hz signal and controls the MOSFET to
The proposed PFC circuit is based on the MC34262, a make the envelope of the high frequency pulsed current as
dedicated IC, together with a power switch, in this case a close as possible to the 50 Hz sinusoidal waveform. On the
MOSFET, arranged in a boost topology. Of course, the other hand, the output DC voltage is regulated (sensing is
rectified voltage is no longer filtered by a large capacitor, the achieved through pin 1) and the current flowing into the
filter having been designed to damp the high frequency power switch is monitored across the sense resistor
noise from the line (see typical schematic diagram in connected between Source/Ground of Q1.
Figure 23).
This circuit feeds the lamp ballast converter and recharges
the reservoir capacitor (i.e., C6, Figure 11). The MC34262
100 kΩ 1N4937
MUR150E
+400 V
4 x 1N4007 100 nF
22 kΩ
1.2 MΩ
630 V
330 μF
1.8 MΩ
4.7 Ω 8 5
7 MTP4N50E
22 μF
3
MC34262 450 V
4
MAINS 6 2 1 12 kΩ
185 V − 265 V 10 nF 12 kΩ 1 μF 1.2 Ω
A %H
1 30
10
7
0.5 6
IEC555-2 SPECIFICATION
5
0 ω 4
60 120 180 240 300 360 3
2
1
10 20 30 40
LINE INPUT CURRENT HARMONIC
TOTAL HARMONIC DISTORTION
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C9
R3 2.2 nF
100 k/1 W T2 D2
MUR180E C13
D1 R9 Q2 100 nF
MUR120 330 k BUL44D2 250 V
R2 R8 R11 Ptube = 55 W
R4 1k
1.2 M 22 k T1b C6 4.7 R
C2 + R7 10 nF R13
330 μF 1.8 M D3 2.2 R
25 V 1N4007
R18
3 PTC
8 5 R10 L1
Q1 10 R 1.6 mH C11
3 7 AGND 2 MTP4N50E C4 +
U1 47 μF 4.7 nF
MC34262 1 450 V D4 T1a 1200 V
D3 D3 DIAC R16
1 6 2 4 FT063 1M C12
1N4148 1N4148
C8 22 nF
C3 2.2 nF
R1 C1 D3 D3 T1d
12 k 10 nF 1 μF R5 R6 1N4148 1N4148
1R 1R Q2
P1 BUL44D2
20 k D5
R12 ZENER 10 V
C7 4.7 R C14
C5 Q4 T1c R14
10 nF C10 R17 100 nF
0.22 μF MCR26 2.2 R 10 k 250 V
17
R15 470 nF
100 R
AN1543/D
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Notes: * all resistors are ± 5%, 0.25 W unless otherwise noted. AGND
FUSE * all capacitors are Polycarbonate, 63 V, ±10%, unless otherwise noted.
D7 D8
C17
LINE 47 nF C15
220 V 630 V 100 nF
FILTER C16
47 nF
D6 630 V D9
The performance is outstanding, with a cosΦ = 0.98 and constant DC voltage. The circuit uses the newly developed
a Total Harmonic Distortion (THD) well within the BUL44D2 transistors in a standard self oscillant
EEC555−2 regulations. configuration. The performance is summarized below, and
The MC34262 data sheet and the associated Technical the parts list and printed circuit board layout are available in
Notes give all the information required to design a PFC the appendix.
loaded by a lamp ballast or any other type of electronic
circuit. Table 5.Test Results
In order to make sure that the PFC will not be damaged Nominal Operating Frequency: 40 kHz
during the start−up sequence of the lamp ballast, the time
constant of R1/C1 delays the operation of the MC34262 Nominal Output Power: 55 W
about three seconds, thus yielding a safe amount of time to Power Transistors Case 65°C (steady
operate both circuits. Of course, the DC voltage will not be state, free air)
constant during the start−up, but this is irrelevant since the Temperature:
converter is not yet running in steady state. CosΦ: 0.98
The demo board, designed by ON Semiconductor,
includes a PFC circuit which drives the converter with a Global Efficiency: 85%
2
5 μs
10 mV
1
IC = 500 mA/DIV
1
5 μs
10 mV
2
IB = 100 mA/DIV
5 μs
1 10 mV 50 Ω 200 MS/s
2 10 mV 50 Ω
1 DC 9 mV
j STOPPED
LINE = 230 V LOAD = 58 W
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3
.1 μs
100 V LOSSES = IC*VCE
VCE = 100 V/DIV
A 1*3
.1 μs
6 V2
1
.1 μs
10 mV
IC = 200 mA/DIV
.1 μs
1 10 mV 50 Ω
2 10 mV 50 Ω 500 MS/s
3 1 V DC x 100 1 DC 7.4 mV
j STOPPED
4 .2 V DC x 10
Figure 27. Switching Losses
4 VCE = 1 V/DIV
2 μs
1V
DYNAMIC VCE(sat)
4
VIRTUAL VCE(zero)
1
2 μs 1
10 mV
IC = 500 mA/DIV
2 μs
1 10 mV 50 Ω
2 10 mV 50 Ω 500 MS/s
3 50 mV DC x 100 1 DC -5.4 mV
j STOPPED
4 .1 V DC x 10
Measuring the dynamic VCE(sat), under high VCE value, is recover from the +400 V coming from the rail voltage,
not straight forward because the input amplifier of the within less than 10 to 20 μs.
oscilloscope becomes saturated by the large VCE voltage Several techniques exist to overcome this problem. The
and cannot accurately sense the low saturation value when one used by ON Semiconductor is depicted in Figure 29.
the transistor turns on.
For example, setting the oscilloscope to 500 mV/div will
yield meaningless results because the instrument will not
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VCE
+VCC
LOAD
VCES(dyn1) R1 +Vaux
D1
Q1
VCES(dyn2) t
1 μs
3 μs
VCE(sat)dyn DEFINITION MEASUREMENT TECHNIQUE
Diode D1 must sustain the peak voltage developed across There are three main keys to solving this problem:
the device under test (Q1). D1 must also have a very fast a. Use standard Bipolar transistors with a Baker clamp
turn−on time. The Vaux value is adjusted between 10 to 20 network.
V (depending upon the expected VCE(sat)dyn), and the VF of b. Use high voltage MOSFETs.
diode D1 is calibrated at the current forced by resistor R1 c. Use the newly developed H2BIP transistors.
(usually IF = 10 mA). Using the Baker clamp technique is straight forward, as
The VCE(sat)dyn is then calculated by subtracting the shown by the schematic diagram given in Figure 30, but
forward drop (VF) from the voltage sensed by the there are some drawbacks:
oscilloscope.
The accuracy of this method is good enough to
• the designer must use at least three fast diodes (two low
voltage, one high voltage).
characterize and compare the behavior of several transistors.
Additionally, to make this test reproducible, the dynamic • the ON voltage of the power transistor is no longer the
VCE(sat) is specified under two timing conditions (see Figure VCE(sat), but increases up to VCE(sat) + VBE(on), yielding
29): one microsecond and three microseconds after IB1 much higher ON losses than those generated with a
reaches 90% of its end value. standard circuit.
For example, the nominal VCE(sat) for a BUL44 is
HIGH END DIMMABLE LAMP BALLAST 0.20 V, @ IC = 1 A, but the ON voltage rises up to 1.0
Since a voltage across the fluorescent tube lower than the V when the device is driven with a Baker clamp. It’s
Von value would cause the tube to turn off, it’s not practical clear that with five times more power dissipated in
to use the variations of VCC to adjust the output power. In steady state, a heatsink is mandatory to cool the
fact, using this basic technique yields a limited span of the transistor.
dimming effect for the light output of the lamp. • the diodes associated with this solution are not free and
On the other hand, one can use Pulse Width Modulation they occupy space on the printed circuit board.
(PWM) of the current through the tube to dim the light, but
care must be taken to balance the magnetic circuit. COLLECTOR
Another simple, but efficient solution, is to use a variable
frequency (with a constant 50% duty cycle) to drive the D3
converter, keeping the series inductance constant.
Since the impedance of the output network is a function Q1
D1
of the frequency (Equation 1), the power can be adjusted BASE VCE(sat)
from zero to 100% using this technique.
As already stated, the storage time associated with the D2
bipolar transistor is a key parameter for the electronic lamp
ballasts. In the case of the dimmable circuits, this parameter
is even more important because it will offset the operating VBE(on)
frequency by a variable amount. Moreover, since the current
EMITTER
varies as the output power is adjusted, the transistor bias
varies as well and the Base drive must be designed to Figure 30. Typical Baker Clamp Circuit
automatically compensate these variations.
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Although this solution is sometimes used, it’s not the The oscillator is built with the VCO integrated into U1 to
preferred one to build a dimmable lamp ballast. make this module dimmable with a voltage source. The
The MOSFETs solve all the problems associated with the flip−flop U2 provides two out of phase signals to drive the
storage time, even when the operating Drain current varies Mosfet Q1 and Q2 which, in turn, control the power stage
over a wide range, but the ON losses can be a limiting factor. Q3/Q4. Transistors Q5 and Q6, respectively connected
The RDS(on) of a MOSFET increases when the breakdown across Gate/Source of Q3/Q4, provide a low impedance path
voltage V(BR)DSS increases (for a given chip size). The only to rapidly discharge the input capacitance of the high voltage
way to reduce RDS(on) is to increase the die size, but this also devices, avoiding the risk associated with poor drive
increases the cost, thus limiting the use of MOSFETs to high conditions, particularly when the converter operates at high
end applications. Additionally, care must be taken to protect frequency.
the Gate/Source from voltage spikes over ± 20 V. The results of the tests performed in Toulouse are
The H2BIP* device integrates an active anti−sat network summarized in Table 6.
into the die of a Bipolar power transistor, together with an
antiparallel diode connected across the Collector/Emitter. Table 6.Dimmable Lamp Ballast Test Results
The basic concept is twofold:
Pout min 15 W
a. Avoid the hard saturation, thus making the storage time Pout max 65 W
as short as possible. Fmin 22 kHz
b. Avoid the storage time variation whatever the Fmax 170 kHz
operating Collector current is, assuming that the CosΦ 0.60 (without PFC network)
intrinsic hFE is higher than the forced IC/IB. MTP8N50E 0.98 (with MC33262based PFC)
Of course, the tsi cannot be zero, but it is small enough to TC = 40°C (steady state, in free air)
make this new technology a good choice to design an
electronic lamp ballast. The time delays built with R3/CissQ1, R4/CissQ2 and
Also, the ON voltage is very close to the VCE(sat) (no more R5/CissQ3 , R6/CissQ4, make sure that none of these circuits
than 100 mV are needed to activate the anti−saturation will have a cross conduction during the nominal operation.
network), keeping the associated losses to a minimum, and For these reasons, one cannot use bipolar devices for Q1 and
the devices can sustain the high voltage needed in these Q2.
applications. The design of the series inductance L1 and resonant
• H2BIP: see new product paragraph. capacitor C2 is straightforward as already described for the
self oscillant circuit. The transformer T1 is built on a
Circuit Analysis T1600A toroid (external diameter 16 mm), the primary
To adjust the output power of the fluorescent tube inductance being 1 mH. Assuming AL = 1600, the primary
described in the half bridge design example, we will vary the and secondary windings are 25 turns each.
frequency from 20 kHz to 180 kHz. Of course, the circuit can
no longer be self oscillant and we’ll use an oscillator to drive
the power stage as shown in Figure 31.
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+15 V +15 V +15 V
R5 D5
1N4148 C3
R8 + 100 R 3 100 nF
1k C8 Q3 250 V
C17 100 nF C9 + C10 2 MTP8N50E
4.7 μF 100 nF 100 μF
R7 16 V 16 V R11 1
15 k T1b
1k Q5 L1
D1 BC557C 1 mH
D3 3 C5
1N4148 TP2 R3 C2
16 AGND Q1 220 nF
6 2.2 k 2 MPF960 630 pF
4 6 T1a R6 D6 1200 V
AGND 1 FT1603A 1N4148
C1 3 S 1 100 R 3
R1
470 pF U1
C U2 Q
TP3
D2 7 11 8.2 k Q4
MC14046 MC14013 2 MTP8N50E
P1 1N4148 9 12 5 2
D Q 3
22 k R R4 T1c R12 1
5 R2 Q2 C6 1k Q6
150 k 4 2.2 k 2 MPF960 BC557C
220 nF
TP1 8 1
C14 C4
100 nF 100 nF
250 V
22
R9
AGND
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10 l/2 W
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FUSE R13 R10
D7 D8 47 R/2 W 330 k
+15 V
Q5
D4 MC7815
T2 BRIDGE 100 V/1 A
15 V-3.5 VA
IN OUT
GROUND
+ C11 + C7
100 μF 100 μF
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3
2 μs
200 V
VDS = 200 V/DIV
3
4
2 μs
5V
1 ID = 200 mA/DIV
2 μs 1
10 mV
VGS = 5 V/DIV
4
2 μs
1 10 mV 50 Ω
2 10 mV 50 Ω 500 MS/s
3 2 V DC x 100 1 DC 2.6 mV
j STOPPED
4 .5 V DC x 10
Figure 32. Drain Current and Gate Voltage in Steady State at Pout = Pmax
3
2 μs
200 V
VDS = 200 V/DIV
3
4
2 μs
5V
1 ID = 200 mA/DIV
2 μs 1
10 mV
VGS = 5 V/DIV
4
2 μs
1 10 mV 50 Ω
2 10 mV 50 Ω 500 MS/s
3 2 V DC x 100 1 DC 2.6 mV
j STOPPED
4 .5 V DC x 10
Figure 33. . Drain Current and Gate Voltage in Steady State at Pout = Pmin
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tsi Re = 0 Ω
tsi ( μs)
5
INTEGRATION OF EMITTER FEEDBACK Re
4
tsi Re = 1.2 Ω
Rb
3
0 20 40 60 80 100 120
TC = °C
Figure 36. tsi = f (TC) at IC = Constant
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C2
Q1
100 nF
D4 GATE DRIVE NETWORK 400 V
1N4148
R1
C5 INPUT 330 kΩ
RECTIFIER
D3 Q3
R2
BC557
LINE D2 Cp C3
FILTER 100 nF
C6
Lp
400 V
C4 Q2
D6
1N4148
LINE
220 V
C1 FLUORESCENT
22 nF TUBE
Q4
D5 R3
BC557
D1 R4
DIAC 32 V 10 Ω
This circuit works fine, but the four extra components for This device can be driven from any network. The turn off
each power MOSFET (Q3/D3/D4/R2 for Q1 and time is independent of the impedance connected Gate to
Q5/D5/D6/R3 for Q2) take up significant space on the pcb, Source, the value of resistor R1 being large enough to keep
the total cost is not negligible and, more over, using standard the steady state Igs current below 100 μA. The ZPCMOS
transistors for Q3 and Q4 can lead to uncontrolled operation can be used in existing circuits, assuming that the electrical
of the module as a consequence of the very large gain parameters are compatible, as a drop−in replacement
dispersion of these parts. solution to improve the overall efficiency of a given
By using an existing process called Smart Discrete™, ON application. Figure 41 demonstrates the net savings, in terms
Semiconductor has integrated this sub circuit into the die of of component counts, brought by the ZPCMOS in a lamp
the MOSFET, making the device driveable from high ballast application.
impedance. This family of products is called ZPCMOS, an
acronym for Zero Power Controlled MOSFET, the basic
Q1 GATE DRIVE NETWORK
internal circuit is shown in Figure 40. ZPCMOS
DRAIN
Q1
GATE D1
Q2
R1 Lp
D2 Q2
Q3 VGS(Q1)
Vin ZPCMOS
D3
V1
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+VCC
+VCC
Q1
R1 Q1
P CHANNEL
D1 Q3
Q2
Vout
D2
DRIVE
NETWORK
Q4
C1 N CHANNEL
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to keep the costs compatible with this market, it is preferable SOT223), or into a single SOIC (assuming that the losses
to leave the power switches outside the IC, the half bridge can be held to a minimum, avoiding the risk of high junction
being built either with two small footprint packages (DPAK, temperature).
+VCC
START−UP
OUTPUT
Q1
Q3
PFC
OSCILLATOR AND
MC33262
GATE DRIVE
The design of a multi chip package is not as A more realistic way is to set the junction temperature at
straightforward as it seems at first. It depends greatly on the +120°C, yielding 400 mW maximum into the silicon under
thermal behavior of the overall system. For example, let the the same ambient conditions. Of course, these losses are
junction to ambient thermal resistance be 150°C/W for a equally dissipated in each of the power devices, assuming
plastic 8 pin SOIC package and the ambient temperature those in the driver are negligible. For compact fluo lamps in
being +60°C. The maximum losses allowable into the the range of 7 W to 15 W, powered from the 220 V line, the
silicon are given by Equation 28: peak current into the switches is around 400 mA and the
TJ Tamb maximum allowable RDS(on) for the MOSFET is given by
Pmax + (28) Equation 29:
Rthja
RDS(on)(max) + P (29)
Under the above conditions, TJ = (150−60)/150 = 600 mW IDRMS2
This value yields a zero safety margin because it assumes In this example, RDS(on) = 0.2/((0.4/√2)2) = 2.50 Ω.
the die is continuously operating at its maximum Obviously, this is the maximum value at TJ = +120°C,
temperature. The transistor lifetime is highly reduced as a yielding a net 1.60 Ω at TJ = +25°C. The die size of a 500 V
result of Arrhenius’s law (the expected life if divided by rated MOSFET will be 150 x 150 mils, a dimension
1000 when the temperature increases from +40° to +150° ). incompatible with the existing low cost 8 pin SOICs.
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The circuit can be either split into two packages (one for Figure 46 gives the typical block diagram for such an
the controller, the second for the power stage), or built inside application.
the same SOIC as depicted by the dotted line in Figure 45. +Vbat +100 V/+400 V HIGH
PRESSURE
−80 V LAMP
FLYBACK
Q1 −80 V
LINE L
Q
CONTROLLER
Q2
IS
Q
+V
C1 C2
R
IGNITION
EMERGING APPLICATION
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FERRITE LAMP even replacing the standard incandescent bulbs designed for
personal use.
+VCC
Nowadays, engineers have access to a broad range of
semiconductors, from which they can select the best device
5 cm to match their applications. Power transistors, either Bipolar
Cp
or MOSFET, are reliable and can run these electronic
Lp modules for more than ten years without failure. New
Q1
technology has only begun to bring more intelligence into
the silicon, at an affordable cost, making the lighting
DRIVER systems more rugged, and with features one cannot even
XTAL imagine with the standard electromechanical ballasts:
dimming, remote control, and real time energy saving, just
RF RESERVED FREQUENCIES:
to name a few.
2.65 MHz 13.56 MHz 27.12 MHz In 1993 the electronic lamp ballast market represented
CLASS D OR E AMPLIFIER
AVAILABLE BAND: 100 kHz-400 kHz. around 50 million Compact Energy Saving lamps, 50
POWER FERRITE MATERIAL AVAILABLE million industrials (two, four and six foot tubes) and 20
UP TO 3 MHz. million low voltage Halogen lamps, numbers which are
LAMP IONIZATION VOLTAGE: 0.6 TO
0.9 V/cm.
expected to more than double within five years. In addition,
Figure 47. Typical Static Induction Discharge new applications are emerging, like the high pressure
Lamp Application discharge lamps for vehicular and the induction lamps.
As a main supplier of semiconductors, our goal is to
CONCLUSIONS develop new products to make sure that any designer in the
Not only does the ELB save a lot of energy, but the world will find the optimum solution to cope with his or her
miniaturization of the electronic ballasts makes them own needs: this is the benefit of the electronic lamp ballasts
suitable for small enclosures. The fluorescent lighting expertise accumulated by ON Semiconductor.
market will continue to grow rapidly during the next decade,
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APPENDIX
1. V(BR)CEO: Collector to Emitter Breakdown Voltage, 3. FBSOA: Forward Bias Safe Operating Area. This
Base open. This is the minimum guarantee value for a parameter specifies the maximum power the transistor
given transistor. Modern power transistors do not have can sustain when it is operating in the Forward Base bias
a wide spread of their electrical parameters and the mode. The FBSOA is dependent upon the power pulse
designer must not rely on some safety margin set by width and cannot be exceeded under any circumstances.
older, non−repetitive, semiconductors. 4. V(BR)CER: Collector to Emitter Breakdown Voltage,
2. RBSOA: Reverse Bias Safe Operating Area. This Base connected to the Emitter via a low impedance.
parameter specifies the maximum energy the transistor 5. V(BR)CES: Collector to Emitter Breakdown Voltage,
can handle when commutating an inductive load. The Base shorted to the Emitter.
RBSOA is a dynamic parameter which is dependent 6. V(BR)CBO: Collector to Base Breakdown Voltage,
upon the Base reverse voltage bias as specified in the ON Emitter open.
Semiconductor designer’s data sheets.
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Current Density Limit: When the frequency increases, the skin effect becomes
An rms current density of 4.50 A/mm2 causes dominant and the resistance increases:
approximately a 30°C temperature increase with natural ò*1
cooling for a transformer or an inductor whose core area RHF +
2*p*r*a
product (AP = Aw*Ae) is 1 cm4. The thickness (a) is given, by Lord Rayleigh’s formula:
With a larger core, the allowable current density decreases
a + 1
because the surface usable to dissipate the heat increases less
2 * p * Ǹ((m * F * 107)ńò)
rapidly than the volume producing the heat:
Jmx = 4.5*AP−0.125 A/mm2
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THICKNESS (A)
d mm μ permeability (1 for copper)
0.1
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IB1
IB
90%
Rload 10%
IC(sense
IB1 ) +
VCC IB2
- IC
td ts
DUT
tr tf
90% 90%
IB2
IB(sense)
IC
IB1 = FORWARD BIAS
IB2 = REVERSE BIAS
10% 10%
BASIC TEST CIRCUIT
NOTE: Waveforms are idealized and not scaled.
Figure 50. Switching Time Definition
Total Components = 54
Notes: * all resistors are 0.25 W, ± 5%, unless otherwise noted
* all capacitors are polycarbonat, 63 V, ±10%, unless otherwise noted
Transformer T1: Core = FT6.3
Ferrite = 4 A
T1A = 1 turn (primary)
T1B = T1C = 5 turns each (secondaries)
Output inductance L1: Core = EF2509
Ferrite = B2 or equivalent (Operating frequency: 150 kHz min)
N = 38 turns, wire dia = 1 mm, preferably Litz type.
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Total Components = 60
Notes: * all resistors are 0.25 W, ± 5%, unless otherwise noted
* all capacitors are polycarbonat, 63 V, ±10%, unless otherwise noted
Transformer T1: Core = FT1600A−M01
Ferrite = A9
T1A = T1B = T1C = 20 turns, wire dia. = 0.2 mm
Output inductance L1: Core = EF2509
Ferrite = B2 or equivalent (Operating frequency: 150 kHz min)
N = 38 turns, wire dia = 1 mm, preferably Litz type.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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