Millimeter-Wave BiST and BiSC using a High-

Definition Sub-Ranged Detector in 90nm CMOS

Sleiman Bou Sleiman1, Amneh Akour1,2, Waleed Khalil2, Mohammed Ismail1,2
Analog VLSI Lab1 and ElectroScience Lab2, ECE Department
The Ohio State University
Columbus, OH
{bousles, akoura, khalil, ismail}@ece.osu.edu

Abstract— A wideband CMOS mm-Wave amplitude detector for

on-chip self-test and calibration is presented. The high-
conversion-gain detector enables accurate on-chip amplitude
measurements and allows for the prediction of key RF
parameters. The detector operates across the 60GHz band and
achieves a dynamic range of 0-0.5V and a sensitivity of -9V/V.
The detector’s practical use in mm-wave Built-in-Self-Test
(BiST) and Built-in-Self-Calibration (BiSC) circuits is
demonstrated using a 60 GHz CMOS LNA. Simulation results
show that the LNA gain, compression point, and intermodulation
distortion are predicted with minimal error. The detector and
LNA are built in IBM’s 90nm CMOS technology.
Fig. 1. Radio transceiver architecture with possible BiST and BiSC
I. INTRODUCTION configurations using loopback.

A dvances in semiconductor technology allowed for the

implementation of high performance RF blocks in
CMOS, opening the doors for a full System-on-Chip
(SoC) solution. More recently, CMOS technology is sought
for the millimeter-Wave (mmW) regime albeit many
challenges and critical shortcomings with respect to SoC
integration. mmW and RF circuits, unlike the more robust
digital circuits, suffer from low yield due to process, power
supply, and temperature (PVT) variations and require several
expensive silicon cycles to meet their specifications.
Additionally, parasitics – more pronounced at mmW than at
RF – quickly come into play and increase the adverse
variability and hence the performance uncertainty of a given
chip. For this reason, the design of mmW/RF IC blocks in
platform baseband SoCs has so far been restricted.
Countering the advantages of decreasing feature size into
the nanometer regime, process variations – even in digital
circuits – are getting more amplified. This necessitates the
need for a new approach to RF and mmW design through
integration of on-chip Built-in-Self-Test (BiST) and Built-in-
Self-Calibration (BiSC) circuits. While highly beneficial in
GHz RF circuits, BiST(SC) have not been widely
implemented as design complexity was contained – by
allowing for overdesign and some area/power sacrifices.
However in mmW and as devices scale down and parasitics
play ever-critical roles, the design complexity becomes very
quickly unbound. Two key components of the new design
paradigm are block/system self-awareness and block/system
programmability. The first component is achieved with
accurate and efficient BiST as a precursor to implementing the
latter by leveraging the more robust digital capabilities of
SoCs. In other words, this is achieved using digitally-assisted
mmW circuits within calibration loops to alleviate mmW
shortcomings (Fig. 1.)
In Section II, we present a compact, non-invasive, and
efficient mmW amplitude detector serving the needs for both
BiST and BiSC. In Section III, we verify our detector using a
60 GHz LNA as circuit-under-test/calibration (CUT/C).
II. DETECTOR DESIGN
A. Detector Requirements
To enable testing and measurements of single blocks or an
aggregate of blocks in a transceiver, multiple detectors can be
inserted to extract the signal amplitudes at different points or
conversely a single detector with switches connecting it to the
various measurement points. Opting for the first configuration,
we need to design area-efficient detectors whereas if targeting
the second, we need to have a very wide dynamic range
detector, as the signal varies considerably along the chain.
Other requirements include low power, wideband operation,
and more importantly high input impedance so as not to load
the circuit it connects to. Another important consideration
when dealing with complete on-chip measurements is the need
for high RF-to- DC conversion gain. A high conversion gain
is very desirable for self-test and self-calibration as it eases the
requirements on the digitizing ADC (see Fig. 1.) However,
with decreasing power supply voltages, an increase in
conversion gain limits the dynamic range. Previous detectors
described in the literature [1]-[7] do not offer high resolution
and most suffer from a low RF-to-DC conversion gain of
around -1V/V (see Fig. 2, [7] uses a 3.3V supply). In the next
section, we present a detector that fulfils the aforementioned
requirements, and to the authors’ best knowledge, the
implementation presented is the first to operate at mm-Wave
frequencies.

978-1-4244-7773-9/10/$26.00 ©2010 IEEE 477

 1.6 In I D0
W
exp
Vbias Va cos( ωt )
I B0 exp
Va cos( ωt )
[6]
Huang L nVT nVT
1.4 [4]
wang
n
DC Output (V)

2
1.2 [8]
Fan Va 1 Va
[7]
Valdes I B0 1 cos( ωt ) cos2 ( ωt ) (2)
nVT 2 nVT
1 [1,2]
Jonsson
0.8 Va
2
Va Va
2

I B0 1 cos( ωt ) cos( 2ωt )

0.6 2 nVT nVT 2 nVT

0.4 where IB0 [=ID0(W/L)nexp(Vbias/nVT)] is the dc-bias current of

0.2 the transistor. Initially charged to VDD, DCout is then
discharged by the drain current In through the NMOS
0
transistor. This creates a negative I-V relationship with respect
0 0.5 1 to an increase in the mmW signal amplitude. As the detector
Input RF Amplitude (V)
output is low-pass filtered by the RC load, it reacts to the dc
Fig. 2. Response of various detectors in literature component of In given by
2
Va
B. Proposed Detector Architecture I nDC I B0 1 (4)
2nVT
Our proposed architecture is shown in Fig. 3. It is an
implementation of an architecture similar to [1], however it A high conversion gain can then be achieved with proper
does not employ a feedback resistor for biasing but depends device sizing and biasing. However, in order to achieve a wide
on a separate gate biasing circuit. The input transistor is biased dynamic (i.e. amplitude) range, the detector should employ
in the subthreshold region and its saturated drain current can several modes of operation each covering an overlapping sub-
be expressed as [9] range of amplitudes. This is achieved by appropriately
W VGS changing the gate biasing of the input NMOS device: by
In I D0 exp (1) decreasing the gate bias, higher amplitude signals are needed
L n nVT
to turn the input transistor on. Using a 3-bit programmable
where ID0 is a current constant independent of gate-to-source
mode select voltage bias circuit, and setting the overlap to
voltage, (W/L)n is the aspect ratio of the NMOS transistor, n is
50mVamp (∆Vbias=35mV), we achieve 8 modes of operation
a process dependent term related to depletion region
covering a wide signal range from 0 to 0.5Vamp. As shown in
characteristics [4], and VT is the thermal voltage.
Fig. 4, the linear region of the response is between 0.2V and
Superimposing a small sinusoidal input voltage, Vacos(ωt) on
1V (for a 1.2V supply) providing a slope of around -9V/V . To
the gate bias, Vbias, the following power series approximation
reduce the loading impact of the detector, its input impedance
of the current equation holds:
is kept greater than 800 Ω across the 60 GHz band. Further,
the detector’s wideband operation is also validated across the
60 GHz band. The complete circuit is built in IBM’s 90nm
1.2 CMOS technology. As test and calibration do not need to run
VDD
1.2 all the time but only intermittently, low power requirements
Detector Core
VDD
Pbias
Detector Core 1
Pbias MODE0 MODE1 MODE2
d DCout 1 1.2
MODE3 MODE4 MODE5
d DCout
(V) (V)

MODE6 MODE7
IN
0.8 1
Output

IN
DC Detector Output (V)

0.8 -9V/V
Output

Vbias 0.8
0.6
Detector

Vbias
0.6
Detector

(a) 0.6

VDD 0.4
DCDC

Mode2..0
VDD
0.4
Thermometer-code
Mode2..0 0.4
Vbias Thermometer-code
A 7..1
0.2 50
Vbias A7..1 50
0.2 mV
50
mV
0.2
A1 A2 A3 0 mV
A7
A1 A2 A3 A7
0 0 0.1 0.2 0.3 0.4 0.5
Programmable Mode Select High-Frequency Signal Amplitude (V)
0
Programmable Mode Select 0 0.1 0.2
[55-65 GHz] 0.3 0.4
(b) 0 0.1 0.2
High-Frequency 0.3
Signal Amplitude (V) 0.4
Fig. 3. The proposed mmW-amplitude detector: (a) Circuit core, (b) ]Fig. 4. mmWave-to-dc response of the proposed
High-Frequency mmW-amplitude
Signal
(55-65 Amplitude (V)
GHz)
Programmable mode select detector (55-65 GHz)

478
are not critical for the detector circuits since the detector and At each sweep instance, a gain value can be computed and
its bias circuit can be simply turned off using switches or after a sufficient number of iterations, a gain curve is obtained
power gating. where the 1dB compression point is readily deduced.
Knowledge of the LNA gain enables more sophisticated tests,
C. Detector usage in BiST and BiSC
such as two-tone tests for intermodulation (IM) measurements.
The detector can be used to quantify a number of transceiver The IM3 amplitude can be extracted from the detector output
parameters such as gain, linearity, compression points, and by measuring the input and output of the LNA and comparing
even IQ mismatch – as presented in [10]. Since the detector is the latter with the expected output given no distortion (=
followed by an ADC, a quantized detector response can either input×predicted gain): the discrepancy between these two
be saved in a lookup table or fitted into an equation: possibly signals is attributed to the IM amplitude. It should be noted
as a function of slope (-9V/V), mode (50mV shifts), or that in the case of two-tone tests, DCout becomes a low-
piecewise linear reconstruction to enable prediction of signal frequency oscillating signal whose mean is to be considered in
amplitude. For example, using an 8-bit ADC and saving the the IM3 extraction [10]. The results of this sweep showing the
first mode’s response in a lookup table, a quantized detector actual and predicted values using the detector are shown in
output of 128 (= 256/2, DCout = 1.2/2 = 0.6V) equates to a Fig. 8. It can be verified that the detector is able to match the
0.09Vamp signal in mode0, +50mV per additional mode (or real gain with a maximum 0.3dB error, the 1dB compression
more accurately +60mV between mode0 and mode1, +50mV point and IIP3 to within 0.4dB, shown below in Table I.
hereafter). Table I
In the context of a self-calibration loop, the detector can be Actual vs Predicted values for LNA
used as an optimization indicator, e.g. following an Actual Predicted Error
optimization step; a decrease in DCout of a detector monitoring Gain, A [dB] 10.14 10.45 0.3
a specific circuit node indicates an increase in the amplitude of P1dB [dBm] -9.73 -9.32 0.4
the signal at that node. IIP3 [dBm] 3.9 4.3 0.4

III. BIST AND CALIBRATION OF A 60GHZ LNA

The LNA is the first gain stage in the receiver path and
hence needs to be designed to meet tight specifications for the
whole receiver. At 60 GHz, the design of the LNA becomes
very challenging as even the smallest parasitics or disruptions
in operating conditions can completely alter the circuit
performance.
In the following we demonstrate the feasibility of the
proposed detector for test and calibration of the LNA under
test, shown in Fig. 5 [11].
A. Built-in-Self-Test
The accuracy of the proposed detector is verified by
connecting it to a 60 GHz LNA and applying known input
amplitudes. It is worth noting that the detector is verified not
to load the LNA, a critical aspect of this design (see Fig. 7). A
B. Built-in-Self-Calibration
To satisfy the growing number of corners, LNAs and
other mmW circuits need to incorporate some dynamic, rather
than static, structures that allow their operating points to adjust
and guarantee optimal operation under varying conditions, as
shown in Fig. 9. To enable the calibration loop, the previous
BiST setup is augmented with an optimization block that runs
a specific algorithm for each CUT/C. In the simple case of a
single tuning knob, the BiSC can perform an algorithm similar
to Fig. 10 which sweeps through the possible digital codes,
while holding the input constant, and keeps track of the
detector output: the code resulting in the minimum-
CUT mmW/RF

complete on-chip solution to such a BiST configuration (LNA)

requires loopback between transmitter and receiver chains. In
our demonstration, two detectors are used to sense the input DET DET
controlled

and output signals and output a dc voltage which is then

loopback

Digital

quantized (8-bits) and analyzed (see Fig. 6). The detectors’

BiST BiSC
biasing is dynamically adjusted when its output is not
between 0.2 and 1V. In this example, we measure the gain Fig 6. BiST and BiSC setup for the LNA
and compression point by sweeping the input amplitude and 10
predicting both the LNA’s input and output signal amplitudes.
5
VDD VDD VDD
0 with detector w/o detector
-5 S21 S21
dB

CPW CPW CPW

-10 NF NF
IN Matching
Circuit
Matching
Circuit
Matching
Circuit
Matching
Circuit OUT -15 S11 S11
-20
Vbias Vbias Vbias -25
55GHz
5.50E+10 60GHz
6.00E+10 65GHz
6.50E+10
Fig. 5. Three-stage cascade common-source LNA with interstage Fig. 7. Effect of the detectors on the LNA gain, input match, and Noise
matching Figure

479
 2 15
1
Output Signal Power (dBm)

Output Signal Power (dBm)

5
0
-1
-5
-2
-3 -15
-4
-25
-5
-6 Series1
Fundamental
Simulated Gain Curve -35 IM3
Series2
-7 Predicted Gain Curve Predicted
Linear fund/IM3
(trend)
-1dB Line, w.r.t. predicted curve Simulated
Linear fund/IM3
(Series4)
-8 -45
-18 -16 -14 -12 -10 -8 -6 -20 -15 -10 -5 0 5
Input Signal Power (dBm)

Fig. 8. Measurements for LNA gain and linearity. Left: simulated and predicted gain curve, and gain compression point. Right: fundamental and
IM3 component curves, dotted lines show the LNA’s simulated fundamental/IM3 behavior, solid lines are extended data-fitted lines from
extracted fundamental/IM3 amplitudes.

DCout/maximum-mode is retained to be applied to the circuit

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480