14

Performance, Processing, and

Lithography Trends

Krishna Seshan

1.0 INTRODUCTION

Lithographically defined dimensions will continue to shrink as

device scaling enables higher speeds and greater density of transistors.
Lithography equipment, resist processes, and mask-making will change to
meet the challenges. Gate oxides have to become thinner requiring changes
in both growth and metrology equipment. As gate oxides become thinner,
voltages must drop bringing about new material requirements. Lithogra-
phy will call for highly planarized surfaces, causing higher demands on
chemically-mechanically polished surfaces.
As transistor densities increase, the wiring levels providing inter-
connectivity will increase. This will increase the RC (resistance-capaci-
tance) delay contribution of interconnections. The consequent drive to
reduce resistance will drive the change from aluminum-based wiring
metallurgy to copper-based metallurgy. In addition, the drive to decrease
the dielectric constant will call for changes of the SiO2-based dielectric to
a class of “low-K” dielectrics.
Stringent demands will be made on contamination control, particle
detection, and yield enhancement. One of the consequences will be the
move from 8 inch to 12 inch wafers. This will drive consolidation of
process steps.

595
596 Thin-Film Deposition Processes and Technologies

These changing technologies will present new reliability challenges.

This chapter discusses these trends and challenges.

2.0 SCALING THE TRANSISTOR

Gate oxide thickness, channel length, and power supply voltage

scale along well-predicted trends as shown in Fig. 1. This figure is the
basis for understanding the lithography challenges—where line patterning
in the range of 100 nm (0.1 µm) and gate oxides of 30 nm (0.03 µm) will
need to be grown and measured.

Figure 1. Gate oxide thickness, channel length, and power supply voltage scale along
well-predicted trends.

As gate length decreases, the delay per gate decreases. This enables
the transistor-based inverters to switch faster. However, there is a
competing and slowing-down effect, referred to as interconnect delay.
Chapter 14: Performance, Processing, and Lithography Trends 597

Interconnections can be serious limiters of higher performance.[3] Figure 2

shows how the pitch decreases and the number of metal layers increase
with scaling. The RC delay caused by this crowding of metal lines can be
modeled using various capacitance-calculating models. The result is al-
ways the same: the back-end RC delay contribution increases.
The effect of the back-end delay is seen clearly when the total delay
(gate delay + interconnect delay) is plotted for different generations.
Figure 3 is a graph derived from the NTRS roadmap showing the total
delay versus generation. This is only an estimate and is not real data. From
this graph it should be clear that there is need to change the interconnect
metallurgy to copper and to try to reduce the dielectric constant of the
interlayer dielectric (see also Fig. 4). Many companies have announced
processes and some are cited in the references.[1][2]

Figure 2. The pitch decreases and the number of metal layers increase with scaling.
598 Thin-Film Deposition Processes and Technologies

Figure 3. Graph shows the total delay vs device generation. This is only an estimate and
is not real data.
Chapter 14: Performance, Processing, and Lithography Trends 599

Figure 4. Changing to Cu-based metallurgy requires significant changes in the way the
metal is deposited and patterned.

3.0 LOW RESISTANCE: CHANGE TO COPPER-BASED

METALLURGY

Figure 4 shows how the tungsten via and Al-Si line are replaced
with a copper via and a copper line. The challenge then is to change the
interlayer dielectric. At this time several schemes are proposed by which
the dielectric is controlled. One method includes introduction of fluorine
into the deposited SiO2.
The standard capacitance extraction method draws on a very simple
approach that is shown in Fig. 5.
600 Thin-Film Deposition Processes and Technologies

Figure 5. Capacitance extraction methodology and results.

The left top of the figure shows a metal “runner” modeled as a sum
of a parallel plate plus a fringing capacitor. The result of such calculations
(after Bakoglu, Ref. 6) is shown in the left bottom graph which indicates
that as the lines are made narrow and tall, the capacitance decreases. The
dielectric constant for oxide is taken to be 3.9. However, because of
fringing effects, the capacitance asymptotically approaches 1 pf/µm.
On the right is a line surrounded by other metal lines, and here the
graph shows how interconnect RC delay increases as lines are packed
together.
From these graphs it is evident that reducing R, the line resistance,
and C, the line-to-line capacitance, will be a central challenge for some
time.
Chapter 14: Performance, Processing, and Lithography Trends 601

4.0 TREND TO LOW K MATERIALS

In order to obtain lower dielectric constants, the industry will have

to evaluate several new materials. One simple method is to add fluorine to
the deposited silicon dioxide. This is known as SiOF and has a dielectric
constant of about 3.6, as shown in Fig. 6. Other spin-on materials are under
evaluation, but it is too early to predict which materials may be widely
used.
The combination of copper plus new low K materials provides many
new challenges for the thin film industry including the development of
deposition processes and equipment. Spin-on-glasses are candidates and
these often need to be capped. Etching the glasses to deep aspect ratios
may require the use of high density plasmas and modification of modern
reactive ion etching methods. Filling the vias, and making this compatible
with the copper dual Damascene process, may provide challenges for
polishing and for lithography.
Table 1 shows some of the new materials that are currently avail-
able. This list is not exhaustive.

Figure 6. Dielectric constants of some materials.

602 Thin-Film Deposition Processes and Technologies
Table 1. Various Dielectric Materials

Dielectric Material/Trade Manufacturer Compatibility/Use

Range Name or Process

K ~7 Si3N4 - Silicon CVD- or HDP- Al metallurgy

Nitride nitride
Cu metallurgy
Use: moisture
passivation
K ~4 All forms of Various sub- In wide use with Al
SiO2, plasma atmospheric, metallurgy, also
TESO source low pressure with Cu
oxides and HPD metallurgy.
processes Introduction of
fluorine decreases
K
K<3 Fox™ Dow Chemical
SiLK-G™ Dow Chemical All compatible with
Al and with Cu
K<3 FLARE™ Honywell Damascene. Many
Velox Schumacher processes are in
Air Products & development stage.
Chemicals
K <2.5 FSG Entirely in
development stage
Low K Trikon at the time of
Flowfill Technology writing of this
Black Applied book.
Diamond Materials
Coral Novellus
3MS Dow Corning
HOSP™ Honywell
Parylene AF -4 Parylene
K<2.0 Nanoglass™ Honeywell
Chapter 14: Performance, Processing, and Lithography Trends 603

5.0 LITHOGRAPHY AND PLANARIZATION

Basic optical laws pertaining to lithography dictate the need for

highly planarized surfaces.
Smaller dimensions make severe demands on lens designs for opti-
cal lithography equipment. Lenses have to be aberration free, shorter
wavelengths must be used to expose lithography patterns, and high nu-
merical apertures are necessary. The higher the numerical aperture, the
smaller the depth of focus.
Depth of focus is defined as the distance range within which an
image plane will still have the smallest features resolved. As the depth of
focus of lenses decreases, imaging surfaces have to be more planar,
placing additional demands on CMP.

6.0 CHALLENGES TO CONTAMINATION/CLEANING

This vast subject is discussed in Ch. 7 of this book. Here, the trends
are considered from two points of view. First, Sec. 6.1 deals with the
challenges to the detection of smaller and smaller particles. The second
section (Sec. 6.2) deals with trends in equipment.

6.1 Detection/Types of Contamination

Some typical numbers describing limitations on defects are pro-

jected in Table 2. The main message from this table is that detection of
small particles will be a challenge in enforcing and verifying cleanliness.
The costs of operating cleanrooms and keeping equipment clean
will presumably increase, and equipment will become more sophisticated
and expensive. Many laser light scattering methods for checking the state
of cleanliness are currently in the development stage.
Sources of defects are airborne contamination, now containing
increased amounts of molecular organic materials like amines and resist
and resist cleaning materials. These are referred to as AMC (airborne
molecular contamination). The detection of these contaminants and their
effect on yield loss will remain a challenge to the industry.
The challenge to mask-making will be more stringent. See Ref. 8 for
details.
604 Thin-Film Deposition Processes and Technologies

Table 2. Defect Trends

Technology 1997 1999 2001 2003 2006 2008 2012

Generation

Wafer 30 13 8 5 2 1 1
Handling
2
(defects/meter )

Wafer Size 200 300 300 300 300 450 ? 450 ?

(mm)

Critical Defect 125 90 75 65 50 35 25

Size (nm)

Electrical 1940 1712 1512 1353 1119 939 776

2
Defect Do/m
for 60% yield

Chip Area 300 340 385 430 520 620 750

Logic

Mask Levels 22 23 23 24 25 ? 27 ? 28 ?

Faults per Mask 88 74 66 56 45 35 28

Level

6.2 Trends in Integrated Processing

The concept of integrated processing is not new. It is intuitive. It is

ease to show pictorially (Fig. 7), however, actually building equipment is
difficult and expensive, and the practical details of how to keep the
equipment clean and functioning become very complex.
A trend toward integrated processing includes mini-environments
around tools so that locally clean areas near the tool and the wafer are
maintained. The mini-environment can be extremely clean (Class 0.1)
whereas the cleanroom can be in the Class 1 range (see Fig. 8). These will
Chapter 14: Performance, Processing, and Lithography Trends 605

be increasingly necessary as the wafer size increases. Actual tools based

on the conceptual diagram in Fig. 7 are now available and in use.
Cleanroom technology needs increasing attention. Reduction of
particulate contaminants needs sophisticated levels of understanding,
measurements, and diagnostics with experimental and theoretical simula-
tions. Contaminants may be particulate, organic or ionic, and their sources
may be airborne, from chemicals used, from various processing steps, or
from people, tools and equipment. Intrinsic tool processing like evapora-
tion or sputtering may generate particles which are then released from the
tool. This area will receive significant attention in the years ahead.

Figure 7. Conceptual diagram of integrated processing.

606 Thin-Film Deposition Processes and Technologies

log partial pressure

Figure 8. Cleanroom Class designations and associated partial pressures.

7.0 SUMMARY

In this industry it is difficult to be ever up-to-date and to assess

trends accurately, but scaling occurs by rigorous laws so that we can
relatively accurately predict where we need to be. It is more difficult to
predict how we get there and what processes and materials will be in use.
One thing is certain: the deposition of thin films will continue to be an
enabling technology.

REFERENCES

1. Chau, R., et al., 30 nm Gate Length CMOS Transistor, IEDM 2000

Proceedings, p. 45 (2000)
2. Tyagi, Sunit, et al., A 130 nm Generation Logic Technology Featuring 70
nm Transistor, Dual Vt Transistor and 6 layers of Cu Interconnect, IEDM
2000 Proceedings, p. 567 (2000)
3. Bohr, M., Interconnect Scaling—The Real Limiter to High Performance
ULSI, IEDM Proceedings, p. 241 (1995)
4. Seshan, K., Maloney, T. J., Wu, K. J., Quality & Reliability of Intel’s 0.25
µm Process, Intel Technology Journal, available on the web at: http//
developer.intel.com/technology/itj/q31998/articles/art 2a.htm
Chapter 14: Performance, Processing, and Lithography Trends 607

5. Ning, Tak H., Silicon Technology Directions in the New Millennium, IEEE
IRPS Symposium, p. 1
6. Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI, Addison
Wesley (1990)
9. Lilenfield, Pedro, Applications of Pellicles in Clean Surface Technology,
in: Treatise of Clean surface Technology, (K. L. Mittal, ed.), p. 291,
Plenum, New York (1987)
10. National Technology Roadmap published yearly by Semiconductor Industry
Association (SIA). Copyright the SIA Association. These numbers are
from the 1999 edition.