CHAPTER 1

INTRODUCTION

1.1 LOW POWER CMOS CIRCUITS

The current trend towards low-power design is mainly driven by two
forces, the growing demand for long-life autonomous portable equipment and
the technological limitations of high- performance VLSI systems. For the first
category of products, low-power is the major goal for which speed and dynamic
range might have to be sacrificed. High speed and high integration density are
the objectives for the second application category, which has experienced a
dramatic increase of heat dissipation that is now reaching a fundamental limit.
These two forces are now merging as portable equipment grows to encompass
high-throughput computationally intensive products such as portable computers
and cellular phones.

The most efficient way to reduce the power consumption of digital

circuits is to reduce the supply voltage, since the average power consumption of
CMOS digital circuits is proportional to the square of the supply voltage. The
resulting performance loss can be overcome for standard CMOS technologies
by introducing more parallelism and to modify the process and optimize it for
low supply voltage operation.

1.1.1 LIMITS FOR LOW POWER CMOS CIRCUIT DESIGN

The practical limitation in the CMOS circuits is as follows
1. When capacitive loads are imposed on the power supply current I, it is
necessary to obtain a given bandwidth which is inversely proportional to the
Tran conductance-to-current ratio gm/I of the active device. The small value of

1
gm/I inherent to MOS transistors operated in strong inversion may therefore
cause an increase in power consumption.
2. The presence of additional sources of noise implies an increase in
power consumption. These include l/f noise in the devices and noise coming
from the power supply or generated on chip by other blocks of the circuit.
3. The need for precision usually leads to the use of larger dimensions for
active and passive components, with a resulting increase in parasitic capacitors
and power.
4. All switched capacitors must be clocked at a frequency higher than twice
the signal-frequency. The power consumed by the clock itself may be dominant
in some applications.

Interest in and evolution of low-voltage supply, low-power circuits have

grown rapidly from applications on watches and medical electronics such as
pacemakers, hearing aids, blood flow meters to a host of other applications.
This increased interest is mainly due to commercial implications of portable
equipment, power reduction on non-battery-powered systems and consumer
electronics. Some of these examples are the laptop/notebook computers as well
as workstations, PCs, electronic organizers, language translators, electronic
dictionaries, implantable devices, portable radios and TV sets.

In this project dual threshold method is used to reduce the leakage current.
The advantage of the proposed method is, fast approach to analyze the total
leakage power of a large circuit block considering both the Igate and Isub. This
method has minimal Layout impact in reducing the leakage power without
incurring any delay in the circuit.

2
1.2 FEATURE SIZE
Feature size reduction in MOSFETs has been the key enabler to the
continuation of Moore’s law. Just as significant as effective channel length Leff
reduction has been shrinking of the gate oxide thickness Tox. Feature size is
shown in Figure 1.1. Aggressive scaling is required to provide substantial
current at reduced voltage supplies and to suppress short-channel effects such as
drain-induced barrier lowering (DIBL), it results in the presence of significant
gate tunneling leakage current. Igate arises due to the finite probability of an
electron directly tunneling through the insulating SiO2 layer. Igate is the strong
exponential function of Tox as well as the voltage potential across the gate
oxide. Another key point is that for a pMOS device is typically one order of
magnitude smaller than an nMOS device with identical Tox and Vdd when
using SiO2. This is due to the much higher energy required for hole tunneling in
SiO2 and the fact that there are very few electrons associated with a pMOS
device.

Figure 1.1 Feature size

3
 Another key point is that for a pMOS device is typically one order of
magnitude smaller than an nMOS device with identical Tox and Vdd when
using SiO2. This is due to the much higher energy required for hole tunneling in
SiO2 and the fact that there are very few electrons associated with a pMOS
device. However, in alternate dielectric materials the energy required for
electron and hole tunneling can be completely different. In the case of nitrided
gate oxides, pMOS Igate can actually exceed nMOS Igate, depending on the
nitrogen concentration. There are numerous process integration problems with
such high-k materials in particular their compatibility with Si and the resulting
mobility degradation which reduces drive current. Even this projection may be
optimistic as the introduction of new materials has much slower process than
very aggressive scaling of already existing solutions.

1.3 SOURCES OF LEAKAGE CURRENT

There are four main sources of leakage current in a CMOS transistor shown
in Figure 1.2
1. Reverse-biased junction leakage current (IREV).
2. Gate induced drain leakage (IGIDL).
3. Gate direct-tunneling leakage (IG).
4. Subthreshold (weak inversion) leakage (I SUB).

Figure 1.2 Sources of leakage current

4
1.3.1 JUNCTION LEAKAGE
The junction leakage occurs from the source or drain to the substrate
through the reverse-biased diodes when a transistor is off. A reverse-biased p-n
junction leakage has two main components one is minority carrier
diffusion/drift near the edge of the depletion region, the other is due to electron-
hole pair generation in the depletion region of the reverse-biased junction. In the
case of an inverter with low input voltage, the nMOS is off, the pMOS is on and
the output voltage is high. Subsequently, the drain-to-substrate voltage of the
off nMOS transistor is equal to the supply voltage. This results in a leakage
current from the drain to the substrate through the reverse-biased diode. The
magnitude of the diode’s leakage current depends on the area of the drain
diffusion and the leakage current density, which is in turn determined by the
doping concentration. If both n and p regions are heavily doped, band-to-band
tunneling (BTBT) dominates the pn junction leakage.

1.3.2 GATE-INDUCED DRAIN LEAKAGE

The gate induced drain leakage (GIDL) is caused by high field
effect in the drain junction of MOS transistors. For an nMOS transistor with
grounded gate and drain significant band bending in the drain allows electron-
hole pair potential at Vdd generation through avalanche multiplication and
band-to-band tunneling. A deep depletion condition is created since the holes
are rapidly swept out to the substrate. At the same time electrons are collected
by the drain, resulting in GIDL current. This leakage mechanism is made worse
by high drain to body voltage and high drain to gate voltage. Transistor scaling
has led to increasingly steep halo implants, where the substrate doping at the
junction interfaces is increased while the channel doping is low. This is done
mainly to control punch-through and drain-induced barrier lowering while
having a low impact on the carrier mobility in the channel.

5
1.3.3 GATE DIRECT TUNNELING LEAKAGE
The transisor gate leakage is shown if Figure 1.3 flows from the gate
through the “leaky” oxide insulation to the substrate. In oxide layers thicker
than 3–4 nm, this kind of current results from the Fowler-Nordheim tunneling
of electrons into the conduction band of the oxide layer under a high applied
electric field across the oxide layer. Component of leakage current is shown in
Figure1.4 and Figure1.5 for lower oxide thicknesses however, direct tunneling
through the silicon oxide layer is the leading effect. Mechanisms for direct
tunneling include electron tunneling in the conduction band (ECB), electron
tunneling in the valence band (EVB) and hole tunneling in the valence band
(HVB), among which ECB is the dominant one. The magnitude of the gate
direct tunneling current increases exponentially with the gate oxide thickness
Tox and supply voltage V.

Figure 1.3 Transistor gate leakage

Figure 1.4 Gate leakage components in thin oxide MOSFET

6
 Figure 1.5 Components of tunneling current

1.3.4 SUBTHRESHOLD LEAKAGE

The subthreshold leakage is the drain-source current of a transistor
operating in the weak inversion region. Unlike the strong inversion region in
which the drift current dominates, the subthreshold conduction is due to the
diffusion current of the minority carriers in the MOS device. For instance, in the
case of an inverter with a low input channel for a MOS device, the nMOS is
turned off and the output voltage is high. In this case, although Vgs is 0V, there
is still a current flowing in the channel of the off nMOS transistor due to the
Vdd potential of the Vds. The magnitude of the subthreshold current is a
function of the temperature, supply voltage, device size and the process
parameters out of which the threshold voltage (Vt ) plays a dominant role.
In current CMOS technologies, the subthreshold leakage current
Isub, is much larger than the other leakage current components. This is mainly
because of the relatively low Vt in modern CMOS devices. It is highly desirable
to have a sub threshold swing as small as possible since this is the parameter
that determines the amount of voltage swing necessary to switch a MOSFET
from OFF to ON state (typical values of S for bulk CMOS devices are 70-110
mV/decade; the theoretical lower bound is 60 mV/decade corresponding to
n=1.). This is especially important for modern MOSFETs with supply voltages
reaching sub-one volt region. To minimize S, the thinnest possible gate oxide

7
(since it increases Cox) and the lowest possible doping concentration in the
channel (since it decreases Cdep ) must be used. Higher temperature results in
larger S value, and hence, an increase in the OFF leakage current. In long
channel devices, the influence of source and drain on the channel depletion
layer is negligible. However, as channel lengths are reduced, overlapping source
and drain depletion regions cause the depletion region under the inversion layer
to increase. The wider depletion region is accompanied by a larger surface
potential, which attracts more electrons to the channel. Therefore, a smaller
amount of charge on the gate is needed to reach the onset of strong inversion
and the threshold voltage decreases. This effect is worsened when there is a
larger bias on the drain since the depletion region becomes even wider.

8
 CHAPTER 2
LITERATURE REVIEW

1-V power supply high-speed low-power digital circuit technology

with 0.5-pm multithreshold-voltage CMOS (MTCMOS) is proposed. This
technology features both low threshold voltage and high-threshold voltage
MOSFET’s in a single LSI.
An enhanced dual threshold leakage control technique has been
proposed in this paper. By selectively placing the high threshold voltage, the
leakage should be reduced by more than 10 times, while at the same time
achieving comparable performance.
In present CMOS circuits, the power dissipation caused by leakage
current cannot be neglected anymore. An effective way to reduce the leakage
power is dual-threshold techniques. Low-threshold transistors are assigned to
critical paths of the circuits to enhance the performance, while high threshold
transistors are assigned to non-critical paths to reduce the leakage current. This
paper proposes a new transmission gate flip-flop based on dual-threshold
CMOS technique to reduce its leakage power.
Gate-sizing is an effective technique to optimize CMOS circuits for
dynamic power dissipation and performance while dual-V,h (threshold voltage)
CMOS is ideal for leakage power reduction in low voltage circuits. This paper
focuses on simultaneous dual-V,h assignment and gate-sizing to minimize the
total power dissipation while maintaining high performance
Optimization of power and delay is very important issue in low-
voltage and low-power applications. In this paper, we use the dual-threshold
technique to reduce leakage power by assigning a high-threshold voltage to
some transistors and low-threshold to some others .Here, the polarity of the
MOSFETs is considered as the selection criteria for assigning threshold.

9
 Low voltage low power VLSI sub system describes about the
linear relationship between oxide thickness and threshold voltage
Low voltage low power CMOS design techniques for deeps of
submicron ICs explains about source of power consumption and ways to
achieve dual threshold voltage
Power minimization by simultaneous dual threshold assignment
describes about the simultaneous assignment of dual threshold

2.1 EXISTING METHODS TO REDUCE THE LEAKAGE POWER

2.1.1 BY GATING THE POWER SUPPLY

The most natural way of lowering the leakage power dissipation of a
VLSI circuit in the STANDBY state is to turn off its supply voltage. As shown
in Figure 2.1 this can be done by using one pMOS transistor and one nMOS
transistor in series with the transistors of each logic block to create a virtual
ground and a virtual power supply. In practice only one transistor is necessary,
because of their lower on-resistance, nMOS transistors are usually used.

Figure 2.1 power gating circuit.

10
 In the ACTIVE state, the sleep transistor is on. Therefore, the circuit
functions as usual. In the STANDBY state, the transistor is turned off, which
disconnects the gate from the ground. Note that to lower the leakage, the
threshold voltage of the sleep transistor must be large. Otherwise, the sleep
transistor will have a high leakage current, which will make the power gating
less effective. Additional savings may be achieved if the width of the sleep
transistor is smaller than the combined width of the transistors in the pull-down
network.
To guarantee the proper functionality of the circuit, the sleep transistor
has to be carefully sized to decrease its voltage drop while it is on. The voltage
drop on the sleep transistor decreases the effective supply voltage of the logic
gate. Also, it increases the threshold of the pull-down transistors due to the body
effect. This increases the high-to-low transition delay of the circuit. This
problem can be solved by using a large sleep transistor. On the other hand,
using a large sleep transistor increases the area overhead and the dynamic power
consumed for turning the transistor on and off. Because of this dynamic power
consumption, it is not possible to save power for short idle periods. There is a
minimum duration of the idle time below which power saving is impossible.
Increasing the size of the sleep transistors increases this minimum duration.

Figure 2.2 using one sleep transistor for several gates.

11
 Since using one transistor for each logic gate as shown in Figure
2.2 results in a large area and power overhead, one transistor may be used for
each group of gates as depicted. To find the optimum size of the sleep transistor,
it is necessary to find the vector that causes the worst case delay in the circuit.
This requires simulating the circuit under all possible input values, a task that is
not possible for large circuits.

Figure 2.3 sleep transistor sharing.

These inverters switch at different times due to their propagation
delays. Therefore, it is possible to combine their sleep transistors and use one
transistor instead of three as shown in Figure 2.3. In general, if there are n logic
gates whose output transition windows are non-overlapping, and each has a
sleep transistor whose width is Wi, then these sleep transistors may be replaced
with a single transistor whose width is Weq = Max Wi. This will decrease the
delay degradation of the logic gates whose corresponding sleep transistors are
narrower than Weq. Further, if there are several sleep transistors corresponding
to some logic gates with overlapping output transition windows, then these
sleep transistors may be replaced by a single transistor whose width.

12
 The drawbacks of gating the power supply is

• It decreases the voltage swing therefore, it decreases the DC noise margin

• Decreased circuit speed due to the sleep transistor’s resistance

• Increased area for sleep signals and transistors

• Long time to re-enable a circuit block

• Reduced performance and noise immunity

• Sleep transistor sizing is a non-trivial task and requires much effort

2.1.2 BY BODY BIAS CONTROL AND POWER SUPPLY COLLAPSE.

One of the methods proposed for decreasing the leakage current is
using reverse-body bias (RBB) to increase the threshold voltage of transistors in
the STANDBY state. The threshold voltage of a transistor can be calculated
Where VT0 is the threshold voltage for VSB =0, Fφ is the substrate
Fermi potential, and the parameter γ is the body-effect coefficient. Reverse
biasing a transistor increases its threshold voltage. Reverse biasing can be done
during standby, by applying a strong negative bias to the nMOS bulk via a
charge pump and connecting the pMOS bulks (N wells) to the VDD rail. The
reverse body biasing (RBB) is applied to the pMOS transistors by raising the N-
well voltages. This method requires a triple-well technology, which may not
always be available. Because the threshold voltage changes with the square
root of the reverse bias voltage, a large voltage may be necessary to get a small
increase in the threshold voltage. On the positive side, with RBB, the IC logic
state is retained while in the STANDBY mode, allowing operation to resume
where it suspended. It is unnecessary to save the sate of the logic before
entering the STANDBY state.

13
 When IG is ignored, the leakage current has three main
components IREV, IGIDL and IOFF. The last component is typically much
larger than the first two. Bringing the voltage of nMOS Bulk below zero volts
decreases IOFF, but it increases IREV and IGIDL. This is because the strong
bulk biasing increases GIDL and drain to bulk tunneling leakages to the point
where they become limiting on advanced processes. To avoid this, RBB should
use the lowest effective voltages. This suggests that there is an optimum
substrate voltage for which the total leakage current is at a minimum.
When Vss is increased to apply RBB while reducing Vdd - Vss to
approximately 350 mV with a VDD value of 1 V. In addition to the RBB effect
on IOFF, this rail-to-rail voltage reduction limits GIDL, drain to bulk
tunneling, and gate leakage components while applying approximately 650 mV
body bias to the NMOS transistors. The amount of power supply collapse is
limited because an excessive collapse of the core voltage would result in non-
state-retentive sleep mode, which is undesirable in many applications. Briefly,
state loss occurs when the total leakage current of the transistors holding a logic
state exceeds that of the “on” transistors.
The drawbacks of gating the power supply is

• This method become less effective as the supply voltage is scaled down

• The optimum substrate voltage decreases by a factor of two, and the

leakage reduction becomes less effective by a factor of four in each
technology generation

• Method may not be as effective in future technology generations

14
 CHAPTER 3
METHODOLOGY

3.1 DUAL THRESHOLD VOLTAGE METHOD

The dual threshold voltage method is used to reduce the leakage power.
This method is a fast approach to analyze the total leakage power of a large
circuit block, considering both Igate and subthreshold leakage Isub. This
technique is more effective for reducing total leakage power in standby mode
and active mode.
It is a method to assigning high threshold in critical path and low
threshold in non critical path of full adder without affecting the internal
parameters .Dual threshold can be achieved by using dual supply voltage and
adjusting the aspect ratio of transistor

3.1.1 LEAKAGE POWER ANALYSIS

Standby current estimation is complicated by the state dependence of
both the Igate and Isub currents. The state dependence of subthreshold leakage
current has been extensively studied and exhibits the so-called stack effect,
where multiple transistors that are off in series have a significantly reduced
subthreshold leakage current. Similarly, gate tunneling current has state
dependence, as well as dependence on the device type. As mentioned, pMOS
devices typically exhibit gate tunneling currents that are approximately one
order of magnitude lower than those of nMOS devices. Hence, we ignore the
pMOS gate current and focus only on nMOS transistors in our analysis.
However, our analysis method can be extended to include nMOS based Igate
when nitrided gate oxides are used.

15
 Gate tunneling current furthermore has a strong dependence on
the Vgs and Vgd of a device, leading to state dependence. The maximum gate
tunneling current and for the occurs when the input is at Vdd and Vs= Vd= 0v
for the gate nMOS device. In this case, tunneling current is at its maximum with
equal current flowing to the source and drain nodes. At the same time, the
pMOS device exhibits subthreshold leakage current. As the input voltage is
decreased, is reduced by more than one order of magnitude when Vgs = Vth,
nmos and becomes zero when Vgs=0.

Figure 3.1 Inverter with NMOS leakage current

As the input voltage decreases and the output voltage increases, Vgd will
become negative resulting in a reverse gate tunneling current from the drain to
the gate node. However, this reverse gate tunneling occurs when the nMOS
transistor is off and tunneling is restricted to the gate-to-drain overlap region,
due to the absence of a channel as shown in Figure 3.1. Since the gate-to-drain
overlap region is substantially smaller than the channel region, reverse
tunneling current is much smaller than the forward tunneling current when the
device is on, and hence can be ignored.

3.2 TANNER EDA

16
 Tanner EDA is a leading provider of Electronic Design
Automation (EDA) software solutions for the design, layout and verification of
Analog/MixedSignal ICs and MEMS. This tool help to automate and simplify
the design process, enabling engineers to cost-effectively bring commercially
successful electronic products to market ahead of the competition.Tanner’s
fully-integrated solutions consist of tools for schematic entry, circuit simulation,
waveform probing, full-custom layout editing, placement and routing, netlist
extraction, LVS and DRC verification. Tanner EDA’s innovative solutions are
used in a range of applications in next-generation wireless, consumer
electronics, imaging, power management, biomedical, automotive and RF
market segments.
Tanner EDA tools are used by more than 25,000 engineers for
Analog/ Mixed-Signal ICs and MEMS devices. Customers such as Catalyst
Semiconductor, Honeywell, Jet Propulsion Laboratory, NEC, Ricoh Company
Ltd., Sarnoff Corporation, Xerox Corporation and others rely on these tools to
help them speed from concept to silicon efficiently. Some of the products
designed with Tanner EDA tools include imaging technology for the Mars
Rover, components for Bluetooth peripherals and thermal management sensors
for cell phones and notebook PCs.
3.2.1 T-SPICE
The essential analog design tool in the Tanner EDA Tool Suite
offers significant improvements in simulation speed and robustness. It delivers
smooth and efficient design flow from schematic to simulation to waveform
viewing. T-Spice offers options and commands not found in Berkeley SPICE or
most derivatives, such as design optimization, Monte Carlo analysis, multi-
dimensional parameters, or source and temperature sweeping. Tightly integrated
with Tanner EDA’s S-Edit schematic capture tool, T-Spice provides a state-of-
the-art analog design environment at an affordable price.

17
3.2.2 S-EDIT

S-Edit, Tanner EDA’s schematic capture tool, has been completely re-
architected and rebuilt into a new tool with user interface, performance and
interoperability enhancements added. New is the ability to probe element and
sub-circuit terminal currents and charges. S-Edit uses the TCL scripting
language, which makes it fully expandable, as well as enabling easy
modification of current designs. Integrated productivity tools, such as Design
Checker and Library Browser, plus multiple libraries and language support for
English, Chinese, Russian and Japanese, all combine to deliver a comprehensive
and interactive design environment.
In addition, S-Edit supports integrated analog simulation with
automatic conversion from Cadence® and View Draw® schematics. Users can
run simulations and cross-probe from S-Edit, making the design process real-
time and more efficient. The ability to view operating point simulation results
directly on the schematic is another S-Edit productivity enhancing feature.

18
 CHAPTER 4
RESULTS AND DISCUSSION

The Full Adder circuit and Array multiplier is simulated using SPICE tool.
From that response the advantage of the proposed system can be clearly known

4.1 FULL ADDER CIRCUIT WITH OUT DUAL THRESHOLD

The results for the FULL ADDER circuit are shown in Table 4.1

C B A S C+1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 4.1 Full Adder output results

4.1.1 SCHEMATIC:

19
 Figure - 4.1 : SCHEMATIC DIAGRAM OF 28T FULL ADDER WITH
OUT DUAL THRESHOLD

4.1.2 WAVEFORM :

20
 Figure 4.2 Output waveform
4.1.3 POWER RESULTS

21
Average power consumed -> 1.273518e-005 watts
Max power 2.593316e-005 at time 1.21014e-006
Min power 2.069169e-028 at time 1.45456e-006

4.2 FULL ADDER CIRCUIT WITH DUAL THRESHOLD

22
4.2.1 SCHEMATIC:

23
Figure - 4.3 : Schematic Diagram of 28T Full Adder With Dual Threshold

24
4.2.2. WAVE FORM

Figure 4.4 Output waveform

4.2.3 POWER RESULTS

v31 from time 0 to 5e-005
Average power consumed -> 4.169098e-009 watts
Max power 4.169098e-007 at time 0
Min power 4.169098e-007 at time 0

25
4.3 4X 4 ARRAY MULTIPLIER WITHOUT DUAL THRESHOLD

4.3.1. STRUCTURE OF 4X4 ARRAY MULTIPLIER.

Figure 4.5 Array multiplier structure

26
4.3.2 SCHEMATIC:

Figure 4.6 Schematic Diagram of 4x4 array Multiplier without dual threshold
27
4.3.3. WAVE FORM

Figure 4.7 Output waveform

4.3.4. POWER RESULTS

v1 from time 0 to 0.0005
Average power consumed -> 4.365293e-08 watts
Max power 4.365293e-005 at time 0
Min power 4.365293e-005 at time 0

28
 4.4 4X 4 ARRAY MULTIPLIER WITH DUAL THRESHOLD

4.4.1. SCHEMATIC:

Figure 4.8 Schematic Diagram of 4x4 array Multiplier with dual threshold

29
4.4.2. WAVE FORM

Figure 4.9 Output waveform

4.4.3. POWER RESULTS

v1 from time 0 to 0.0005
Average power consumed -> 8.565493e-010 watts
Max power 8.565493e-007 at time 0
Min power 8.565493e-007 at time 0

30
4.5 POWER ANALYSIS TABLE
Circuits Average power consumed
(watts)
Full adder with out dual threshold 1.273518e-005 watts
Full adder with dual threshold 4.169098e-009 watts
Array Multiplier without dual threshold 4.365293e-008 watts
Array Multiplier with dual threshold 8.565493e-010 watts

TABLE 4.2 POWER ANALYSIS

CHAPTER 5

31
 CONCLUSION AND PHASE II WORK SCHEDULE
5.1 CONCLUSION
The leakage power has been reduced for the circuits like Full Adder
circuit and Array Multiplier using Dual threshold method. This technique can be
applied to complex circuit so that the Leakage power can be reduced. This
method has 40 to 50% leakage power reduction. This project is carried out by
tanner EDA simulation tool.
5.2 WORK SCHEDULE FOR PHASE II:
The work for the phase II is scheduled to be the design of the low
power FIR filter with the designed dual threshold adder and the 4×4 Array
Multiplier.

REFERENCES

32
1. Anindya ghosh, Debapriyo ghosh, “Optimization of Static Power,

Leakage Power and Delay of Circuit Using Dual Threshold MOSFET

Based Design and T-SpiceSimulation” -2009 International Conference on
Advances in Recent Technologies in Communication and Computing
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4. Wei, L.; Chen, Z.; Roy, K.; Johnson, M.C.; Ye, Y.; De, V.K, “Design and

optimization of dual-threshold circuits for low-voltage lowpower-

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