Von Neumann
Architecture
Harvard
Register
Different levels of cache
Memory hierarchy
Main memory
Disc space
Algorithm
Top 10 SW power optimization Optimize for speed for more CPU idle
mode or reduce CPU frequency
Don't over calculate
Use DMA for efficient transfer
Use co-processors to efficiently
Code handle/accerlate frequent/specialized
processing
Use more buffering and batch processing
to allow more computation at once and
more time in low power modes