Esd

ELE863/EE8501 VLSI Systems
Electrostatic Discharge Protection
GATE
BOND SOURCE
PAD
Fei Yuan, Ph.D, P.Eng.

Department of Electrical & Computer Engineering
Ryerson University
Copyright c 2009
Copyright (c) F. Yuan 2009 (1)

OUTLINE
• Introduction to ESD
• Principle Sources of ESD in ICs
• ESD Models
• ESD Protection Mechanisms
• ESD Protection Devices
• ESD Protection Circuits

Introduction to ESD
• What is ESD ?
⊲ ESD - Electro-Static Discharge.
⊲ ESD is a transient discharge of static charge that arises from either

human handling or a machine contact.
⊲ Although ESD is the result of a static potential in a charged object,

the energy dissipated and damages made are mainly due to the
current flowing through ICs during discharge.
⊲ Most ESD damages are thermally initiated in the form of device /

interconnect burn-out or oxide break-down. The basic phenomenon
of ESD is that is a large amount of heat is generated in a localized
volume significantly faster than it can be removed, leading to a
temperature in excess of the materials’ safe operating limits.
⊲ ESD Damages
pn-junction may melt.
Gate oxide may have void formation.
Metal interconnects & Vias may melt or vaporization, leading to

shorts or opens.
⊲ Gate-oxide breakdown is another form of ESD damage.

Introduction to ESD (cont’d)
• Why is ESD Critical ?
⊲ The aggressive decrease in physical dimensions and increase in

doping in modern CMOS technology result in a significant decrease
in gate-oxide thickness and pn-junction width −→ Require less
energy and lower voltages to destroy MOS devices.
500
450
400
350
300
tox [A]
250
200
150
100
50
0 0.5 1 1.5 2 2.5 3
Lmin [µm]
Figure 1: Scaling of gate oxide thickness of MOS transistors.

Introduction to ESD (cont’d)
0.8
0.7
0.6
Junction depth [µm]
0.5
0.4
0.3
0.2
0.1
0 0.5 1 1.5 2 2.5 3
L [µm]
min
Figure 2: Scaling of junction depth of MOS transistors.
20
V Student Version of MATLAB
t1
Vox
15
Vt1, Vox [V]
10
5
20 40 60 80 100
Gate oxide thickness, t [A]
ox
Figure 3: Scaling of the breakdown voltage of gate oxide (Vox ) and the avalanche breakdown voltage
(Vt1 ) of pn-junctions.
⊲ The level of ESD stress, however, does not scale down with the
technology.

Principle Sources of ESD in ICs
• Human Handling
⊲ A person walking on a synthetic floor can accumulated up to 20 kV.

This voltage is discharged when the person touches an object that is
sufficiently at ground. Charge exchange occurs between the person
and the object in a very short time duration (10 ns - 100 ns). The
charging current is approximately 1A - 10A, depending upon the
time constant.
• Test and Handling Systems
⊲ Equipment can accumulate static charge due to improper

grounding. The charge is transmitted through ICs when it is picked
up for placement in test sockets.
• IC Itself is Charged During Transport / Contact

With Charged Objects
⊲ ICs remain charged until they come into contact with a grounded
surface (large metal plates /test sockets). Charge is discharged
through the pins of ICs. Large currents in the internal interconnects
can result in high voltage inside the devices which can cause
damage to thin dielectrics and insulators.

ESD Models
• Human Body Model (HBM)
⊲ HBM models the ESD of a human body.
⊲ Peak current ≈ 1.3A, rise time ≈10-30ns.
Human body model
R=1.5kW
VC (0 - ) C=100pF DUT
Figure 4: Equivalent circuit of the human body model of ESD. The switch closes upon an ESD event.

ESD Models (cont’d)
• Machine Model (MM)
⊲ MM models the ESD of manufacturing / testing equipment.
⊲ Peak current ≈ 3.7A, rise time ≈15-30ns, bandwidth ≈ 12 MHz.
Machine model
VC (0 - ) DUT
C=200pF
Figure 5: Equivalent circuit of the machine model of ESD. The switch closes upon an ESD event.
⊲ ESD stress caused by charged machines is sever because of zero

body resistance. Most ESD protection circuits can only protect
HBM and MM.

ESD Models (cont’d)
• Charge Device Model (CDM)
⊲ CDM models the ESD of charged integrated circuits.
⊲ Inductance in the model is mainly due to the inductance of bond

wires.
⊲ Peak current ≈ 10A, rise time ≈1ns.
⊲ Gate oxide breakdown is the signature failure of CDM stress, in

contrast to the thermal failure signature of HBM and MM stress.
⊲ CDM stress has the fastest transient and has the max. peak current.
⊲ CDM stress is the most difficult ESD stress to protect against.
Charged device model

R<10 W L<10 nH
DUT
Figure 6: Equivalent circuit of charged device model of ESD. The switch closes upon an ESD event.

ESD Protection Mechanisms (cont’d)
• Current Limiting Characteristics of n-well Resistors
• Impact Ionization
• Avalanche Multiplication of pn-junctions
• First Breakdown (Avalanche Breakdown) of nMOS
• Second Breakdown (Thermal Breakdown) of nMOS

• Current Limiting Characteristics of n-well Resistors
⊲ Conductivity
⊲ Majority charge carriers in n-well resistors are free electrons.
⊲ At low voltages, the velocity of free electrons (majority charge

carriers) and that of holes (minority charge carriers) in a n-well
resistor are linearly proportional to the field intensity of the applied
electric field −→ a linear resistor with a constant resistance.
vn = µn E, vp = µp E, (1)
where vn and vp are the velocity of free electrons and that of holes,
respectively, µn and µp are the bulk mobility of free electrons and
holes, respectively.
⊲ The total charge crossing a cross-section of area A per second is

given by
Q = (vnn + vp p)Aq, (2)
where n and p are the concentration of free electrons and holes,

respectively, and q is the charge of an electron.
⊲ The current density is obtained from
Q
J= = (nµn + pµp )qE = σE, (3)
A
where
σ = (nµn + pµp )q (4)
is the conductivity.
⊲ Current Density
⊲ For n-type, the concentration of free electronics is approximately

the doping of the donors, i.e. n≈nn , where nn is the doping of
donors, we have vn≈µn E. Consequently
J≈Jn = (nnµn E)q = nn vn q = σE (5)
J is linearly proportional to E or equivalently the voltage across the

semiconductors.

⊲ Velocity Saturation
⊲ At high voltages, the velocity of free electrons saturates due to the

increasing collision with silicon lattices. As a result, the current
through n-well resistors remains nearly constant regardless of
voltage increase
Jsat = nn vn,satq (6)
vn,sat ≈107cm/s, nn = 1017/cm3 −→ Jsat = 1.6×105A/cm2.
vn
Ohmic region Saturation region
v
sat
(10 7 cm/s)
0 4
10 V/cm E
Figure 7: Velocity saturation
⊲ n-well resistors exhibit a large resistance in the saturation region

shown above.
⊲ n-well resistors in the saturation region can be used as

current-limiting devices for ESD protection by limiting the amount
of ESD discharging current that can pass through the devices.

• Avalanche Multiplication in pn-junctions
⊲ When a pn-junction is reverse biased, the reverse current (leakage

current) is solely due to (i) the movement of thermally generated
charge carriers in the depletion region and (ii) the diffusion of
charge carriers in the neutral regions.
⊲ When the reverse biasing voltage exceeds Vsat = 105V/cm, the

carriers in the depletion region can impart enough energy in the
collision with the silicon lattices to generate electron-hole pairs,
which become free charge carriers. These charge carriers are then
accelerated, collide with the silicon lattices, and create more free
charge carriers −→ Avalanche Multiplication.
Strike the covalent bond

and destroy it
Free electron -
Si Si Si
- Holes
Hole
-
Si Si Si Si Si Si Si Si Si
Covalent bonds
Si Si Covalent bond Si
destroyed
Figure 8: Avalanche multiplication

• Avalanche Breakdown of nMOS
⊲ Parasitic Lateral Bipolar Transistor in nMOS
PAD
G
D S
p+ n+ n+
Isub
Rsub VB
p-substrate
Figure 9: Parasitic lateral BJT in nMOS transistors.
⊲ nMOS is used as ESD protection devices.
⊲ Gate is grounded to ensure nMOS is off under normal operation

conditions.
⊲ Drain-substrate/source-substrate pn-junctions are reverse biased.
⊲ A parasitic lateral BJT as shown exists in the substrate.
⊲ Under normal operation conditions, this parasitic BJT is off

because both the pn-junctions of the nMOS transistor are reverse
biased −→ Isub = 0, −→ VB = 0.

⊲ Avalanche Breakdown of Drain pn-junction of nMOS
⊲ When VD increases, the electric field across the drain-substrate

depletion region becomes high enough such that avalanche
multiplication occurs at the drain-substrate junction −→ free
electron-hole pairs are generated.
⊲ The generated free electrons go to the drain due to its high

potential, whereas the generated holes go to substrate due to its low
potential −→ It gives rise to Isub −→ The base potential
VB = Rsub Isub is increased subsequently.
⊲ When VB is sufficiently high, the source-substrate pn-junction

becomes forward biased −→ electrons in the source (emitter) are
emitted to the substrate (base) −→ the parasitic lateral BJT is ON
−→ Avalanche Breakdown of MOSFETs −→ Static charge on pads
is discharged via the BJT to the ground. Current capacity is
determined by the width of the MOSFETs (the width of the BJT).
⊲ The turn-on time of the parasitic BJT is determined by the base

transit time (τb = 250ps for 1 µm channel length).
⊲ Note the fundamental differences between the parasitic BJT and

normal BJTs. The base width of the parasitic BJT equals to the
channel length of the nMOS transistor (in the range of µm),
whereas that of a normal BJT is very small (in the range of Å) −→
This BJT has a small current gain as the emitter and collector have
the same dimension.

⊲ Snapback
ID
Thermal
breakdown
region
(Vt2 , I t2 )
Thermal
breakdown Snapback region
(ESD protection
operation region)
Slope=1/R sh
Avalanche
breakdown
Vsh (Vt1 , I t1 ) VD
Figure 10: Avalanche breakdown, snap back, and thermal breakdown of nMOS transistors.
⊲ When the BJT is ON, more electrons flows from the source to the
drain −→ ID ↑ and VD decreases sharply until the snapback holding
voltage Vsp is reached. The snapback holding voltage is mainly
across the drain-substrate pn-junction. The marginal increase of the
drain voltage is due to voltage drop across the drain diffusion,
source diffusion, and contact resistance.
⊲ During snapback, the resistance has positive temperature

coefficients. This implies that if the current in any region increases,
the temperature of the region will increase, thereby increasing the
resistance, which encourages the current to flow elsewhere −→
current is conducted uniformly by all figures of nMOS transistors.

• Thermal Breakdown of nMOS
⊲ During snapback, the current of nMOS increases with the external

voltage VDS .
⊲ If VDS continues to increase, the device enters the thermal

breakdown −→ with the onset of the thermal breakdown, the
resistance of the current path has negative temperature coefficients,
encourages current to concentrates in certain localized fingers of
nMOS and eventually destroys the fingers.
⊲ The concentration of ESD current into a few fingers indicates that

no matter how many fingers are used, only a few will be activated
in case of an ESD strike −→ ESD current capability of the device
does not scale with its size.
⊲ To enhance the self-protection of ESD protection devices, the

current must flow UNIFORMLY in all fingers of ESD protection
devices.

• Avalanche Breakdown versus Thermal Breakdown
⊲ If the avalanche breakdown voltage of ESD protection devices is

LESS THAN their thermal breakdown voltage, then the avalanche
breakdown occurs before the thermal breakdown −→ ESD stress
will be released by the avalanche breakdown and the devices will
not enter the thermal breakdown.
⊲ If the avalanche breakdown voltage of ESD protection devices is

GREATER THAN their thermal breakdown voltage, the avalanche
breakdown will occur at a voltage higher than the thermal
breakdown voltage. After the avalanche breakdown occurs, VDS will
still higher than the thermal breakdown voltage −→ the devices will
enter thermal breakdown and concentrate currents in a localized
area due to negative temperature coefficients −→ device will be
destroyed.
ID ID
Thermal
breakdown
Thermal
breakdown
Avalanche Avalanche
breakdown breakdown
Vsp Vt1 < Vt2 VD Vsp Vt2 < Vt1 VD
(A) Avalanche breakdown voltage is less than (B) Avalanche breakdown voltage is greater then
thermal breakdown voltage thermal breakdown voltage
Figure 11: Avalanche breakdown/thermal breakdown voltages

ESD Protection Devices
• n-well Resistors
• Gate-Grounded nMOS Transistors (GGNMOS)
• Gate-Coupled nMOS Transistors (GCNMOS)
• Silicon Controlled Rectifiers (SCR)
• Medium Voltage Triggered SCR

ESD Protection Devices (cont’d)
• n-well Resistors
M1 M1
M1 M1
SiO2 Poly
SiO2
SiO2
N-well
P-substrate P-substrate
n+
Poly-resistor N-well resistor
Figure 12: Poly and n-well resistors
⊲ Poly-resistors in general should not be used as ESD protection

devices due to their poor heat dissipation capability (Poly resistors
are isolated from the substrate by the SiO2 layer). Note that the
heat generated by ICs is taken away via two paths (i)
PADs/traces/pins and (ii) substrate/ground plate.
⊲ n-well resistors have a good contact with the substrate. They are
used as primary current-limiting devices.
⊲ When a n-well resistor is used as the current-limiting device,

together with a nMOS (primary ESD protection device), it is
essential to make sure that the n-well resistor will not enter its
thermal breakdown when the nMOS is in its avalanche breakdown.

• Diodes
n-well
p+ n+
pn-junction
Rn-well
p-substrate
p+/n-well diode
(a) p+/n-well diodes
Internal
PAD circuits
n+ p+ p-well n+/p-well diode
R p-well
p-substrate
(b) n+/p-well diodes
Figure 13: Diodes in CMOS. (a) p+ /n-well diodes; (b) n+ /p-well diodes; (c) ESD protection using
diodes.
⊲ Two main types of diodes : n+ /p-well diodes and p+ /n-well diodes.

p+ /n-well diodes have a pn-junction between the n-well and
p-substrate whereas there is no isolation between the diode and the
p-substrate in n+ /p-well diodes.
⊲ When forward-biased, diodes can sustain a large current with a

small device dimension.
⊲ Diodes are widely used for ESD protection at radio frequencies due
to the small junction capacitance, which has a less impact on the
bandwidth of RF circuits.

• Gate-Grounded nMOS Transistors
PAD
D G S
DS SS
n+
RD RS
R sub
p-substrate
Figure 14: Drain contact-gate spacing (DS) and source contact-gate spacing (SS) of ESD protection
nMOS transistors.
⊲ During a ESD strike, the pn-junction at the drain undergoes an

avalanche breakdown. Holes flow to the substrate, resulting in an
increase in VB −→ parasitic BJT will be turned on −→ ESD
current flows from the collector the (drain of nMOS) to the emitter
(the source of nMOS that is connected to the ground) −→ ESD
stress at the drain of the nMOS transistor (PAD) is released.
⊲ The dimensions of ESD nMOS should be large enough to handle

large ESD currents −→ multiple fingers structure is used to
implement ESD nMOS.
⊲ The main design parameters of nMOS are (i) channel length, (ii)
drain contact-to-gate spacing, and (iii) device width. The source
contact-to-gate spacing is not critical and is kept at its minimum
design value.

i) The minimum channel length is good for efficient turn-on but the
punch-through limit will be reduced.
ii) Drain contact-to-gate spacing affects the resistance of ballast

resistors. For silicided processes, the minimum drain contact-to-gate
spacing is used.
iii) Device width determines the maximum current that the device
can conduct.

• Gate-Grounded nMOS Transistors (cont’d)
n-well ballasting
D
resistor
Contact/via
n+
1 2 3 4
G
S
Metal-2 Metal-1
Figure 15: Lumped ballast resistors are added at the drains to ensure a uniform ESD current distri-
bution among the fingers of ESD protection transistors.
⊲ During an avalanche breakdown, the current flowing through the

drain increases. However, the positive temperature coefficient of the
resistance of n+ -diffusion (called Ballast Resistors) at the drain
prevents current from concentrating in a localized region −→ it
forces the ESD current to flow into other fingers −→ uniform
current distribution is achieved.
⊲ The effect of n+ -diffusion resistance is virtually eliminated in

silicided CMOS processes because in these processes n+ is silicided
and the resistance of silicided n+ is small (a few ohms).
⊲ To preserve the current-limiting ability of ballast resistors, explicit

n-well ballast resistors at the drain are added. Note that the sheet
resistance of n-well is much higher than that of n+ -diffusion.

• Gate-Coupled nMOS Transistors
⊲ In most applications, the gate of ESD nMOS is grounded to ensure

that the ESD nMOS will not cause any extra leakage at the pin
during normal operation (Without ESD).
⊲ The avalanche breakdown voltage is reduced if the gate of nMOS is

properly biased during a ESD strike.
⊲ The gate voltage helps reduce the width of the pn-junction at the
drain −→ increase the electric field in the junction and lower the
avalanche breakdown voltage of the junction.
⊲ The value of C and R must be such that (i) they have no effect on
the operation of the circuit when there is no ESD stress, (ii) they
must couple a sufficient voltage to the gate during a ESD strike
such that the avalanche breakdown voltage of nMOS is effectively
reduced.

• Gate-Coupled nMOS Transistors (cont’d)
Internal PAD
V circuits
DS C
(Avalanche
breakdown
voltage)
R
VG
ID
Thermal breakdown
Reduced avalanche breakdown

Avalanche breakdown
VD
Vsp
Figure 16: Gate-coupled nMOS
⊲ C behaves as a short-circuit for ESD strikes (high frequencies).
⊲ Gate voltage helps reduce the width of the pn-junction at the drain
(connected to the pad) as the potential of the substrate underneath
the gate oxide is increased −→ drain pn-junction will undergo an
avalanche breakdown at a lower junction voltage −→ ESD
protection occurs at a lower drain voltage (better ESD protection).

⊲ Drawbacks of nMOS-based ESD Protection
⊲ Effective for non-silicided processes. Less effective for silicided

processes.
⊲ Need additional ballast n-well resistors to increase ESD protection.
⊲ Need gate-coupling circuitry to improve ESD protection.

• Silicon-Controlled Rectifiers (SCR)
Internal PAD
circuits
pn-junction
p+ n+ n+ p+
Rnwell
T1 T2
n-well
Rsub Ic2
p-substrate
Figure 17: Silicon-controlled rectifiers (SCRs).
⊲ Under normal operation, the pn-junction between n-well and

p-substrate is reverse biased and SCR has no effect on the operation
of the protected circuits.
⊲ During a ESD strike, the pn-junction between n-well and substrate

undergoes an avalanche breakdown −→ currents flow from n+
through Rnwell to the substrate −→ a sufficient voltage drop across
Rnwell turns on T2 −→ a large current flows from p+-diffusion
through Rsub to the ground −→ T1 turns on −→ T1 and T2 latch
up to release ESD stress.
⊲ SCR has a high ESD breakdown voltage (≈40V with the latch-up
time ≈1ns) as compared with that of nMOS because the breakdown
voltage of n+/p-sub is lower than that of n-well/p-sub (large
pn-junction width) −→ internal circuits might have already been
destroyed even before ESD protection circuits are activated.
⊲ SCR is not affected by silicidation −→ attractive for modern CMOS

processes where silicidation is common.

• Medium-Voltage Triggered SCR
⊲ An additional n+ is added at the edge of the n-well to reduce the

junction width.
n+-diffusion
Internal PAD
is added
circuits
p+ n+ n+ n+ p+
Rnwell
T1 T2
n-well
Rsub Ic2
p-substrate
Figure 18: Modified silicon-controlled rectifiers (MSCRs).
⊲ During an ESD strike, pn-junction in this region undergoes an

avalanche breakdown at a LOWER voltage.
⊲ Breakdown voltage : 25V for 0.35µm CMOS (40V for conventional

SCR).

• Low-Voltage Triggered SCR
⊲ An additional n+ is added at the edge of the n-well to reduce the

junction width.
Grouded-gate Internal PAD

is added circuits
p+ n+ n+ n+ p+
R nwell
T1 T2
n-well
Rsub Ic2
p-substrate
Figure 19: Low-voltage silicon-controlled rectifiers (LVTSCRs).
⊲ The added gate-grounded nMOS enters avalanche breakdown first.
⊲ Avalanche voltage is similar to gate-grounded nMOS (10V

approximately).

ESD Protection Circuits
• Requirements of ESD Protection Circuits :
⊲ Provide a low-impedance path from input pads to the ground during

an ESD strike to release the static charge accumulated on the pads.
⊲ Clamp the voltage of the pads at a level that is below the dielectric
breakdown voltage of thin transistors during an ESD strike.
⊲ Provide a very high impedance and a low capacitance during

normal operation such that it has a little effect on the operation of
the protected circuits.

ESD Protection Circuits
• Basic Configuration
Primary ESD Current Secondary ESD

Internal
PAD Elements limiting Elements
circuits
resistor
Figure 20: Configuration of ESD protection circuits
⊲ Primary ESD protection elements shunt most of ESD currents.

Primary ESD protection elements have large width and need more
time to turn on.
⊲ Secondary ESD protection elements serve to limit the voltage at the

circuit being protected until the primary ESD protection devices are
fully operational. Secondary ESD protection devices have smaller
width.
⊲ The effectiveness of the primary ESD protection devices is

determined by the secondary protection stage. Note that due to the
small dimensions, the secondary protection devices enter avalanche
breakdown before the primary protection devices are activated. It is
critical to ensure that the avalanche breakdown of the primary
protection devices is activated before the secondary protection
devices enter their thermal breakdown so that the secondary ESD
protection devices will not be destroyed by ESD stress.
⊲ Current-limiting resistor has two functions (i) limit the current

flowing into the internal circuits. (ii) withstand some ESD voltage
so that the secondary protection circuit will not be damaged in an
ESD strike.

ESD Protection Circuits (cont’d)
• Basic Circuits
R
Internal
PAD circuits
Current-limiting
resistor
Primary ESD elements Secondary ESD elements
Figure 21: Basic ESD protection circuits
⊲ Both nMOS and pMOS are used for positive and negative ESD
strikes.
⊲ Under normal operation conditions, ESD devices are off −→

minimize the leakage current of these devices.

• ESD of 0.35µm CMOS Processes
⊲ In sub-micron CMOS, the onset of damage has been observed at

between 1 kV and 2kV.
⊲ Design rules are set for 2 kV HBM and 200V MM.
⊲ Min. resistance of the isolation n-well resistor : 200 Ω.
⊲ Soft-pull is used to balance the breakdown voltage and the speed of

I/O fingers under ESD zapping.

• Distributed ESD Protection Circuits
⊲ De-centralize a large capacitance into a set of small capacitances

separated by inductors - a transmission line is constructed −→
capable of transmitting high-frequency signals.
zo zo zo zo
PAD Internal
circuits
z in
zo zo zo zo
PAD Internal
circuits
C C C C
Figure 22: Top - Distributed ESD protection with equal sections; Bottom - small-signal equivalent
circuit.

• Multi-Finger Turn-On (MFT)
⊲ Thermal breakdown voltage of each finger of a large ESD protection

transistor is made higher than the avalanche breakdown voltage of
the finger.
⊲ Lumped resistors are added at source and drain. The one at drain
functions as ballast resistors while the one at source sense the ESD
current and generates a voltage that is applied to the gate of the
adjacent finger −→ behave as a gate-coupled nMOS transistor −→
to initiate ESD protection earlier, better ESD protection.
PAD Internal
Rd Rd Rd Rd circuits
Rs Rs Rs Rs
Figure 23: Equivalent circuit of poly back-end ballast with segmentation.

• Soft-Ground-Gate nMOS MFT
⊲ Based on substrate pick-up technique −→ when an ESD strike

occurs, the potential of substrate increases because ESD currents
flow to the substrate. The gate potential increases subsequently −→
behaves as gate-coupled nMOS transistor that have a low avalanche
breakdown voltage (better ESD protection).
PAD Internal
Rs Rs Rs Rs
Figure 24: Equivalent circuit of a soft-grounded-gate nMOS MFT.

• Domino nMOS MFT
⊲ Lumped resistors are added at source and drain. The one at drain
functions as ballast resistors while the one at source sense the ESD
current and generates a voltage that is applied to the gate of the
adjacent finger −→ behave as a gate-coupled nMOS transistor.
PAD Internal
Rs1 Rs1 Rs1 Rs1
Rs2 Rs2 Rs2 Rs2

Macro-ballasting
resistors
Figure 25: Equivalent circuit of domino nMOS MFT.

References
⊲ For details on ESD protection and references, please read Chapter 8
of CMOS Current-Mode Circuits for Data Communications (Fei
Yuan, Springer : New York, 2007).

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ELE863/EE8501 VLSI Systems

Electrostatic Discharge Protection

Fei Yuan, Ph.D, P.Eng.

Copyright (c) F. Yuan 2009 (1)

• Principle Sources of ESD in ICs

• ESD Protection Mechanisms

• ESD Protection Devices

• ESD Protection Circuits

Copyright (c) F. Yuan 2009 (2)

⊲ ESD - Electro-Static Discharge.

⊲ ESD is a transient discharge of static charge that arises from either

⊲ Although ESD is the result of a static potential in a charged object,

⊲ Most ESD damages are thermally initiated in the form of device /

pn-junction may melt.

Gate oxide may have void formation.

Metal interconnects & Vias may melt or vaporization, leading to

⊲ Gate-oxide breakdown is another form of ESD damage.

Copyright (c) F. Yuan 2009 (3)

⊲ The aggressive decrease in physical dimensions and increase in

Figure 1: Scaling of gate oxide thickness of MOS transistors.

Copyright (c) F. Yuan 2009 (4)

Figure 2: Scaling of junction depth of MOS transistors.

Copyright (c) F. Yuan 2009 (5)

⊲ A person walking on a synthetic floor can accumulated up to 20 kV.

• Test and Handling Systems

⊲ Equipment can accumulate static charge due to improper

• IC Itself is Charged During Transport / Contact

Copyright (c) F. Yuan 2009 (6)

⊲ HBM models the ESD of a human body.

⊲ Peak current ≈ 1.3A, rise time ≈10-30ns.

Human body model

Copyright (c) F. Yuan 2009 (7)

⊲ MM models the ESD of manufacturing / testing equipment.

⊲ Peak current ≈ 3.7A, rise time ≈15-30ns, bandwidth ≈ 12 MHz.

⊲ ESD stress caused by charged machines is sever because of zero

Copyright (c) F. Yuan 2009 (8)

⊲ CDM models the ESD of charged integrated circuits.

⊲ Inductance in the model is mainly due to the inductance of bond

⊲ Peak current ≈ 10A, rise time ≈1ns.

⊲ Gate oxide breakdown is the signature failure of CDM stress, in

⊲ CDM stress is the most difficult ESD stress to protect against.

Charged device model

Copyright (c) F. Yuan 2009 (9)

• Avalanche Multiplication of pn-junctions

• First Breakdown (Avalanche Breakdown) of nMOS

• Second Breakdown (Thermal Breakdown) of nMOS

Copyright (c) F. Yuan 2009 (10)

⊲ Majority charge carriers in n-well resistors are free electrons.

⊲ At low voltages, the velocity of free electrons (majority charge

⊲ The total charge crossing a cross-section of area A per second is

Q = (vnn + vp p)Aq, (2)

where n and p are the concentration of free electrons and holes,

⊲ The current density is obtained from

σ = (nµn + pµp )q (4)

⊲ For n-type, the concentration of free electronics is approximately

J≈Jn = (nnµn E)q = nn vn q = σE (5)

J is linearly proportional to E or equivalently the voltage across the

Copyright (c) F. Yuan 2009 (12)

⊲ At high voltages, the velocity of free electrons saturates due to the

Jsat = nn vn,satq (6)

vn,sat ≈107cm/s, nn = 1017/cm3 −→ Jsat = 1.6×105A/cm2.

Figure 7: Velocity saturation