26 IBM Microelectronics First Quarter 2001

CMOS technology continues to be scaled to smaller dimensions, higher performance, and low-power dissipation.
Designers must understand the power/performance tradeoff to optimize their designs while minimizing off-state leakage
current. This article by Hargrove et al. and the article by Bernstein et al. that follows describe the optimal threshold voltage
selection for enhanced performance and a methodology for estimating the impact of technology scaling on total chip off-
state leakage current (Iddq).

A Methodology for Estimating Total Off-State Leakage

Current (Iddq) in CMOS Technology
Michael Hargrove, Andres Bryant, Suk Hoon Ku, Edward Nowak, and Melanie Sherony

As CMOS technology is scaled to smaller dimensions and leakage current are schematically represented. The total device
low-power product applications become more pervasive, leakage current, Ioff, is comprised of three major components:
designers must be able to accurately calculate the total off-
state leakage current (Iddq) and subsequent power dissipation • Device off-current I1
of their specific chip design. The result of this calculation is • Gate leakage I2
also critical in determining the specific tool requirements for
• Thermal and tunneling junction leakage I3
burn-in. This paper describes the derivation and physical
interpretation of the various leakage components that com-
prise the Iddq current for a given technology and product
design. The dependence of Iddq on device channel length,
power supply, and temperature is described, as well as the
Poly gate
methodology of incorporating across-chip linewidth varia-
tions (ACLV). Specific logic and SRAM design examples are
given, along with a discussion of both the assumptions used
to determine the total number of devices that are in an off-
I2
state configuration and the incorporation of low-Vt devices.
N+ I1 I3 N+
Introduction
CMOS technology is continually being scaled to smaller dimensions
and lower power-supply voltage to maximize performance and opti- Box
mize density. As CMOS devices are made smaller, the power-sup-
ply voltage (Vdd) must also be decreased to limit the amount of off-
state leakage current that devices will conduct. However, lower Vdd
P-substrate
implies degraded device performance unless the corresponding
device threshold voltage (Vt) is also decreased. Lowering the Vt
Figure 1. Cross section of a typical SOI MOSFET showing off-current
maximizes the overdrive voltage (Vg - Vt) which is directly propor-
leakage components.
tional to the device current drive; however, the device leakage cur-
rent (Ioff) increases. Therefore, scaling CMOS technology improves The device off-current, I1, is determined by the Lpoly and the
density, but also puts additional constraints on device design in channel width (W) of the device. It is comprised of device
order to maximize performance. channel current at Vg = 0 V, which is an exponential function
of Lpoly, and device corner current, which depends on the
As CMOS technology-scaling continues and low-power device width. Numerous measurements are made on
product requirements become more pervasive, it becomes devices with varying channel length and width to accurate-
extremely important that chip designers have the capability ly determine the correct exponential dependence of Ioff on
to accurately calculate the total off-state leakage current of Lpoly and the corner current dependence on W.
their specific chip design. This calculation begins by first
understanding the various components that comprise the The gate leakage current, I2, is determined by the gate-
specific CMOS device (NFET and PFET) leakage current. oxide thickness (Tox), Vdd, and the total gate area (Lpoly x W).
Once the device leakage components are identified, the Thin gate oxide can be a significant contributor to the total
functional dependence of the total device leakage current Iddq of a chip. Typical logic circuits employ the minimal-
on gate channel length (Lpoly), Vdd, and temperature can then design channel length for optimal performance; therefore,
be analytically described. The analytic description is then the gate leakage current is specified in terms of the total
used by designers to calculate the total off-state leakage device width (Wtotal) of NFET and PFET devices.
current (Iddq) of their specific chip.
The thermal and tunneling junction leakage, I3, is deter-
CMOS Device Leakage Components mined by the total doping level in the substrate and the tem-
A cross section of a typical silicon-on-insulator (SOI) CMOS perature. This leakage component is typically lumped into
device is shown in Figure 1. The various components of device the device off-current (I1).
IBM Microelectronics First Quarter 2001 27

Functional Dependence of Ioff Across-Chip Linewidth Variation (ACLV)

The device off-state leakage current, Ioff, also known as the sub- Every chip on a given wafer has a distribution of Lpoly centered
threshold leakage current, is a function of Lpoly, temperature (T), at the nominal design dimension Ldesign. This means that there
and power-supply voltage (Vdd). A typical Ioff plot as a function are a significant number of MOSFETs with Lpoly varying about
of Lpoly and temperature is shown in Figure 2. this mean by an amount described by the ACLV. The ACLV
accounts for the variation in Lpoly across a chip due to photoli-
10-6 thography and etch-bias variations. The ACLV distribution for a
105 °C/1.2 V given technology is determined by extensive measurements of
specifically designed structures that represent both the envi-
85 °C/1.2 V
ronment and orientation variations that can be encountered on
10-7 25 ¡C/1.2 V
a given chip layout. Integration of the ACLV distribution
(assumed to be Gaussian) with the Ioff equation (Equation 1) and
Ioff (A/µm)

accounting for the total device width on chip (Wtotal) results in

10-8 the total-chip standby current, Iddq. The resulting equation is
given by

Iddq(Ldesign) = Wtotal
10-9
[I1(T)e —
Ldesign/L1e0.5(σACLV/L1)2

+ I2(T)e —
Ldesign/L2e0.5(σACLV/L2)2]
10-10
0.06 0.08 0.10 0.12 0.14 (4)
n
Lpoly (µm)
+ WtotalA1 Vdd — Vdd (nom)
_____________

Figure 2. Typical device off-current (Ioff) vs. Lpoly at various temperatures.

0.5Vdd
[I1(T)e —
Ldesign/L3e0.5(σACLV/L3)2
As Lpoly decreases, Ioff increases exponentially. The functional
+ I2(T)e —
Ldesign/L4e0.5(σACLV/L4)2] ,
dependence of Ioff on Lpoly, T, and Vdd is given by

Lpoly/L1 + Lpoly/L2] where σACLV is one-third of the total dispersion in MOSFET Lpoly
Ioff = [I1(T)e —
I2(T)e —

about the chip mean, and L3 and L4 are functions of L1, L2, A1, and
(1)
[1 + A1e — Vdd —Vdd (nom) n
A2Lpoly( _____________
0.5xVdd (nom)
) ]. A2. The total tolerance on Iddq can range between 40% and 60%
for standard- and low-Vt NFETs and PFETs, respectively.
Technology-design manuals specify the exact values of all the fit-
The first two exponential terms in brackets describe the off- ting parameters discussed above and provide calculated exam-
state leakage current dependence on Lpoly and temperature, ples of Idd for specific nominal-design dimensions Wtotal and ACLV.
while the second bracketed term describes the Vdd depend-
ence. The premultipliers I1(T) and I2(T) describe the temperature Example Iddq Calculation
dependence and are given by Assuming a 0.13-µm CMOS technology, the nominal-design
channel length and corresponding Lpoly are specified, including
1 1 the σACLV. For a given chip design, the total NFET and PFET
I1(T) = I1(25°C)eB1(T°C+273°C 298°C)
_________________________ ____________
—

device width (Wn and Wp) are also known, as well as the nomi-
and (2) nal Vdd and associated power-supply tolerance. Typical values
1 1 for some of these parameters are given in Table 1.
I2(T) = I2(25°C)eB2(T°C+273°C 298°C)
_________________________ ____________
—
,
Table 1: Specified CMOS technology parameter values.
where I1(25 ºC), I2(25 ºC), B1, and B2 are fitting parameters. I1(25 Parameter NFET PFET
ºC) and I2(25 ºC) are the base leakage currents of the device and
Vdd (V) 1.2 1.2
are determined from measured data at 25ºC. The length scale
is determined by the ratio Lpoly/L1 (Lpoly/L2) in the exponential. It Tox (nm) 1.5 1.5
is also temperature-dependent, and given by Ldesign (µm) 0.125 0.125
Wtotal (µm) 5 x 106 5 x 106
and
(3)
L2 = L21 + L22(T - 25°C) . With this information, the total Iddq current can be calculated for
different use conditions and chip layout. For example, a micro-
The power-supply dependence is also an exponential function processor with 10-million logic and array peripheral transistors
of Lpoly and varies as a Vdd ratio raised to the power n. The func- and 36 Mb of SRAM would typically have 5-million PFETs and
tional form of the Ioff dependence on Lpoly, Vdd, and temperature 5-million NFETs. Assuming that the median device width for
is determined from hardware. The associated fitting parameters both NFETs and PFETs is 1 µm, the corresponding gate-current
are carefully fit to match the hardware results. (Igate) contribution would be calculated knowing the Igate
28 IBM Microelectronics First Quarter 2001

dependence on Wn and Wp and the operating voltage and tem- Figure 4 illustrates the impact of increasing the power-supply
perature. For a given oxide thickness, Vdd, and temperature, the voltage to the burn-in voltage. The higher Vdd increases Iddq by
corresponding Igate relationship is given as a factor of 5X.
100
Igate = IgnWn + IgpWp , (5) 140 °C/1.8 V
40 °C/1.8 V
25 °C/1.8 V
10
where Ign and Igp are NFET and PFET fitting parameters that

Total I Iddq (A)

match the measured gate-current data at the specified condi- w/Low-Vt
tions. Assuming Ign = Igp = 5 nA/µm for worst-case use condi- w/o Low-Vt
tions, the total gate current in the logic and array peripherals is 1
50 mA. Assuming the same device-level gate-current leakage in w/Low-Vt
the SRAM (5 nA/µm for each device, which translates into 10
nA/cell), the total SRAM Igate leakage would be 320 mA.
0.1
Therefore, the total Igate contribution to the worst-case Iddq
would be 370 mA. Given the technology parameter values in w/o Low-Vt
Table 1 and values for the various fitting parameters that com-
prise the Iddq equation, the chip leakage current is then calcu-
0.01
lated and added to the gate leakage component to obtain the 0.06 0.08 0.10 0.12 0.14
total chip Iddq for a given use condition specified by the design- Lpoly (µm)
er. Figure 3 shows the calculated total-chip Iddq vs. Lpoly at vari-
ous temperatures and nominal power supply, with and without Figure 4. Calculated Iddq current for an example microprocessor
low-Vt devices used in the logic. The elevated temperature sig- chip at burn-in power supply and various temperatures, with and
nificantly increases Iddq, as does the use of low-Vt devices. without low-Vt devices.
These results assume that one half of the total number of cell
devices in the SRAM are in an off-state condition and are there- Conclusions
by contributing to Iddq. A reasonable assumption for the total The accurate assessment of total chip leakage current is
number of logic devices not in an off-state condition is to extremely important as CMOS technologies are scaled to small-
assume that one-third of the devices are on while the remaining er dimensions and lower power. Understanding the leakage
two-thirds are off. components that comprise the Iddq and their dependence on
device channel length, power supply, and temperature is fun-
damental in achieving this accurate assessment. The method-
ology described in this paper can be implemented by designers
100 to simulate their specific chip design.

•••
140 °C/1.2 V
40 °C/1.2 V Michael Hargrove is a device design engineer in high-performance
10 CMOS technology at the IBM Semiconductor Research and
25 °C/1.2 V
Total I Iddq (A)

Development Center (SRDC) in Hopewell Junction, NY. He is currently

focused on device design issues for 70-nm CMOS technology.

1 Andres Bryant is a senior engineer working on device design and tech-

w/Low-Vt nology transfer in IBM Microelectronics, Essex Junction, VT. He is cur-
w/o Low-Vt rently responsible for technology transfer of the 0.13-µm-generation
high-performance SOI CMOS technology into manufacturing.
w/Low-Vt
0.1 Suk Hoon Ku is a device designer for high-end CMOS device design at the
SRDC in Hopewell Junction, NY. He is currently working on advanced SOI
CMOS design for the 0.13-µm generation.
w/o Low-Vt
Edward Nowak is a senior technical staff member at IBM
0.01
Microelectronics, Essex Junction, VT. He is currently responsible for
0.06 0.08 0.10 0.12 0.14
future technology definition, performance, and application.
Lpoly (µm)
Melanie Sherony is a device design engineer for high-performance
Figure 3. Calculated Iddq current for an example microprocessor chip at CMOS technology at the IBM SRDC in Hopewell Junction, NY. She is
nominal Vdd and various temperatures, with and without low-Vt devices. currently working on device design issues for SOI CMOS technology.