205

A Multiple-valuedSingle-Electron SRAM by the PADOX Process

Hiroshi Inokawa, Akira Fujiwara, and Yasuo Takahashi
hTT Basic Research Laboratories, hTT Corporation
3-1 Morinosato Wakamiya,Arsugi-shi,Kanagawa P&, 243-0198 Japan
Email: inokawa@aecl.ntt.co.jp

Abstract
(b) 3-terminal Id-VgP
Multiple-valued static memory consisting of a
single-electron transistor (SET) and a MOSFET is
proposed. The.memory operation is verified by using
transistors fabricated by the CMOScompatible
pattemdependent oxidation (PADOX) process. The
results indicate that a dramatic increase of CMOS
memory density can be attained by the use of a SET
with multiple-valued capability.

Introduction Fig. 1 (a) Schematic of the proposed multiple-valued memory.

(b) 3-terminal IcV, characteristics of a SET. (c) 2-terminal
In contrast to floating-gate singleelectron I-vcharacteristics of the combined SET-MOSFET circuit with
memories, such as nanocrystal memories [1-5], static the SET gate shorted to the MOSFET drain.
memories feature a fast simple write operation and
stable retention while the power is on. Thus we believe
that the static type will have a wide range of
applications different from those of the floating-gate
type. Multiple-valued operation has been reported for
floating-gate singleelectron memories [SI,but is not
exclusive,to that type of memory. We propose here a
multiple-valued static memory comprised of a
single-electron transistor (SET) and a MOSFET and
demonstrate its characteristics using transistors
fabricated by the pattemdependent oxidation
(PADOX)[6-81on the same silicon-on-insulator (SO0
wafer.

Fig. 2 (a) A possible layout of the integrated SET and

Principle of Operation
Figure l(a) is a schematic of the proposed
multiple-valued static memory. The source of a
MOSFET with fixed gate bias V, is connected to the
drain of a SET. As illusmted in Fig. l(b), the SET'
drain current I,+increases and decreases periodically as
a function of the gate voltage V , [9-111. However, the
Id has such large dependence on the drain voltage V,
that the peak current is almost proportional to the V,,
and the valley current increases more rapidly when the
Coulomb-blockade condition breaks. The MOSFET
c o ~ e ~ t etod the SET eliminates this large V,
dependence of the SET characteristics by keeping the
V , nearly constant around V=-V&. where V, is the
threshold voltage of the MOSFET. This V,-V, is set
MOSFET. (b) Circuit diagram corresponding to the layout
above. (c) Potential profile along the length of the narrow wire
where, a SET is created [8].
low enough to sustain the Coulomb-blockade
condition. By connecting the SET gate to the
MOSFET drain, the multipeak negative differential
resistance characteristics shown in Fig. l(c) are
obtained as 2-terrninal I-V characteristics. If a
constantarrent source I,, is connected to the
SET-MOSFET circuit, the periodic nature of the I-V
characteristics results in a number of stability points, .
and this enables the multiple-valued memory
operation.

0-7803-6520-8/01/$10.000 2001 IEEE.

206

71 1

30 '4
%T 20
Y

p
-
.

10
n v o
"1 2 3 4
"w 0 measured at 1.08 V of . V Stability points (a-f) expected for
Fig. 3 I,V, (3-terminal) characteristics of a SET fabricated by
PADOX [MImeasured
, at 27 K and 10 mV of V,.
l(r
10.4
T small shift due to the drain voltage, which are suitable
3 106
10-10
10-12
0.5 1 1.5 2 2.5
"e9 0 characteristics originate from the characteristics of a
Fig. 4 IcV, characteristics of a MOSFET fabricated OR
same SO1 wafer for the above SET,measured at 27 K.
EXpehents
Both the SET and the MOSFET were fabricated on
a thin silicon-on-insulator (SOI) layer. A possible
layout and the corresponding circuit diagram of the
integrated SET and MOSFET are shown in Figs. 2(a)
and (b). The SET is creiited in a narrow wire region by
pattemdependent oxidation (PADOX) [6-81. The
quantum size effect raises the potential in the wire, but
in the middle of the wire the high compressive stress
generated by the oxidation reduces the bandgap pig.
2(c)] [8]. This creates two tunnel barriers and an island
sandwiched between them, which constitute a SET.
Since the areas outside the wire can easily be used for
MOSFETs, PADOX is highly compatible with the
CMOSprocess.
Figure 3 shows the IKVp characteristics of a SET.
Periodic draincurrent peaks are clearly seen along
with the effect of tunnel resistance modulation by the
gate voltage. From this figure and a Coulomb diamond
plot, gate capacitance, sourcddrain capacitance, and
I
2 3 4 5
Fig. 5 I-V (2-tenninal) characteristics of the proposed circuit
,
the current load of 4.5 nA are also shown.
tunnel resistance were calculated to be 0.27 aF,2.7 aF,
and 80-220 kn,respectively.
Figure 4 shows the subthreshold characteristics of
a MOSFET fabricated on the same SO1wafer for drain
voltages of 5 V and 10 mV. The gate length, width and
the gate oxide thickness are 14 pm, 12 pm and 90 nm,
respectively. The device exhibits a sharp cutoff and a
for the proposed application.
Figure 5 shows the I-V characteristics of the
combined SET-MOSFET circuit. The current
increases and decreases periodically, reflecting the 2,
V, characteristics of the SET (Fig. 3). If a current
3 source of 4.5 nA is C O M W ~to~ the ~ circuit, stability
points a-f should appear. Note that these multipeak
the single SET, and the number of peaks is infinite in
principle. This is an amactive feature of the device,
and is not available in other negative-resistance device
like resonant-tunnelingdiodes (RTDs) [12-14]
Memory operation was confirmed by current
sweep measurements, which are shown in Fig. 6. If the
current starts from stability point a and increases, the
voltage jumps when the current exceeds the second
peak in the I-V characteristics (Fig. 5). If the current
sweep is reversed at this moment, stability point b can
be reached. Other stability points, c-e, can also be
reached by choosing higher current-sweep reversal
points. Note that stability point f cannot be attained by
this current-mode operation, because the last peak in
the I-V characteristics (Fig. 5) is lower than the
previous one. Direct access to any stability point can
be made by the voltage-mode operation exemplified in
FCEl memory devices [12].
Discussion
Here we discuss the two major issues in large-scale'
memory applications, i.e. cell area and operating
speed.
 207

5 WL 1 -

E
s3

2 BL

1
2 4 6 8
I (nN
Fig. 7 (a) A multiple-valued singleelectron SRAM cell with
Fig. 6 current Sweep n m ~ ~ ~ m of e nthe
B PrOPO~memory. two depletion-mode MOSFETs (M1 and M 2 ) and one
The complianceof the curient source is 5 v. enhancement-mcde MOSFET (M3). (b) An example of the
SRAM layout.

Table 1 Comparison of cell shuchues to improve the operating speed of the multiple-valuedSRAM.

WL

I
wl storage capacttor I wl readout Trs.
5 I 6 II

Destrudlve Nobdestrudlve

Multlplevalued DRAM Multlplevalued Flash

Figure 7(a) shows a four-transistor memory cell as
a practical design. A depletion-mode grounded-gate
MOSFET M1 is used to sustain the SET drain voltage
around the absolute threshold voltage of M1.Another
depletion-mode MOSFET, M2, with its gate and
source shorted serves as a current source, and
pass-transistor M3 controls the access to the cell. In
write operation, the voltage applied to the bit line (BL)
is transferred through M3, and is quantized to a
stability point after M3 is cut off. As described in the
previous section, any stability point can be directly
reached by this voltage-mode operation. Figure 7(b)
shows an example of the cell layout. It has an area of
31.19, where F is half the minimum wiring pitch.
Thus this cell not only has a multiple-valued function,
but is much smaller than an ordinary 6-transistor
SRAM cell.
The write-in speed of the proposed SRAM should
be fast since the capacitance connected to the memory
node (the crossing point of the three MOSFET
terminals) is comparable to that of the ordinary SRAM,
and that associated with the SET is very small (-aF).
The read-out speed of the original cell [Fig. 7(a)] is
slow, because the current that can be supplied to the
bit line (BL)without deseoying the memory status is
less than a nanoampere, as can be understood from Fig.
5. If we assume the bit line capacitance of 100 fF and
a voltage swing of one volt, the read-out speed
becomes of the order of 100 p.
To improve the read-out speed, we considered two
208
additional cell structures (Table 1).
If we add a storage capacitor C, to the memory
node as shown in the center column of Table 1, the
charges stored in C, can be driven out to the BL in a
short time. The small voltage difference on the BL is
read by a sense amplifier. The speed should be
comparable to that of multiple-valued DRAM [15].
Although the read-out operation is destructive, the data
can be refreshed immediately by the sense amplifier,
and of course the proposed SRAM does not require
periodic refreshing. Also note that the area penalty due
to the storage capacitor is negligible, since the area
above the storage node is open in the proposed cell
Fig. 7co)i.
Another way to improve the speed is to add
MOSFETs specialized for read+ut operation (See the
right column of Table 1). M4 converts voltages at the
memory node to current levels, and M5 controls the
access from the sense line (SL).By using a special
read-out scheme, such as parallel charge sensing,
speed comparable to that of multiple-valued flash
memory [16,17] should be attainable. Although this
cell structure enables nondesauctive read-out, the cell
area is sacrificed considerably due to the increased
number of transistors.
Conclusions
We have devised a novel multiple-valued SRAM
comprised of a SET and a MOSFET, and verified the
basic operation using devices fabricated by
silicon-based PADOX technology. Discussion of the
SRAM cell design and its operating speed revealed
that the area should be much smaller than, and the
speed should be comparable to that of conventional
memories. The results open up the possibility of
dramatically increasing the memory density of future
scaled-down CMOS.
Acknowledgments
We thank Dr. Yukinori Ono for helpful discussions,
and technical advice in electrical measurements.
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