Power Consumption Optimization Of Dynamic

Comparators
Jhoan Salinas, Student Member IEEE1,2 Héctor Gómez, Student Member IEEE1,2
Ricardo Astro, Student Member IEEE1,2 and Elkim Roa.1,3
1
Research Group on Integrated Circuits Design CIDIC − Universidad Industrial de Santander − Colombia
2
Instituto Nacional de Astrofı́sica, Óptica y Electrónica − México
3
Purdue University − United States of America
Emails: {hgomez, jsalinas, rastro}@inaoep.mx, elkim@purdue.edu

Abstract—This paper makes a comparison of some dynamic (denoted by τlacht ). However the additional area occupied by
comparators and gives a conclusion about which one is more the inductors can be unacceptable for applications that require
suitable for analog to digital converter architectures with a a large numbers of comparators.
large number of comparators such as a pipeline or flash. The
comparison was developed in AMS 0.35 µm CMOS process In this paper a revision of the most common dynamic
applying a design strategy based on geometric programming as comparators allows some useful conclusions about what ar-
an optimization tool. The circuits simulated in HSPICE with chitecture gives the best power/speed ratio. These conclusions
a level 49 BSIM3v3 transistor model, shows that Kobayashi’s are obtained after designing each architecture using geometric
topology achieved the best FOM value with 457 f W/Hz, while programming as an optimization tool. This paper is organized
the proposed circuit achieved a value of 582.7 f W/Hz operating
at 1.19 and 1 GHz respectively. as follows: Section II reviews the operation of Kobayashi’s
Index Terms—Low Power, Dynamic Comparator, Analog to comparator. Section III illustrates Goll’s topology. The pro-
digital conversion, Geometric Programming. posed circuit is described in section IV. Simulation results of
all architectures are presented in section VI. Finally, in Section
I. I NTRODUCTION VII some conclusions are depicted.
Comparison is a fundamental operation in the performance
of an analog-to-digital converter (ADC). A comparator is a II. KOBAYASHI ’ S A RCHITECTURE
circuit which by a logic level indicates whether a voltage or In Figures 1 and 2, the Kobayashi’s topology [1] and a
current signal is greater than another. In architectures such as typical transient response of the output voltages are shown.
flash and pipeline that use many comparators, the behavior of When the clock is low, after the transient responses have
this latter limits its specifications such as power consumption, ceased, there is not a significant current flow and leakage
speed, area and resolution. currents dominate the power consumption [4]. Switches M7
The main issues in comparator design is the direct depen- and M8 pulls Voutp and Voutn toward VDD , leaving the
dence between power consumption and operating speed, as comparator in equilibrium, ready to decide.
well as how a larger resolution generally requires the use of Wicht developed a transient analysis and provided ex-
pre-amplifiers, that deteriorates the maximum operating speed pressions for the decision stage of this topology [4]. When
and increase both of area and power consumption.
Typically positive feedback has been used to force a quick
decision. In order to avoid hysteresis, the comparators should VDD
be controlled by an external clock which handles some
switches that lead the circuit to a metastable state before any Clk M7 M2 M4 M8 Clk
decision. Each clock state corresponds to a mode of circuit
operation: decision and reset. −
Vout
+
Vout M1 M3
In order to minimize power consumption, dynamic com-
parators are well known as the best option because of their IN IP
operation based in deciding and stopping consume. Nowadays, Vin− M5 M6 Vin+
one of the most popular architectures is based on a structure
called sense amplifier, proposed by Kobayashi [1]. In addition
there are topologies that attempts to reduce capacitance on Io
the output node. For example Goll [2] merges reset function in Clk M9
PMOS transistors of the latch in order to reduce output capac-
itance. Park [3] uses integrated inductors so as to compensate
capacitive effect and to improve regeneration time constant Fig. 1. Kobayashi’s comparator [1].
 M3 and M4 [5]. Despite the decision process being a large-
signal operation, the estimated parameters of the small-signal
model do not introduce large errors in the evaluation of tlatch
[3].
Output

gm,ef f = gm3 + gm4 − gds3 − gds4 (4)

The latch finishes its intervention when M1 or M3 turns
off. In steady state the current consumption is interrupted
minimizing the static power consumption.
Fig. 2. Simulated transient response for the circuit of Figure 1.
To finish the mathematical description, the decision time
ttotal is estimated from equations (1) and (3) as follows:
ttotal = to + tlatch . (5)
transistor M9 turns on, two phases of decision are defined.
The first one occurs when transistors M5 and M6 discharge III. G OLL’ S A RCHITECTURE
+ −
outputs Vout and Vout , while M2 and M4 are off. The required The topology is shown in Figure 3. As it can be observed the
time to discharge the output node, with an equivalent parasitic modification of conventional latch using the PMOS transistors
capacitance CL , from VDD to VDD − Vthp , is known as to . as both active loads and reset switches avoids the use of
It can be observed that at time to transistors M2 and M4 are additional transistors that contribute to the capacitive load in
turned on. In Equation (1) an approximation for to assuming the output nodes.
a constant value for CL is shown, where Vthp corresponds to When the clock is low, the output nodes are pulled toward
the threshold voltage of M2 , and Io is the drain current of VDD , because M10 and M11 operate in triode while M0
M9 . It should be noted that Io depends on the input common and M1 are turned off. In comparison mode (clock high),
mode voltage VCM and the supply voltage VDD . transistors M0 and M1 are turned on while M10 and M11
CL Vthp 2 CL Vthp act as active loads, since the transistor M8 provides a gate
to = = . (1) voltage Vclk −Vth8 . Now output nodes are pulled toward VDD ,
IP Io
therefore M6 and M7 are turned on while M2 and M3 have
An input voltage difference ∆Vin causes an imbalance a gate voltage close to VDD . This enables the comparator to
in drain currents of M5 and M6 (IN and IP ), and in the operate at a reduced supply voltage [2]. The latch regenerates
+ −
discharging speed of Vout and Vout . This gives rise to an the output depending on the input voltage difference between
output voltage difference Vo which is regenerated by the latch M4 and M5 . In order to reduce the static current flow once
in the second phase. Equation (2) estimates the value of Vo , the decision ends, transistors M6 and M7 are located below
where β5,6 is the transconductance parameter of M5 and M6 M4 and M5 . They interrupt the current flow in one branch
respectively. depending on which of the output nodes go to zero.
+ −
A similar analysis can be used to calculate the decision
Vo = | Vout (t = to ) − Vout (t = to ) | time. The main difference lies in the activation of the entire
IN to circuit (differential input pair and latch) in comparison phase,
= Vthp −
CL enabling a higher download speed of the output nodes, allow-
IN ing to reduce the delay in the first phase. The latch time is
= Vthp (1 − )
IP improved due to the fact that the reset transistors does not
r
8β5,6
= Vthp ∆VIN . (2)
Io VDD
Tbias
In (3), it is estimated the time required for the latch to re- M8 M 10 M 11
generate a voltage difference ∆Vout from the initial difference
Vo [5]. Nwell
−
Vin−
+
Vin+ Vout Vout
CL ∆Vout M4 M5
tlatch = ln M2 M3
gm,ef f Vo M6 M 7 CL CL
s !
CL 1 Io ∆Vout
= ln . (3) Io Io
gm,ef f 2Vthp 2β5,6 ∆VIN
M0 M1
In (3) the effective transconductance of the inverter formed Clk
by M1,3 and M2,4 corresponds to the expressed in (4) in
terms of drain-source conductance and transconductance of Fig. 3. Goll’s architecture [2].
load the output node. However, in the reset phase the PMOS each node giving solvency for the reset stage. To select W10
transistors (used as active loads in the previous stage) take the same criterion than in Goll’s design is used.
the output signals to VDD and prepare the circuit for a new The realised analysis to find expressions for decision and
decision. Accordingly, the sizes of these transistors must be reset times is similar to the others topologies. The decision
large enough to achieve an enough current flow, allowing to time of the first phase in the comparison to extends from
fulfill in a right form as both active load and reset switches, clock’s high logic level until either M2 or M4 cross through
the latter being the most critical. Nevertheless, the size of M10 the triode-saturation region’s edge.
and M11 limits the response speed since the increment in their
V. G EOMETRIC P ROGRAMMING
width increases the load capacitance.
To study the delay, it can be assumed that the transistors Geometric programming (PG) is a kind of non-lineal
M0 , M4 and M5 form a differential pair with input ∆Vin mathematical optimization problem where the functions in-
(disregarding M6 and M7 ) and the transistors M1 , M2 and volved are restricted to be monomials and posynomials of
M3 form another differential pair with input ∆Vout . You may the optimization variables [6]. A monomial is a function
find the voltage difference in time function like: f (x) = cxa1 1 xa2 2 . . . xann , where c ≥ 0 and ai is any real num-
p p t ber; the posynomials are composed by the sum of monomials.
∆Vout (t) = ( 2β5 Io ∆Vin + 2β2 I1 ∆Vout (t)) (6) A geometric program has the standard form:
CL
and doing
2CL Vdsat minimize f0 (x) (9)
to = (7) subject to fi (x) ≤ 1, i = 1, . . . , m (10)
Io + I1
the time in which M11 transistor comes in saturation region. gi (x) = 1, i = 1, . . . , p (11)
 √ 
CL (I0 + I1 − 2Vdsat 2β2 I1 )∆Vout where f0 is the objective function, fi is an inequality con-
tlatch = ln √ (8)
gm,ef f 2Vdsat 2β5 Io ∆Vin straint, gi is an equality constraint and x = (x1 , . . . , xn ) are
optimization variables. f0 and f1 , . . . , fn can be monomial
IV. P ROPOSED CIRCUIT
or posynomial, but equality constraints are restricted to be
The strong dependence of the decision time with regard to monomials.
load and download from output node shows the requirement In the Table I it is shown the PG formulation for
for keeping low the associated capacitance to this node. A Kobayashi’s topology. Here it can be observed how the re-
revision to Kobayashi’s topology show that the capacitive load
associated to one output node is given by five transistors.
Whereas in the Goll’s topology the reset transistors are ad- Minimize Power
2
P = CL VDD
ditional capacitive loads generating an increment in the total
output capacitance with regard to previous topology. Consid- Subject to
ering the first case, the Kobayashi’s topology is modified to Wr = W W9
5
Wp = W W2
1
Ws = W7
load the output node with only three transistor as it is shown Cl1 = k1 (W5a11 )(Wra12 )(Waa13 )(Wpa14 )(Wsa15 )
Cl2 = k2 (W5a21 )(Wra22 )(Waa23 )(Wpa24 )(Wsa25 )
in Figure 4. With the proposed change, the required effort to
Cl3 = k3 (W5a31 )(Wra32 )(Waa33 )(Wpa34 )(Wsa35 )
load the output nodes is reduced achieving an increment in tr1 = r11 (W5r12 )(Wrr13 )(Wnr14 )(Wpr15 )(Wsr16 )
the operation frequency for the same power consumption. tr2 = r21 (W5r22 )(Wrr23 )(Wnr24 )(Wpr25 )(Wsr26 )
The circuit operation is similar between architectures, how- tr3 = r31 (W5r32 )(Wrr33 )(Wnr34 )(Wpr35 )(Wsr36 )
ever the additional transistors, M7 and M8 , inject current in Cl1 ≤ CL
Cl2 ≤ CL
Cl3 ≤ CL
tr1 ≤ td
VDD tr2 ≤ td
Tbias tr3 ≤ td
Io = K(W5b1 )(Wrb2 )(Vcm b3 )
M2 M4 p2
gmp = Kp (( I2o )p1 )(Vds1 )(W2p3 )(Lp4 )
Clk
M10 gmn = Kn (( I2o )n1 )(Vds2
n2 )(W n3 )(Ln4 )
1
−1
+ − 2vthp CL Io ≤ to
Nwell Vout M1 M3 Vout −0.5 −0.5
q A
Io ( 22 )
tla = 0.5CL (gmp )(gmn )A1 ( 8∗kL ( Vdvout Vin
))A2 ( W )
Clk M7 M8 Clk q nm5 thp 5
A
−0.5 −0.5 Io ( 24 )
tlb = 0.5CL (gmp )(gmn )A3 ( 8∗kL ( Vdvout ))A4 ( W )
nm5 thp Vin 5
Vin− M5 M6 Vin+ tla + tlb ≤ tlatch
1
tlatch + to ≤ 2f
td ≤ treset
Io 1
Clk treset ≤ 2f
M9
TABLE I
C ONSTRAINTS OF THE GEOMETRIC PROGRAM .
Fig. 4. Proposed architecture.
striction of time to is directly converted into a monomial. output transient responses of each topology are shown. The
However, the equation (3) for tlatch is not compatible with transient waveform for Kobayashi’s topology presents a strong
the PG because of a logarithmic dependence. The selected charge-injection in the beginning of comparison stage due to
alternative for overcoming this problem is approximating the
logarithm function in a certain interval of interest with an
equation of the form:

ln(x) ' A1 xA2 + A3 xA4 . (12)

The current Io and the transconductances gmn and gmp are
modeled with monomials, whose settings present an error less
than 10% in the range for W from 1 to 20 µm. Otherwise, the
reset time treset and load output capacitance CL are modeled
with max-monomial functions due to the large error obtained (a) Input voltage.
with monomials-only modeling.
The PG formulation of the others topologies is similar to the
presented and is not shown. The obtained dimensions in the
solution of the geometric program are shown in the Tables II,
III and IV. It should be noted that the operation frequency
restriction is fixed at 1 GHz@CL =10 fF.
VI. S IMULATION R ESULTS
The values obtained in the PG solution can not be im-
plemented in a real layout. Considering this, the dimen-
sions are rounded off to integer multiples of lambda for the
AMS 0.35 µm CMOS process. In the Figure 5 the input and
(b) Transient response of Kobayashi’s comparator.
Kobayashi’s topology
Var. PG [µm] Adj. [µm] Var. Value Units
W1 1.00 1.00 Power 544.1 µW
W2 1.00 1.00 to 154.5 ps
W5 3.32 3.325 tlatch 265.5 ps
W7 3.10 3.10 treset 345.3 ps
W9 3.32 3.325
TABLE II
DIMENSIONS AND SPECIFICATIONS OBTAINED .

Goll’s topology
Var. PG [µm] Adj. [µm] Var. Value Units
W0 1.00 1.00 Power 816.6 µW
W1 1.22 1.225 to 157.9 ps (c) Transient response of Goll’s comparator.
W2 2.44 2.45 tlatch 178.2 ps
W4 1.00 1.00 treset 455.2 ps
W7 1.00 1.00
W10 4.20 4.25
TABLE III
DIMENSIONS AND SPECIFICATIONS OBTAINED .

Proposed topology
Var. PG [µm] Adj. [µm] Var. Value Units
W1 1.00 1.00 Power 583.7 µW
W2 1.68 1.675 to 190.1 ps
W5 3.00 3.00 tlatch 252.9 ps
W7 1.00 1.00 treset 499.1 ps
W9 3.00 3.00
(d) Transient response of proposed topology.
TABLE IV
DIMENSIONS AND SPECIFICATIONS OBTAINED .
Fig. 5. Transient reponse of each comparator operating at 1 GHz.
the parasitic capacitances associated to reset transistors. This is
not the case for the other topologies where this effect is notably
reduced since these transistors are not directly connected to
output nodes.
The performance of the comparison depends on to + tlatch
as treset . Therefore the greatest of these times is the limiting
factor for the maximum operation speed. Considering this,
the fastest comparator is the Kobayashi’s topology, besides to
have the lowest power consumption. The proposed and Goll’s
topology have a similar performance with regard to speed,
power consumption and overshoot.
To compare the performance of the different topologies
in an accurate form the ratio power/frequency is used. With
this measure, Kobayashi’s, Goll’s and the proposed topology
obtained a figure of merit (FOM) of 457 f W/Hz, 743.4 f W/Hz
and 582.7 f W/Hz respectively.
VII. C ONCLUSIONS
In this article a comparative study between two different
dynamic architectures of comparators was realised in order to
determine which is more suitable for ADC considering the
speed/power ratio. After realizing the designs using the geo-
metric programming as optimization scheme for the different
architectures, it was concluded that the Kobayashi’s topology
is the best.
Despite the reduction of the output capacitance in the
proposed architecture, it could not reach the same performance
than Kobayashi’s circuit because the stacking reduced the
current capacity of transistors.
The Goll’s architecture could not to reach the reported
performance in [2] due to the impossibility for implementing
low-Vth transistors in AMS C35B4C3 process, avoiding to
reduce the output capacitance without decreasing the current
capacity.
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no. 4, pp. 523–527, Apr 1993.
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0.5V at 600MHz and 1.5V at 6GHz,” ISSCC Dig. Tech. Papers, pp. 316–
317, 2007.
[3] S. Park and M. P. Flynn, “A Regenerative Comparator Structure With
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1926, 2006.
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