ANU School of Engineering

ENGN 2218 Electronic Systems and Design

Problem Set #04 Comparator Circuits

Q1
Consider the circuit shown in Figure 1.
Assume R1 = 50 kΩ, R2 = 50 kΩ, +VCC = 5 V, −VEE = −5 V, |Vout(max) | = power supply voltage.
(a) Derive expressions for upper and lower trigger points of the comparator.
(b) Sketch the output if vin = 5 sin(2π1000t).

vin
vout

R1 R2

Figure 1: The circuit for Question 2.

Q2
Consider the circuit shown in Figure 2.
Assume R1 = 50 kΩ, R2 = 50 kΩ, R3 = 100 kΩ, +VCC = 10 V, −VEE = −10 V, Vre f = 5 V, |Vout(max) | =
power supply voltage.
(a) Derive expressions for upper and lower trigger points of the comparator.
(b) Sketch the output if vin = 5 sin(2π1000t).

vin vout

Vref R2 R3
R1

Figure 2: The circuit for Question 3.

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Q3 (Non-assessable)
Consider the circuit shown in Figure 3.
Assume R1 = 50 kΩ, R2 = 50 kΩ, +VCC = 15 V, −VEE = −15 V, VZ = 4.7 V, VD = 0.7 V.
(a) Find the bounded maximum output voltages.
(b) Find values of upper and lower trigger points of the comparator.
(c) Sketch the output if vin = 6 sin(2π1000t).

Z1 Z2

Rc
vin vout

R1 R2

Figure 3: The circuit for Question 3.

Q4 (Non-assessable)
Consider the circuit shown in Figure 3.
Assume R1 = 10 kΩ, R2 = 47 kΩ, +VCC = 15 V, −VEE = −15 V, VZ = 4.7 V, VD = 0.7 V.
(a) Find the bounded maximum output voltages.
(b) Find values of upper and lower trigger points of the comparator.
(c) Sketch the output if vin = 3 sin(2π1000t).

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ENGN 2218 Electronic Systems and Design

Problem Set #04 Solution

Q1
Partial Solution
The given circuit data is R1 = 50 kΩ, R2 = 50 kΩ, +VCC = 5 V, −VEE = −5 V, |Vout(max) | = power supply
voltage.

vin
vout

R1 R2

(a)

R1
VUT P = V
R1 + R2 out(max)
R1
VLT P = − V
R1 + R2 out(max)
See Lecture 06 for complete derivation steps.

(b)

VUT P = 2.5 V
VLT P = −2.5 V

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The sketch of output voltage is shown below:

6
Input
Output
4

Voltage (V) 2

−2

−4

−6
0 0.5 1 1.5 2
Time (s) x 10
−3

Figure 4: Comparator output voltage vout (t).

Note: the trigger points where output changes state are highlighted by a black dot.

SEE MATLAB: L13_Example03.m and PSPICE:L13_Example03.sch.

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Q2
Solution
The given circuit data is R1 = 50 kΩ, R2 = 50 kΩ, R3 = 100 kΩ, +VCC = 10 V, −VEE = −10 V, Vre f = 5 V,
|Vout(max) | = power supply voltage.

vin vout

Vref R2 R3
R1

(a)

R R
VUT P = Vre f + Vout(max)
R2 R3
R R
VLT P = Vre f − Vout(max)
R2 R3

where R = R1 ||R2 ||R3 .

(b)

R = 20 kΩ
VUT P = 4V
VLT P = 0V

The sketch of output voltage is shown below:

10 Input
Output

5
Voltage (V)

−5

−10
0 0.5 1 1.5 2
Time (s) x 10
−3

Figure 5: Comparator output voltage vout (t).

Verify using PSPICE P04_Q02.sch.

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Q3
Partial Solution
The given circuit data is R1 = 50 kΩ, R2 = 50 kΩ, +VCC = 15 V, −VEE = −15 V, VZ = 4.3 V, VD = 0.7 V.

Z1 Z2

Rc
vin vout

R1 R2

(a)
The circuit is a double-bounded Schmitt Trigger. One zener is always forward biased when the other one is
in breakdown. We have

Vout = v− ± 5 (VZ +VD = 4.3 + 0.7 = 5)

v− = v+ (summing point constraint due to feedback arrangement)
∴ Vout = v+ ± 5 (1)
Apply KCL to non-inverting pin,
v+ −Vout v+ − 0
+ = 0
R2 R1
V
v+ =  out 
1 + RR21
Vout
v+ = (2)
2
Substituting in (1)
Vout
Vout = ±5
  2
1
1− Vout = ±5
2
±5
Vout = = ±10 V
0.5
Hence Vout(max) = ±10 V.

(b)
The trigger points are
R1
VUT P = V =5V
R1 + R2 out(max)
R1
VLT P = − V = −5 V
R1 + R2 out(max)

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(c)
The sketch of output voltage is shown below:

10 Input
Output

5
Voltage (V)

−5

−10
0 0.5 1 1.5 2
Time (s) x 10
−3

Figure 6: Output voltage vout (t).

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Q4
Solution
The given circuit data is R1 = 10 kΩ, R2 = 47 kΩ, +VCC = 15 V, −VEE = −15 V, VZ = 4.7 V, VD = 0.7 V.

Z1 Z2

Rc
vin vout

R1 R2

Vout(max) = ±6.55 V
VUT P = 1.15 V
VLT P = −1.15 V
The sketch of output voltage is shown below:

10
Input
Output
6.55
5
Voltage (V)

1.15
0
−1.15

−5
−6.55

−10
0 0.5 1 1.5 2
Time (s) x 10
−3

Figure 7: Output voltage vout (t).

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