Lecture 13
18-322 Fall 2003
2
Why worry about power?
-- Heat Dissipation
Handhelds
Portables
Desktops Servers
Power Density Trends
Getting that heat off the chip and out of the box is
expensive
A Booming Market: Portable Devices
What we would need…
50
Up to 1 month of uninterrupted 0
operation! 65 70 75 80
Year
85 90 95
= CL * Vdd2 * P0→1* f
Switching activity (factor)
= CEFF * Vdd2 *f on a signal line
P = CL(Vdd2/2) fclk sw
C EFF = Effective Capacitance = C L * P 0→ 1
A Out
B P(Out =1) = ?
P(0->1) = ?
Power Consumption is Data Dependent
A Out
B P(0->1) = ?
A In this case, Z = B as it
X
can be easily seen.
B The previous analysis
Z
simply fails because
the signals are not
independent!
Reconvergence
B Z
C
X wasted power
Z
Unit Delay
Example: A Chain of NAND Gates
out1 out2 out3 out4 out5
1
...
6.0
out8
4.0 out6
out4
V (Volt)
out2
2.0
out1
out3
out5
out7
0.0
0 1 2 3
t (nsec)
Glitch Reduction Using Balanced Paths
0 mismatch
F1 0
1 F1 1
F2 0
0 2
F3
0 F3
0
0
F2 1
0
C LVDD
t pLH =
k n (VDD − VTn )
2
number of transitions/cycle)
6.50
6.00
5.50
⌧ Very data dependent
N O R M A L IZ ED D E L A Y
5.00
(real-delay) 4.00
3.50
2.50
microcoded DSP chip
⌧ Lowering only f decreases 2.00
1.50 adder
average power, but total energy 1.00 adder (SPICE)
worse V
dd
(volts)
Using parallelism (1)
Pref = CrefVDD2fref
fpar = f/2 (tp,new = (50)ns => VDD ~ 2.9V; VDD,par = 0.58 VDD)
Ppar = CparVDD2fpar = 0.36 Pref
Using pipelining
Cpipe = 1.15C
Delay decreases 2 times (VDD,pipe = 0.58 VDD)
Ppipe = 0.39 P
Chain vs. balanced design