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1

Mehmet Serdar Teke


ID:260701050

PSPICE PROJECT-1

Part a

PSPICE BIAS POINT ANALYSIS:

DC Results of Pspice: DC Results found by my calculation:

IB=10.95uA IB=10.17uA
IC=1.837mA IC=1.73mA
IE=1.848mA IE=1.74mA
VB=2.508V VB=2.34V
VC=8.571V VC=8.945V
VE=1.848V VE=1.74V
Output file for Bias Point Analysis:
R_R1 N03617 N00802 3.5k
R_R2 0 N00739 1k
R_R3 0 N00521 22k
R_R4 N00521 N00802 100k
R_R5 N001171 N00478 1k
C_C1 N001171 N00521 10u
2

C_C2 0 N00739 3u
Q_Q1 N03617 N00521 N00739 Q2N2222
V_V1 N00802 0 15Vdc
V_V2 N00478 0
+SIN 0 0.025 1k 0 0 0

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

(N00478) 0.0000 (N00521) 2.5075 (N00739) 1.8478 (N00802) 15.0000

(N03617) 8.5712 (N001171) 0.0000

Part b
INPUT SIGNAL:
40m V

0V

-40mV
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(R5:2)
Time

OUTPUT SIGNAL:

10V

9V

8V

7V
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(Q1:c)
Time

Part c
VO/VS in dB:
3

200

100

-100
10mHz 100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz
20*log(V(Q1:c)/V2(R5))
Frequency

CONCLUSION
Hand calculated results of DC points are a little bit different than the reults calculated
by Pspice. This might be because of β value of the transistor or because of the approximations
that i made to make calculations easier.
There is a phase difference between input and output signals. This phase difference is
almost 180 degrees because of coupling capacitor between input and base. If there was
another coupling capacitor between collector and ouput, there would be no phase difference
since there are two capacitors while going from input to output. (In this situation, each
capacitor causes 180 degrees of phase difference and actually 360 degrees of phase difference
occurs since there are two capacitors which means there is no difference in phase between
input and ouput signals.) The phase difference is not exactly 180 degrees as seen in the figure.
That might be because of the internal capacitance of the transistor. (Capacitance between base
and collector, because input to output path goes through base and collector of transistor.)
The gain of the amplifier is about 40 (1V/0.025V). The type of the amplifier is
common-emitter since input is base and ouput is collector. Common-emitter amplifier has a
high gain that is why the gain in this circuit is very high. Also offset voltage of the ouput has
a value different than zero because there exists a DC voltage of collector and there is no
capacitor between collector and output
In the frequency response of output signal, there are two pole and one zero frequencies.
One pole cut-off frequency is caused by the coupling capacitor connected to the base of the
transistor. One pole and one zero cut-off frequencies are caused by emitter by-pass capacitor
connected to the emitter of the transistor. Low cut-off frequency is almost 4.3kHz and high
cut-off frequency is almost 160kHz. (I took a very close look to the gain in dB graph:3 dB
below frequencies. Close looks to the gain in dB graph are given on the upcoming page.)
4

98.95

98.50

98.00

97.50
4.302KHz 5.000KHz
20*log(V(Q1:c))
Frequency

101.50

101.00

100.50

100.14
22.765KHz 26.762KHz
20*log(V(Q1:c))
Frequency

98.95

98.50

98.00

97.50
161.18KHz 189.47KHz
20*log(V(Q1:c))
Frequency