DOC/LP/01/28.02.

02

LESSON PLAN LP-CS2202

LP Rev. No: 01
Date: 25.6.2010
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 01 of 06

Unit: I Branch: IT Semester: III

Unit syllabus:
BOOLEAN ALGEBRA AND LOGIC GATES 8
Review of binary number systems - Binary arithmetic – Binary codes – Boolean algebra
and theorems - Boolean functions – Simplifications of Boolean functions using Karnaugh
map and tabulation methods – Logic gates
Objective:
This unit discusses different methods used for the simplification of Boolean functions. It
also gives a detailed idea of number system and binary arithmetic.

Session Teaching
No
Topics to be covered
Time Ref Method
Introduction to Number System 1(pp1-7)
1 50m BB
2(7-10)
Conversion of number system from one radix to another in 1( 5-12)
2 50m BB
detail
Binary Arithmetic
1(13-27)
3 Binary addition, Binary Subtraction, Binary Multiplication, 50m BB
2(10-15)
BCD, ASCII, GRAY CODE and Error correcting codes
1(33-37)
4 Boolean algebra and theorems 50m BB
2(17-57)
1(40-59)
Boolean Functions and Representing Boolean Functions
5 50m 2(58-70) BB
Simplification of Boolean functions using theorems.
Internet
Simplifications of Boolean functions using Karnaugh map
6 50m 1(64-70) BB
Introduction to map method, two, three variable k-maps
Four and five variable maps, simplification of Boolean
7 50m 1(70-76) BB
functions using K-map
K-map using don’t care conditions
8 Simplification of Boolean functions using don’t care 50m 1(80-82) BB
conditions
Simplifications of Boolean functions using tabulation
9 50m 2(149-167) BB
method
Introduction to logic gates 1(51-59)
10 50m BB
2(101-113)
Problems in K- map map method
11 50m Tutorial sheet BB

12 Problems in Tabulation method 50m Tutorial sheet BB

 DOC/LP/01/28.02.02

LESSON PLAN LP-CS2202

LP Rev. No: 01
Date: 25.06.2010
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 02 of 06

Unit: II Branch: IT Semester: III

Unit syllabus:

COMBINATIONAL LOGIC 9
Combinational circuits – Analysis and design procedures - Circuits for arithmetic
operations - Code conversion – Introduction to Hardware Description Language (HDL)

Objective:
This unit provides the overview of combinational logic, by discussing various topics
related to combinational circuits and code conversion.

Session Teaching
No Topics to be covered
Time Ref Method
Introduction to Combinational Logic
Analysis and design procedures for combinational 1(111-115)
13 50m BB
circuits.

Design of Combinational circuit for a given Boolean

14 function. 50m 1(115-118) BB
Discussion with various examples
Design of Combinational circuits for arithmetic
15 operations 50m 1(119-123) BB
Half adder, full adder, binary adder
16 carry propagation, binary subtractor, overflow 50m 1(123-129) BB
Decimal adder, binary multiplier, magnitude
17 comparator 50m 1(129-133) BB

Code conversion
1(116-118)
18 Definiton, code conversions example, gray code to 50m BB
binary conversion.
Introduction to HDL 1(147-167)
19 50m BB
Module representation, Gate delays 4(79-88)
20 Boolean expressions, User defined primitives 50m 1(147-167) BB
21 Problems in code conversion 50m BB
22 Tutorial 50m Tutorial sheet BB
Continuous Assessment Test – I
75m
 DOC/LP/01/28.02.02

LESSON PLAN LP-CS2202

LP Rev. No: 01
Date: 25.6.2010
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 03 of 06

Unit: III Branch: IT Semester: III

Unit syllabus:
DESIGN WITH MSI DEVICES 8
Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable
logic - HDL for combinational circuits.

Objective:
This unit focuses on advanced concepts of system design like decoders, encoders,
multiplexers, demultiplexers and programmable logic.

Session Teaching
Topics to be covered
No Time Ref Method
Introduction to MSI
23 Designing of decoders and encoders 50m 1(134-139) BB

Design of 8x1 decoders and encoders using 4x1 1(134-139)

24 50m BB
encoders 2(227-229)

Introduction to multiplexers.
1(141-147)
25 Designing of multiplexers for various Boolean 50m BB
2(223-226)
functions

Introduction to demultiplexers.
Designing of demultiplexers for various Boolean 1(141-147)
26 50m BB
functions 2(223-226)

Design of 8x1 multiplexer and demultiplexers

27 50m 1(141-147) BB
using 4x1 mux
Memory
28 RAM, types of memories, memory decoding, Error 50m 1(255-276) BB
detection and correction, ROM., Types of ROM.
Programmable logic
29 Programmable array logic(PAL), Programmable 50m 1(276-283) BB
Logic array(PLA).
HDL for combinational circuits. 1(190-198)
30 Gate level modeling, data flow modeling, 50m 4(89-105) BB
behavioral modeling
31 Problems in Multiplexer and Demultiplexer 50m Tutorial sheet BB
32 Problems in ROM,PLA,PLA 50m Tutorial sheet BB
 DOC/LP/01/28.02.02

LESSON PLAN LP-CS2202

LP Rev. No: 01
Date: 25.06.2010
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 04 of 06

Unit: IV Branch: IT Semester: III

Unit syllabus:

SYNCHRONOUS SEQUENTIAL LOGIC 10

Sequential circuits – Flip flops – Analysis and design procedures - State reduction and
state assignment - Shift registers – Counters - HDL for sequential logic circuits, Shift
registers and counters.

Objective:
To Learn about sequential circuits, counters, shift registers, and state diagrams

Session Teaching
Topics to be covered
No Time Ref Method
Sequential circuits
1(167-172)
33 Introduction and definitions, Introduction to flip flops, 50m BB
3(314-317)
Discussion of SR
1(167-172)
34 Discussion of D,T, JK flip flops 50m BB
3(317-328)
Analysis and design procedures
clocked sequential circuits, state equation, state table, 1(180-190)
35 50m BB
state diagram, flip flop input equations. 2(323-345)

36 State reduction and state assignment 50m 1(198-202) BB

Design of Shift registers using flip flops
37 50m 1(217-227) OHP
Serial transfer, serial addition, universal shift register
Counters 1(227-243)
38 50m BB
Design of Ripple counters. 3(337-340)
1(227-243)
39 Design of synchronous counters 50m BB
3(341-352)
40 Design of Ring and Johnson counters 50m 1(227-243) BB
1(244-255)
41 HDL for registers and counters 50m BB
4(97-105)
42 Problems in Synchronous Sequential Circuits 50m Tutorial sheet BB
43 Conversion of one flip and another flops and Tutorial 50m Tutorial sheet BB
Continuous Assignment Test II 75m

LESSON PLAN LP-CS2202

 DOC/LP/01/28.02.02

LP Rev. No: 01
Date: 25.06.2010
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 05 of 06

Unit: V Branch: IT Semester: III

Unit syllabus:
ASYNCHRONOUS SEQUENTIAL LOGIC 10
Analysis and design of asynchronous sequential circuits - Reduction of state and flow
tables – Race-free state assignment – Hazards-ASM Chart.

Objective:
This unit deals with analysis and design procedures of asynchronous logic circuits and
hazards.
Session Teaching
Topics to be covered
No Time Ref Method
Asynchronous Sequential circuits 1(342-344)
44 50m BB
Introduction and discussion of Sequential circuits 2(590-594)

Analysis procedure of asynchronous sequential

45 50m 1(344-352) BB
circuits-Transition table, Flow table
Design procedure of asynchronous sequential
1(360-367)
46 circuits-Primitive flow table, reduction of Primitive 50m BB
2(608-619)
flow table
Reduction of state and flow tables
47 50m 1(367-373) BB
Implication table
48 Merging of flow table, Compatible pairs. 50m 1(374-379) BB
Race-free state assignment-Three-row flow- 1(374-379)
49 50m BB
table,four-row flow-table and multiple row method. 3(520)
1(379-384)
50 Hazards-Hazards in combinational logic circuits 50m BB
2(657-673)
51 Sequential circuits, Essential hazards. 50m 1(379-384) BB
Design example for asynchronous sequential
52 50m 1(299-309) BB
circuit-ASM Chart
Problems in Asynchronous Sequential circuits
53 50m Tutorial sheet BB

54 Problems in Hazards 50m Tutorial sheet BB

Continuous Assessment Test – III 75m
 DOC/LP/01/28.02.02

LESSON PLAN LP-CS2202

LP Rev. No: 01
Date: 25.6.2010
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN Page 06 of 06

Branch: IT Semester: III

Course Delivery Plan:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Week
I
I II I II I II I II I II I II I II I II I II I II I II I II I II I II
II
Units     1       2   3       4   5

CAT-I CAT-II CAT-III

Books Referred:

TEXT BOOKS:

1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2002.

REFERENCES

2. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico

Publishing House, 2000.
3. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2003.
4. Bhaskar, Jayaram, “A VHDL Primer, 2nd Edition

Prepared by Approved by

Signature
Name D.Priya Dr.G.Sumathi
Designation Lecturer HOD-IT
Date 25.6.2010 25.6.2010