EE214 Advanced Analog Integrated Circuit Design: - Winter 2011 - Boris Murmann Stanford University Murmann@stanford - Edu

EE214
Advanced Analog Integrated Circuit Design
- Winter 2011 -
Boris Murmann
Stanford University
murmann@stanford.edu
Table of Contents
Chapter 1 Introduction
Chapter 2 BJT Devices
Chapter 3 MOS Devices and Gm/ID-based Design
Chapter 4 Review of Elementary Circuit Configurations
Chapter 5 Two-Port Feedback Circuit Analysis
Chapter 6 Frequency Response of Feedback Circuits
Chapter 7 Wideband Amplifiers
Chapter 8 Noise Analysis
Chapter 9 Distortion Analysis
Chapter 10 Opamps and Output Stages
Chapter 1
Introduction
B. Murmann
Stanford University
Analog Circuit Sequence
Fundamentals for upper- Analysis and design

Design of mixed-
level undergraduates and techniques for high-
signal/RF building
entry-level
y graduate
g performance
p circuits in
bl k
blocks
students advanced Technologies
EE314 —
RF Integrated
Circuit Design
EE114 — EE214 — EE315A — VLSI

Fundamentals of Advanced Analog Signal
Analog Integrated Integrated Circuit Conditioning
Circuit Design Design Circuits
EE315B — VLSI
Data Conversion
Circuits
B. Murmann EE214 Winter 2010-11 – Chapter 1 2

The Evolution of a Circuit Designer…
EE101A,B EE114 EE214 EE314

EE315A,B
Analog Design
EE 114
Bandwidth
Power Dissipation
EE 214
Electronic Noise Distortion

Significance of Electronic Noise (1)
Signal-to-Noise
g Ratio
2
Psignal Vsignal
SNR = ∝ 2
Pnoise Vnoise
Example: Noisy image
http://www.soe.ucsc.edu/~htakeda/kernelreg/kernelreg.htm
p g g

Th
The "fidelity"
"fid lit " off electronic
l t i systems
t is
i often
ft determined
d t i d by
b their
th i SNR
– Examples
• Audio systems
• Imagers,
Imagers cameras
• Wireless and wireline transceivers
Electronic noise directly trades with power dissipation and speed
– In
I mostt circuits,
i it lowl noise
i di
dictates
t t llarge capacitors
it ((and/or
d/ smallll R
R,
large gm), which means high power dissipation
Noise has become increasingly important in modern technologies with
reduced supply voltages
– SNR ~ Vsignal2/Vnoise2 ~ (αVDD)2/Vnoise2
Designing a low-power, high-SNR circuit requires good understanding of
electronic
l t i noise i
Distortion
vo
vi
Small-signal approximation
All electronic circuits exhibit some level of nonlinear behavior

– The resulting waveform distortion is not captured in linearized small-
small
signal models
The distortion analysis tools covered in EE214 will allow us to quantify
the impact of nonlinearities on sinusoidal waveforms

Significance of Distortion
For a single tone input, the nonlinear terms in a circuit’s transfer function
primarily result in signal harmonics
For a two-tone input, the nonlinear terms in a circuit’s transfer function

result
lt in
i so-called
ll d “i
“intermodulation
t d l ti products”
d t ”
Example: Two interferer tones create an

intermodulation product that corrupts the
signal in a desired (radio-) channel
Noise and Distortion Analysis in EE214
Main objective
– Acquire the basic tools and intuition needed to analyze noise and
distortion in electronic circuits
– Look at a few specific circuit examples to “get a feel” for situations
where noise and/or distortion may matter
Leave application-specific examples for later

– EE314: Noise and distortion in LNAs,, mixers and power
p amplifiers
p
– EE315A: Noise and distortion in filters and sensor interfaces
– EE315B: Noise and distortion in samplers, A/D & D/A converters

Technology
MOSFET Bipolar Junction Transistor (BJT)
EE114
EE214
Bipolar vs. CMOS (1)
Advantages of bipolar transistors

– Lower parametric variance
– Higher
Hi h supply
l voltages
l
– Higher intrinsic gain (gmro)
– Higher fT for a given feature size/lithography
Disadvantages of bipolar transistors

– Lower integration density, larger features
– Higher cost

Bipolar vs. CMOS (2)
A.J. Joseph, et al., "Status and

Direction of Communication
Technologies - SiGe BiCMOS and
RFCMOS," Proceedings of the
IEEE, vol.93, no.9, pp.1539-1558,
September 2005.
• CMOS tends to require finer lithography to achieve same speed as

BiCMOS p
process with advanced BJT
Example that Leverages High-Speed BJTs:

40Gb/s Integrated Optical Transponder

Die Photo of 40Gb/s CDR Circuit *
• 120-GHz fT / 100GHz fmax

0.18μm SiGe BiCMOS
• 144 pins
• 3.5mm x 4.2mm
• +1.8V and –5.2V supplies
• 7.5W power dissipation
*A
A. O
Ong, ett al.,
l ISSCC 2003
Radar Sensor
R
Ragonese ett al.,
l ISSCC 2009

Example that Leverages Densely Integrated CMOS:
RF Transceiver System-on-a-Chip (SoC)
In modern CMOS
technology, millions of
l i gates
logic t can b be
integrated on a chip
– Together with
moderate- to high
moderate
performance analog
blocks
Mehta et al., "A 1.9GHz Single-Chip

CMOS PHS Cellphone," ISSCC 2006.
45nm CMOS (Intel)
Steve Cowden
THE OREGONIAN
July 2007

Research in Device Technology
Vdd
Molecular devices
A B
Transport-enhanced FET
Out
Strained Si, Ge, SiGe, III-V
A
B
buried oxide
Gnd
isolation
Nanodevice Spintronics
Silicon Substrate
Self-assembled array
device fabrication
top-gate
channel
Nanotube
channel
3D, heterogeneous back-gate Quantum
i t
integration
ti
isolation
cascade
buried oxide
Multi-Gate / FinFET Nanowire

Gate
Source Drain [Prof. P. Wong] Ferromagnetic

Embedded
domain wall
memory
Time
Thoughts on Device Technology
In the future, innovative circuit designers must embrace “whichever”

technology is most suitable (in terms of performance, cost, reliability, etc.
f their
for th i specific
ifi problem
bl
– Regardless of the respective I-V law and associated nonidealities
In EE214, we will use bipolar and MOS technology to illustrate the

similarities and differences between two advanced technologies
The device parameters and simulation models of the “EE214
EE214
technology” correspond to a modern 0.18-μm SiGe BiCMOS technology
– See e.g. S. Wada, et al., “A manufacturable 0.18-um SiGe BiCMOS
technology for 40-Gb/s optical communication LSIs,” in Proc. 2002
Bipolar/BiCMOS Circuits and Technology Meeting, pp. 84–87.

Analysis of Feedback Circuits
F
Feedback
db k circuits
i it can b be studied
t di d iin severall ways
– Return ratio analysis (EE114)
– Two-port analysis (EE214)
Both methods have their own merits and demerits, and a good circuit
designer should understand both approaches
Two-port analysis nicely captures a number of practical scenarios in
which the forward amplifier (“a”) and feedback network (“f”) can be
intuitively identified and separated (while maintaining loading effects)
– Shunt-shunt, shunt-series, series-shunt, series-series configurations
Example:
Shunt series feedback circuit
Shunt-series
Root Locus Techniques
Provides intuitive guidance on “where the poles move” when the loop
gain is varied
Valuable for stability analysis and frequency compensation

Course Outline
BJT & short channel MOS device models

Review of elementaryy amplifier
p stages
g ((BJT focus))
Two-port feedback circuit analysis
Root locus
Wideband amplifiers
Noise analysis
Distortion analysis
OpAmps and output stages
Summary of Learning Goals
Understand device behavior and models for transistors available in

advanced integrated circuit technologies
– SiGe BJT, short channel MOS
Acquire the basic intuition and models for
– Distortion analysis
– Noise analysis
– Two-port feedback circuit analysis
– Root locus techniques and their application to broadband amplifiers
Solidify the above topics in a hands-on project involving the design and
optimization of a broadband amplifier circuit

Staff and Website
Instructors
– Boris Murmann, Drew Hall
Teaching assistants
– Kamal Aggarwal, Pedram Lajevardi
Administrative support
– Ann Guerra, CIS 207
Lectures are televised
– But please come to class to keep the discussion interactive!
Web page: http://ccnet.stanford.edu/ee214
– Check regularly, especially bulletin board
– Register for online access to grades and solutions
Text and Prerequisites
EE214 C
Course reader
d
– Hardcopies available at Stanford Bookstore (~1/3)
Required textbook
– Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog
Integrated Circuits, 5th ed., Wiley
Reference text
– B. Razavi, Design of Integrated Circuits for Optical Communications,
McGraw-Hill, 2002
Course p
prerequisite:
q EE114 or equivalent
q
– Basic device physics and models
– Frequency response, dominant pole approximation, ZVTC
– Biasing,
g, small-signal
g models
– Common source, common gate, and common drain stages
– Port impedance calculations
– Feedback basics

Assignments
Homework (20%)
– Handed out on Wed, due following Wed in class
– Lowest
L t HW score will
ill b
be d
dropped
d
– Policy for off-campus students
• Fax or email to SCPD before deadline stated on handout
Midterm
Midt E
Exam (30%)
Design Project (20%)
– Design of an amplifier using HSpice (no layout)
– Work
W k ini tteams off two
t
– OK to discuss your work with other teams, but no file exchange!
Final Exam (30%)
Honor Code
Please remember you are bound by the honor code

– We will trust you not to cheat
– We will try not to tempt you
But if you are found cheating it is very serious
– There is a formal hearing g
– You can be thrown out of Stanford
Save yourself a huge hassle and be honest
For more info
– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/honorcode.pdf

Chapter 2
Bipolar
p Junction Transistors
B. Murmann
Stanford University
Reading Material: Sections 1.1, 1.2, 1.3, 1.4, 2.5, 2.6, 2.7, 2.11, 2.12
History
W. Brinkman, D. Haggan, and W. Troutman, “A history of the invention

Bardeen, Brattain, and Shockley, 1947 of the transistor and where it will lead us,” IEEE J. Solid-State Circuits,
vol. 32, no. 12, pp. 1858-1865, Dec. 1997.
W. Shockley,
W Shockley M.M Sparks,
Sparks and G G. KK. Teal
Teal, “P
P-N
N junction
transistors,” Phys. Rev. 83, pp. 151–162, Jul. 1951.

Conceptual View of an NPN Bipolar Transistor (Active Mode)
VBE
Device acts as a voltage
IC ∝ e kT / q controlled current source
– VBE controls IC
The base-emitter junction is
forward biased and the base-
base
collector junction is reverse
IB << IC n- C
biased
p B VCE The device is built such that
– The base region is very thin
VBE n+ E
– The emitter doping is much
higher than the base doping
– The collector doping is much
lower than the base doping
Outline of Discussion
In order to understand the operation principle of a BJT, we will look at

– The properties of a forward biased pn+ junction
– The properties of a reverse biased pn- junction
– And the idea of combining the two junctions such that they are joined
by a very thin (p-type) base region
The treatment in the following slides is meant to be short and qualitative

– See any solid-state physics text for a more rigorous treatment
(involving band diagrams, etc.)

pn+ Junction in Equilibrium (No Bias Applied)
nn0 ≅ ND (Donor concentrat ion)

pp0 ≅ NA (Acceptor concentrat ion)
ni2 n2
np 0 = ≅ i
p p 0 NA
ni2 n2
pn0 = ≅ i
nn0 ND
nn Concentration of electrons on n side (majority carriers)

pn Concentration of holes on n side (minority carriers)
np Concentration of electrons on p side ((minority
y carriers))
pp Concentration of holes on p side (majority carriers)
The subscript “0” in the carrier concentrations

denotes equilibrium (no bias applied)
Built-in Potential
The built in potential sets up an electric field that opposes the diffusion of
mobile holes and electrons across the junction
dp
(Drift ) qμppE = qDp (Diffusion)
dx
⎛p ⎞ ⎛n ⎞ ⎛N N ⎞ kT
⇒ ψ 0 = VT ln⎜⎜ p0 ⎟⎟ = VT ln⎜ n0 ⎟ ≅ VT ln⎜⎜ A 2 D ⎟⎟ VT =
⎜ ⎟
⎝ pn0 ⎠ ⎝ np0 ⎠ ⎝ ni ⎠ q

pn+ Junction with Forward Bias (1)
Depletion region narrows, diffusion processes are no longer balanced by

electrostatic force
At the edge of the depletion region (x=0), the concentration of minority
carriers [np(0)] can be computed as follows
⎛ n ⎞ ⎛ N ⎞ ND
VBE
VT
VBE
VT n2 BE
V
ψ 0 − VBE = VT ln ⎜ n ⎟ ≅ VT ln ⎜ D ⎟ ∴np (0) = ⋅e = np0 e ≅ i e VT

⎜ n (0) ⎟ ⎜ n (0) ⎟ ψ0
NA
⎝ p ⎠ ⎝ p ⎠ e VT
pn+ Junction with Forward Bias (2)
Th
The result
lt on the
th previous
i slide
lid shows
h th
thatt fforward
d bi
biasing
i iincreases
the concentration of electrons at the “right” edge of the depletion region
by a factor of exp(VBE/VT)
The
Th same h
holds
ld ffor h
holes
l att th
the “l
“left”
ft” edge
d off th
the d
depletion
l ti region
i
VBE VBE
ni2
pn (0) = pn0 ⋅ e VT ≅ ⋅ e VT
ND
Since ND >> NA, it follows that pn(0) << np(0), i.e. the concentration of
minority carriers is much larger at the lightly doped edge
Since there must be charge neutrality in the

regions outside the depletion region, the
concentration of the majority carriers at the
edge of the depletion region must also increase
− However, this increase is negligible when
np(0) << pp ≅ NA (or pn(0) << nn ≅ ND)
− These conditions are called “low-level
injection”

What Happens with the Injected Minority Carriers?
Th
The carriers
i would
ld “like”
“lik ” tto diff
diffuse ffurther
th iinto
t th
the neutral
t l regions,
i b
butt
quickly fall victim to recombination
The number of minority carriers decays exponentially, and drops to 1/e
off the
th att the
th so-called
ll d diff
diffusion
i llength
th (Lp or Ln, on the
th order
d off microns)
i )
In each region, there are now two types of currents

− Diffusion of injected
j minority
y carriers due to non-zero dnp/dx ((or dp
pn/dx))
− Majority carrier currents for recombination
n+ Total Current p
Jp
Jn
Hole current (recombination)
Jn
Jp Electron diffusion current ( dnp/dx)
Summary – Forward Biased pn+ junction
Lots of electrons being injected into the p-region, not all that many holes
get injected into the n+ region
– The heavier n-side doping, the more pronounced this imbalance
becomes
The electrons injected in the p region cause a diffusion current that
d
decays iin th
the x-direction
di ti d due tto recombination
bi ti
The recombination necessitates a flow of holes to maintain charge
neutrality; as the diffusion current decays, the hole current increases,
yielding
i ldi a constantt t currentt d
density
it along
l th
the d
device
i
Near the edge of the depletion region, the electron diffusion current
dominates over the hole current that supplies carriers for recombination
– This is a very important aspect that we will come back to

Reverse Biased pn- Junction
Reverse bias increases the

width of the depletion
region
g and increases the
electric field
Depletion region extends
mostly into n- side
Any electron that would
E
“somehow” make it into the
depletion region will be
e-
swept through, into the n-
region
Text, p.2
– Due to electric field
Bipolar Junction Transistor – Main Idea
n+ Total Current p
Jp
Jn
Hole current (recombination)
Jn
Jp Electron diffusion current ( dnp/dx)
“cut here”
Make the p-region of the pn+ junction very thin

Attach an n- region
g that will “collect” and sweep
p across most of the
electrons before there is a significant amount of recombination

Complete Picture
n+ p n-
Text, p. 9
Straight line because base is thin; negligible recombination

((“short
short base”
base electron profile)
BJT Currents
http://en.wikipedia.org/wiki/Bipolar
p p g p _jjunction_transistor
Primary current is due to electrons captured by the collector

T
Two (undesired)
( d i d) b base currentt components t
– Hole injection into emitter (Æ 0 for infinite emitter doping)
– Recombination in the base (Æ 0 for base width approaching zero)

First-Order Collector Current Expression
dnp (x) np (0)

Jn = qDn ≅ −qDn Current density
dx WB
np (0) A is the cross-sectional area
IC ≅ qADn
WB WB is the base width
V
n2 BE
np (0) i e VT Result from slide 7
NA
V
qADnni2 VBET
∴ IC ≅ e
WBNA
VBE q nni2
qAD
∴ IC ≅ IS e VT IS =
WBNA
Base Current
IB = IB1+ IB2 where IB1 = Recombination in the base

IB2 = Injection into the emitter
IB1 follows
f ll ffrom dividing
di idi ththe minority
i it carrier
i charge
h iin th
the b
base (Qe) b
by it
its
“lifetime” (τB)
1 VBE
Qe 2 np (0)WBqA 1 WBqAni2 VT
IB1= = = e
τb τb 2 τbNA
IB2 depends on the gradient of minority carriers (holes) in the emitter. For a
long emitter (all minority carriers recombine)
“long”
⎡ ⎛ 2 VBE − x ⎞⎤ VBE
dpn (x) d n qADp ni2 V
= −qADp ⎢ ⎜ i e VT e p ⎟⎥
L
IB2= −qADp = e T
dx x =0 ⎢ dx ⎜ N ⎟⎟ ⎥ Lp ND
⎢⎣ ⎝⎜ D ⎠ ⎥⎦ x =0
In modern narrow-base transistors IB2 >> IB1.

Terminal Currents and Definition of αF, βF
Text, p. 9
IE = − (IC + IB )
IC
βF (ideally infinite)
IB
IC β
αF = F (ideally one)
( −IE ) 1 + βF
Th
The subscript
b i t “F” iindicates
di t th thatt th
the d
device
i iis assumed
d tto operate
t iin th
the
forward active region (BE junction forward biased, BC reverse biased, as
assumed so far)
– More on other operating regions later
later…
Basic Transistor Model
Text, p. 13
Simplified model; very useful for bias point calculations

(assuming e.g. VBE(on) = 0.8V)

Basewidth Modulation (1)
Side note:
BJT inherently has better (higher)
Text, p. 14 ro than MOS since lower doping
on n-side (collector) has most of
the depletion region inside the
collector
∂ ⎛ qADnni2 ⎞
VBE
∂IC I dWB
= ⎜ e VT ⎟=− C (See eq. (1.18) for dWB/dVCE term)
∂VCE ∂VCE ⎜⎝ WB (VCE ) ⋅ NA ⎟
⎠ W B dVCE
Early Voltage (VA)
Text, p. 15
IC WB
VA =− = const. (independent of IC )
∂IC dWB
∂VCE dVCE
VBE
VT ⎛ VCE ⎞
IC ≅ ISe ⎜1+ ⎟
⎝ VA ⎠

Small-Signal Model
BE V
dIC d I
gm = = ISe VT = C
dVBE dVBE VT
⎛I ⎞
d⎜ C ⎟
1 dIB β 1 IC g
gπ = = = ⎝ F⎠= = m (assuming βF = const.)
rπ dVBE dVBE βF VT βF
⎡ VBE ⎤
1 dIC d ⎢ VT ⎛ VCE ⎞ ⎥ IC
go = = = ISe ⎜1+ ⎟ ≅
r0 dVCE dVCE ⎢ ⎝ VA ⎠ ⎥ VA
⎣ ⎦
Intrinsic Gain
IC VA VA
gmro ≅ ⋅ = VT ≅ 26mV (at room temperature)
VT IC VT
In the EE214 technology,

technology the SiGe npn device has VA = 90V,
90V thus
90V
gmro ≅ = 3460
26mV
Much larger than the intrinsic gain of typical MOSFET devices

Outline – Model Extensions and Technology
Complete picture of BJT operating regions

Dependence
p of βF on operating
p g conditions
Device capacitances and resistances
Technology
– Junction
J ti isolated
i l t d
– Oxide isolated with polysilicon emitter
– Heterojunction bipolar (SiGe base)
– BiCMOS
– Complementary bipolar
BJT Operating Regions
Discussed so far
BE = forward biased
CE = reverse biased
Text, p. 17

Carrier Concentrations in Saturation
Text, p. 16
Base-Collector junction is forward biased

np(WB), and therefore also IC, strongly depend on VBC, VCE
VCE(sat) is the voltage at which the devices enters saturation
– The difference between the two junction voltages, small ~0.05…0.3V
0.05…0.3V
Gummel Plot
A Gummel
G l plot
l t iis a semi-log
i l plot
l t off IC and
d IB versus VBE (linear
(li scale)
l )
It reveals the regions for which high βF is maintained (region II below)
What happens
pp in regions
g I and III?
Text, p. 24

βF Fall-Off
Region III (high current density)

– Injected electron charge in base region nears the level of doping
(“high level injection”)
– For this case, it can be shown that the injected carrier concentration
rises with a smaller exponent (cut in half) and therefore
1 VBE
2 VT
IC = ISe
Region I (low current density)

– There exists excess base current due to (unwanted) recombination in
the depletion layer of the base-emitter junction
– This current becomes significant at low current densities and sets a
minimum for IB
Current Profile of a Forward Biased Diode Revisited
Extra current due to

recombination (small) Total current
Recombination

βF vs. IC and Temperature
Text, p. 24
≅ 7000 ppm / °C
Junction Isolated npn Transistor
Text, p. 97

Device Capacitances and Resistances
Big mess!
First focus on intrinsic elements
Charge Storage
IIn the
th intrinsic
i t i i transistor,
t i t charge
h is
i stored
t d in i the
th jjunction
ti capacitances,
it
Cje and Cjc = Cμ, and as minority carriers in the base and emitter
Both minority carrier charge injected into the base and into the emitter,
are proportional
ti l to
t exp(V(VBE/VT)
– But the charge in the base is much larger, as discussed previously
Base terminal must supply charge for neutrality

Voltage dependent charge Æ capacitance (Cb)
ΔVBE causes change in injected charge
Text, p. 26

Base Charging Capacitance
∂Qe ∂Qe ∂IC

Cb = = τFgm
∂VBE ∂IC ∂VBE
∂Qe ∂ ⎛1 ⎞ qADnnp (0)

τF = = np (0)WBqA ⎟ IC =
∂IC ∂IC ⎜⎝ 2 ⎠ WB
∂ ⎛ 1 WB2 ⎞ 1 WB2
τF = ⎜ IC ⎟ =
∂IC ⎜⎝ 2 Dn ⎟⎠ 2 Dn
τF is called the base transit time (in forward direction)

Typical values for high-speed transistors are on the order of 1…100ps
Junction Capacitance
C j0 2C j0
Cj = n
⎛ VD ⎞
⎜1− ⎟
⎝ ψ0 ⎠
Text, p. 6

Small-Signal Model with Intrinsic Capacitances
Cμ
B C
v1 rπ Cπ gmv1 ro
–
E
Cπ = Cb + C je = Cb + 2C je0
C jc0
Cμ = C jc = n
⎛ VCB ⎞
⎜1+ ⎟
⎝ ψ 0c ⎠
Model with Additional Parasitics
Neglect
Text, p. 32
Range of numbers
re ~1-3Ω
rb ~ 50-500Ω
50 500Ω Values at high end of these ranges may have large
rc ~ 20-500Ω impact on performance Æ Try to minimize through
advanced processing & technology
CCS ~ 3-200fF

BJT in Advanced Technology
Text, p. 107
Oxide isolated
Self-aligned structure (base and emitter align automatically)
Very thin base (~100nm or less) through ion implantation
Reduced breakdown voltages compared to more traditional structures
SiGe Heterojunction Bipolar Technology
A heterojunction is a pn junction formed with different materials for the n

and p regions
Germanium is added to the base of a silicon bipolar transistor to create a
heterojunction bipolar transistor (HBT)
– Base formed by growing a thin epitaxial layer of SiGe
– Results in a lower bandgap (and higher intrinsic carrier
concentration) in the base than emitter
In “band diagram speak” the bandgap mismatch increases the barrier to
the injection of holes (in an npn transistor) from the base into the emitter
One way to enumerate the benefits of a SiGe base is to look at the
current gain expression

HBT Current Gain
Intrinsic carrier concentration in the SiGe base (niB) is larger than

intrinsic carrier concentration in the Si emitter (niE)
qADnnp0 qADnnp0 2
qADnniB
DnNDLp 2
WB WB WBNA niB
βF = 2
≅ 2
= 2
= 2
⋅
1 np0 WBqA qADpniE qADpniE qADpniE DpNA WB niE
+
2 τb LpND LpND LpND
Added degree of
freedom for HBT
Base doping (NA) can be increased while maintaining same βF

− Can reduce base width without affecting rb
− Larger ro due to decrease in base width modulation
Device Parameter Comparison

SiGe npn HBT
Transistor with 0.7μm2 = 0.22μm x 3.2μm
Emitter Area
300
2
90
3x smaller device
3.2x10-17A
1pA 5x bigger IS
2.0V
5 5V
5.5V
3.3V
0.56ps 18x smaller τF
10ps
25Ω 16x smaller rb
60
60Ω
2.5Ω
6.26fF
0.8V
0.4
3.42fF
0.6V
0.33 Oxide isolation vs.
3.0fF
Junction isolation
0 6V
0.6V
0.33

BiCMOS Technology
CMOS
Text, p. 154
Older BJTs used poly Si as “diffusion source” for

emitter doping.
doping Advanced (state-of-the-art) BJTs
use epitaxial growth of both the SiGe base and
Si emitter regions
Advanced Complementary Bipolar Technology
[Texas Instruments]

Cross Section
[Texas Instruments]
Figures of Merit for BJTs
Product of current gain and Early voltage, β·VA

Product of transit frequency
q y and breakdown voltage,
g , fT·BVCEO
Maximum frequency of oscillation, fmax
– More in EE314
T
Transit
it (or
( transition)
t iti ) frequency,
f fT
– Formally defined as the frequency for which the current gain of the
device falls to unity
– Important to keep in mind that the basic device model may fall apart
altogether at this frequency
• Lumped device models tend to be OK up to ~fT/5
– Therefore,
Therefore fT should be viewed as an extrapolated parameter
parameter, or
simply as a proxy for device transconductance per capacitance

Transit Frequency Calculation (1)
Ignore for simplicity

Text, p. 35
rπ
v1 = i io = gmv1
(AC circuit; DC biasing not shown) (
1 + rπs Cπ + Cμ )i
io gmrπ 1
= ≅ gmrπ = βF for ω << = ωβ
(
ii 1 + rπ jω Cπ + Cμ ) (
rπ Cπ + Cμ )
io gm
≅ for ω >> ωβ
ii (
jω Cπ + Cμ )
Transit Frequency Calculation (2)
|io/ii| gm
(asymptote)
(
ω Cπ + Cμ )
≅ βF
Note that rπ “matters” only for
frequencies up to ωβ = ωT/βF
Text, p. 36
gm gm
1= ⇒ ωT =
(
ωT Cπ + Cμ ) Cπ + Cμ
1 C C je Cμ C je Cμ
τT = = b+ + = τF + +
ωT gm gm gm gm gm

fT versus IC plot
“peak fT”
Cje and Cμ High level

dominate injection, τF
increases
Text, p. 37
gm = IC/VT increases
The particular current value at which fT is maximized depends on the

particular parameters of a technology and the emitter area of the BJT
EE214 Technology
Assumed to be similar to a 0
0.18 μm BiCMOS technology featuring a
18-μm
high-performance SiGe npn device
– VCC = 2.5V (BJT), VDD=1.8V (MOS)
See e
e.g.
g
– Wada et al., BCTM 2002
– Joseph et al., BCTM 2001
– IBM 7HP documentation
• https://www-01.ibm.com/chips/techlib/techlib.nsf/products/BiCMOS_7HP)
NPN PMOS/NMOS Poly resistor
http://fuji.stanford.edu/events/spring01/slides/harameSlides.pdf

Cross Section of npn Device
EE214 npn Unit Device
A technology typically comes with an optimized

layout for a unit device of a certain size
Great care is then taken to extract a Spice model
AE = 0.22μm x 3.2μm
for this particular layout using measured data
Spice model (usr/class/ee214/hspice/ee214_hspice.sp)
E
.model npn214 npn
+ level=1 tref=25 is=.032f bf=300 br=2 vaf=90
B + cje=6.26f vje=.8 mje=.4 cjc=3.42f vjc=.6 mjc=.33
+ re=2
re=2.5
5 rb=25 rc=60 tf=563f tr=10p
C + xtf=200 itf=80m ikf=12m ikr=10.5m nkf=0.9
Instantiation in a circuit netlist

* C B E
q1 n1 n2 n3 npn214

BJT Model Parameters
For more info consult the HSpice documentation under
/afs/ir.stanford.edu/class/ee/synopsys/B-2008.09-SP1/hspice/docs_help
PDF files:
home.pdf hspice_cmdref.pdf hspice_integ.pdf hspice_relnote.pdf hspice_sa.pdf
hspice_devmod.pdf hspice_mosmod.pdf hspice_rf.pdf hspice_si.pdf
Adding Multiple Devices in Parallel
For the unit device, there exists a practical

upper bound for the collector current
– Due
D tto ththe onsett off high
hi h llevell iinjection
j ti
This means that the unit device can only
E E E
deliver a certain maximum gm
If more gm is needed, “m” unit devices can
B B B
be connected in parallel
C C C Instantiation in a circuit netlist ((m=3))
* C B E
q1 n1 n2 n3 npn214 3

npn Unit Device Characterization
* ee214 npn device characterization
* C B E
q1 c b 0 npn214
Vc c 0 1.25
ib 0 b 1u
.op
.dc ib dec 10 10f 100u
.probe ib(q1) ic(q1) ie(q1) CC
.probe gm = par('gm(q1)')
.probe
b go = par('g0(q1)')
(' 0( 1)')
.probe cpi = par('cap_be(q1)')
.probe cmu = par('cap_ibc(q1)')
.probe beta = par('beta(q1)')
.options dccap post brief

.inc '/usr/class/ee214/hspice/ee214_hspice.sp'
.end
DC Operating Point Output
**** bipolar junction transistors

element 0:q1
model 0:npn214
ib 999.9996n
ic 288.5105u
vbe 803.4402m
vce 1.2500
vbc -446.5598m
vs -1.2327
power 361.4415u
betad 288.5106
gm 10.2746m
rpi 26 8737k
26.8737k
rx 25.0000
ro 313.4350k
cpi 14.6086f
cmu 2 8621f
2.8621f
cbx 0.
ccs 0.
betaac 276.1163
ft g
93.5999g

Gummel Plot
Transit Frequency
150
Hz]
100
fT [GH
50
0 -4 -3 -2
10 10 10
IC [A]

Intrinsic Gain
ee215 npn
4000
3500
3000
gm /go [GHz]] 2500
2000
1500
1000
500
0 -8 -6 -4 -2
10 10 10 10
IC [A]
gm/IC
Important to realize that gm will not be exactly equal to IC/VT at high currents

I-V Curves
NPN (1x, AE=0.7μm2, I B=0.2, 0.4, ..., 1μA NMOS 2/0.18, VGS=0.6, 0.8, ..., 1.4V
300 800
700
250
600
200
500
I C [μA]
I D [μA]
150 400
300
100
200
50
100
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5
VCE [V] VDS [V]
Passive Components (1)
Joseph et al., BCTM 2001

Passive Components (2)
Diffusion Resistor MIM Capacitor
Text, p. 116

Chapter 3
MOS Transistor Modeling
Gm/ID-based
based Design
B. Murmann
Stanford University
Reading Material: Sections 1.5, 1.6, 1.7, 1.8
Basic MOSFET Operation (NMOS)
Text,, p.41
p
How to calculate drain current (ID) current as a function of VGS, VDS?

Simplifying Assumptions
1)) Current is controlled byy the mobile charge

g in the channel. This is a very
y
good approximation.
2) "Gradual Channel Assumption" - The vertical field sets channel charge,
so we can approximate the available mobile charge through the voltage
diff
difference b
between
t th
the gate
t and
d th
the channel
h l
3) The last and worst assumption (we will fix it later) is that the carrier
velocity is proportional to lateral field (ν = μE). This is equivalent to Ohm's
law: velocity (current) is proportional to E-field
E field (voltage)
Derivation of First Order IV Characteristics (1)
Qn (y) = Cox [ VGS − V(y) − Vt ]
ID = Qn ⋅ v ⋅ W
v = μ ⋅E
ID = Cox [ VGS − V(y) − Vt ] ⋅ μ ⋅ E ⋅ W
W⎡ VDS ⎤
ID = μCox ⎢( VGS − Vt ) − ⎥ ⋅ VDS
L ⎣ 2 ⎦

Pinch-Off
– VGS +
+ VDS –
N N
Qn(y), V(y)
y Voltage at the end of

channel is fixed at VGS-V
Vt
y=0 y=L
Effective voltage across channel is VGS-Vt

– At the point where channel charge goes to zero, there is a high
lateral field that sweeps the carriers to the drain
• Recall that electrons are minority carriers in the p-region of a pn
j
junction;
ti th
they are b
being
i sweptt ttoward d th
the n-region
i
– The extra drain voltage drops across depletion region
To first order, the current becomes independent of VDS
Plot of Output Characteristic

Saturation
Triode Region
Region
ID
VGS-V
Vt
VDS
W⎡ VDS ⎤
Triode Region: ID = μCox ⎢( VGS − Vt ) − ⎥ ⋅ VDS
L ⎣ 2 ⎦
W⎡ (V − V )
Saturation Region: ID = μCox ⎢ ( VGS − Vt ) − GS t ⎤⎥ ⋅ (VGS − Vt )
L ⎣ 2 ⎦
1 W
= μCox (VGS − Vt )2
2 L

Plot of Transfer Characteristic (in Saturation)
ID
Vt
VGS
VOV
dID W W
gm = = μCox ( VGS − Vt ) = μCox VOV
dVGS L L
W 2I
= 2IDμCox = D
L VOV
Output Characteristic with “Channel Length Modulation”
Saturation
Triode Region
Region
go= dID/dVDS ≠ 0
ID
VGS-Vt
VDS
dID d ⎡1 W 2 ⎤
go = = ⎢ 2 μCox L (VGS − Vt ) (1 + λVds )⎥
dVDS dVDS ⎣ ⎦
1 W λID
= μCox (VGS − Vt )2 ⋅ λ = ≅ λID
2 L 1 + λVDS

Capacitances
Text, p. 54
Gate Capacitance Summary
Subthreshold Triode Saturation
Cgs Col ½ WLCox+ Col 2/

3 WLCox + Col
Cgd Col ½ WLCox+Col Col

−1
⎛ 1 1 ⎞
Cgb ⎜⎜ + ⎟⎟ 0 0
⎝ C js WLCox ⎠

Capacitance Equations and Parameters
EE 214 Technology
Parameter (0.18μm)
NMOS PMOS
ε
Cox = ox
t ox Cox 8.42 fF/μm2 8.42 fF/μm2
Col = WCol' C’ol

C 0 491 fF/μm
0.491 0 657 fF/μm
0.657
CJ 0.965 fF/μm2 1.19 fF/μm2

AD ⋅ CJ PD ⋅ CJSW
Cdb = MJ
+ MJSW CJSW 0 233 fF/μm
0.233 0 192 fF/μm
0.192
⎛ VDB ⎞ ⎛ VDB ⎞
⎜ 1 + PB ⎟ ⎜ 1 + PB ⎟ PB 0.8 V 0.8 V
⎝ ⎠ ⎝ ⎠
MJ 0.38 0.40
AD = WL diff
MJSW 0.13 0.33
PD = W + 2L diff
LDIF 0.64 μm 0.64 μm
Complete Small-Signal Model
gd
gs gs m gs o
gb sb db
2
bsub (Cj0 = 0.2 fF/μm , “dwell” model)
Cgg Cgs + Cgb + Cgd Cdd Cdb + Cgd

What are μCox (“KP”) and λ (“LAMBDA”) for our Technology?
.MODEL
MODEL nmos214 nmos
+acm = 3 hdif = 0.32e-6 LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3618397
+K1 = 0.5916053 K2 = 3.225139E-3 K3 = 1E-3
+K3B = 2.3938862 W0 = 1E-7 NLX = 1.776268E-7
+DVT0W
+DVT0
= 0
= 1.3127368
DVT1W
DVT1
= 0
= 0.3876801
DVT2W
DVT2
= 0
= 0.0238708
The HSpice
p model for an NMOS
+U0
+UC
= 256.74093
= 5.182125E-11
UA
VSAT
= -1.585658E-9
= 1.003268E5
UB
A0
= 2.528203E-18
= 1.981392
device in our technology is shown
+AGS
+KETA
= 0.4347252
= -9.888408E-3
B0
A1
= 4.989266E-7
= 6.164533E-4
B1
A2
= 5E-6
= 0.9388917
to the left
+RDSW = 128.705483 PRWG = 0.5 PRWB = -0.2
+WR
+XL
= 1
= 0
WINT
XW
= 0
= -1E-8
LINT
DWG
= 1.617316E-8
= -5.383413E-9
BSIM 3v3 model
+DWB = 9.111767E-9 VOFF = -0.0854824 NFACTOR = 2.2420572
+CIT
+CDSCB
= 0
= 0
CDSC
ETA0
= 2.4E-4
= 2.981159E-3
CDSCD
ETAB
= 0
= 9.289544E-6
110 parameters
+DSUB = 0.0159753 PCLM = 0.7245546 PDIBLC1 = 0.1568183
+PDIBLC2 = 2.543351E-3
+PSCBE1 = 8E10
PDIBLCB = -0.1
PSCBE2 = 1.876443E-9
DROUT
PVAG
= 0.7445011
= 7.200284E-3
KP and LAMBDA nowhere to be
+DELTA
+PRT
= 0.01
= 0
RSH
UTE
= 6.6
= -1.5
MOBMOD
KT1
= 1
= -0.11
found
found…
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 1
+CGDO = 4.91E-10 CGSO = 4.91E-10 CGBO = 1E-12
+CJ = 9.652028E-4 PB = 0.8 MJ = 0.3836899
+CJSW = 2.326465E-10 PBSW = 0.8 MJSW = 0.1253131
+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.1253131
+CF = 0 PVTH0 = -7.714081E-4 PRDSW = -2.5827257
+PK2 = 9.619963E-4 WKETA = -1.060423E-4 LKETA = -5.373522E-3
+PU0 = 4.5760891
4 5760891 PUA = 1.469028E
1 469028E-14
14 PUB = 1.783193E
1 783193E-23
23
+PVSAT = 1.19774E3 PETA0 = 9.968409E-5 PKETA = -2.51194E-3
+nlev = 3 kf = 0.5e-25
An Attempt to Extract μCox
Bias MOSFET at constant VDS>VOV, sweep VGS and plot μCox estimate
300
NMOS 5/0.18
250 NMOS 20/0.72
200
μnCox [μA/V ]
2
2ID
μCox =
W 2 150
V
L OV 100
50
0
0 0.1 0.2 0.3 0.4 0.5
V [V]
OV
The extracted μCox depends on L and VOV and cannot be viewed as a

constant parameter

Questions
Which physical effects explain the large deviation from the basic square
law model?
How can we design with such a device?
– Is there another “simple” equation that describes its behavior?
We will approach the above two questions by performing a systematic,

simulation-based device characterization
– And discuss the relevant p
physical
y p
phenomena that explain
p the
observed behavior
As a basis for this characterization, we consider three basic figures of
merit that relate directlyy to circuit design
g
Figures of Merit for Device Characterization
Square Law
Transconductance efficiency
gm 2
– Want
W t large
l gm, for
f as little
littl currentt =
as possible ID VOV
Transit frequency gm 3 μVOV

≅
– Want largeg gm, without large
g Cgg Cgg 2 L2
Intrinsic gain gm 2
– Want large gm, but no go ≅
go λVOV

Device Characterization
* NMOS characterization
.param gs=0.7
.param dd=1.8
vds d 0 dc 'dd/2'
vgs g 0 dc 'gs'
mn d g 0 0 nmos214 L=0.18um W=5um
.op
.dc gs 0.2V 1V 10mV DD
.probe ov = par('gs-vth(mn)')
.probe
b gm_id
id = par('gmo(mn)/i(mn)')
(' ( )/i( )')
.probe ft = par('1/6.28*gmo(mn)/cggbo(mn)')
.probe gm_gds = par('gmo(mn)/gdso(mn)')
.options
options post brief dccap
.inc /usr/class/ee214/hspice/ee214_hspice.sp
.end
gm/ID Plot
40
35 0.18um NMOS
2/VOV
30
BJT (q/kT)
25
A]
gm/I D [S/A
20
15
10
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

Observations
Square law prediction is fairly close for VOV > 150mV

Unfortunatelyy gm/ID does not approach
pp y for VOV → 0
infinity
It also seems that we cannot do better than a BJT, even though the
square law equation would predict this for 0 < VOV < 2kT/q ≅ 52mV
For further analysis,
analysis it helps to identify three distinct operating regions
– Strong inversion: VOV > 150mV
• Deviations due to short channel effects
– Subthreshold: VOV < 0
• Behavior similar to a BJT, gm/ID nearly constant
– Moderate Inversion: 0 < VOV < 150mV
• Transition region,
region an interesting mi mix of the abo
abovee
Subthreshold Operation
A plot of the device current in our previous simulation

0
1 10
-1
0.8 10
-2
0.6 10
A]
A]
I D [mA
I D [mA
-3
0.4 10
-4
0.2 10
-5
0 10
-0.5 0 0.5 1 -0.5 0 0.5 1
V [V] V [V]
VOV [V] VOV [V]
Questions
– What determines the current when VOV< 0, i.e. VGS< Vt?
– What
Wh t iis th
the d
definition
fi iti off Vt?

Definition of Vt
Vt is defined as the VGS at which the number of electrons at the surface

equals the number of doping atoms
Seems somewhat arbitrary, but makes sense in terms of surface charge
control
Mobile Charge versus VOV
6.E-07
Fixed Charge
5.E-07 Mobile Charge
T t l Charge
Total Ch
4.E-07
harge [C]
3.E-07
Ch
2.E-07
1.E-07
0.E+00
-1.0 -0.5 0.0 0.5 1.0
VOV [V]
Around VGS=Vt (VOV=0), the relationship between mobile charge in the

channel and gate voltage becomes linear (Qn ~ CoxVOV)
– Exactly what we assumed to derive the long channel model

Mobile Charge on a Log Scale
O
On a log
l scale,
l we see th
thatt there
th are mobile
bil charges
h b f
before we reach
h
the threshold voltage
– Fundamental result of solid-state physics, not short channels
1.E-06
1.E-07
1 E-08
1.E 08
Mobile Charge [C]
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
1.E-14
1.E-15
1.E-16
-1.00 -0.50 0.00 0.50 1.00
VOV [V]
BJT Similarity
We have
– An NPN sandwich,
sandwich mobile minority carriers in the P region
This is a BJT!
– Except that the base potential is here controlled through a capacitive
divider,, and not directlyy byy an electrode

Subthreshold Current
• We know that for a BJT

VBE
kT
IC = IS ⋅ e VT VT =
q
• For the MOSFET in subthreshold we have
VGS − Vt
nV
VT
ID = I0 ⋅ e
• n is given by the capacitive divider
C js + Cox C js
n= = 1+
Cox Cox
where Cjs is the depletion layer capacitance
• In the EE214 technology n ≅ 1.5
Comparison – NMOS versus NPN
Vt

Subthreshold Transconductance
dID 1I gm 1
gm = = D =
dVGS n VT ID nVT
Similar to BJT, but unfortunately n (≅1.5) times lower
40
35 0.18um NMOS
~1.5x 2/VOV
30
BJT (q/kT)
25
A]
gm/I D [S/A
20
15
10
0
-0.2
02 -0.1
01 0 0.1
0 1 02
0.2 03
0.3 04
0.4 05
0.5
VOV [V]
Moderate Inversion
IIn the
th transition
t iti region
i between
b t subthreshold
bth h ld and
d strong
t inversion,
i i we
have two different current mechanisms
Drift (MOS) ν = μE
dn kT dn
Diffusion ((BJT)) ν = D = μ
dx q dx
Both current components are always present

– Neither one clearly dominates in moderate inversion
Can show that ratio of drift/diffusion current ~(VGS-Vt)/(kT/q)
– MOS equation becomes dominant at several kT/q

Re-cap
Subthreshold
Operation
Transition to
Strong Inversion
What causes the discrepancy between 2/VOV and 0.18μm NMOS in

strong inversion?
Short Channel Effects
Velocity saturation due to high lateral field

Mobility
y degradation
g due to high
g vertical field
Vt dependence on channel length and width
Vt = f(VDS)
ro = f(VDS)
…
We will limit the discussion in EE214 to the first two aspects of the above
list, with a focus on qualitative understanding

Velocity Saturation (1)
IIn the
th derivation
d i ti off theth square llaw model,
d l it iis assumed
d th
thatt th
the carrier
i
velocity is proportional to the lateral E-field, v=μE
Unfortunately, the speed of carriers in silicon is limited (vscl ≅ 105 m/s)
– At very high fields (high voltage drop across the conductive channel),
the carrier velocity saturates
Text, p. 60
μE
ν d (E) ≅ ≅ μEc = v scl for E >> Ec
E
(approximation) 1+
Ec
v scl
= for E = Ec
2
Velocity Saturation (2)
It is
i important
i t t to
t distinguish
di ti i h various
i regions
i iin th
the above
b plot
l t
– Low field, the long channel equations still hold
– Moderate field, the long channel equations become somewhat
inaccurate
– Very high field across the conducting channel – the velocity saturates
completely and becomes essentially constant (vscl)
T
To gett some feel
f l for
f latter
l tt two
t cases, let's
l t' first
fi t estimate
ti t the
th E field
fi ld using
i
simple long channel physics
In saturation, the lateral field across the channel is
VOV 200mV V
E = e.g. = 1.11⋅ 106
L 0.18μm m

Field Estimates
In our 0.18μm technology, we have for an NMOS device

m
105
v s = 6.7 ⋅ 106 V
Ec = scl ≅
μ cm2 m
150
Vs
Therefore
V
1.11⋅ 106
E m
= ≅ 0.16
Ec V
6.7 ⋅ 106
m
This means that for VOV on the order of 0.2V, the carrier velocity is
somewhat reduced,, but the impairment
p is relatively
y small
The situation changes when much larger VOV are applied, e.g. as the
case in digital circuits
Short Channel ID Equation
A simple equation that captures the moderate deviation from the long
channel drain current can be written as (see text, p. 62)
1 W 2 1
ID ≅ μCox VOV ⋅
2 L ⎛ VOV ⎞
⎜1+ ⎟
⎝ Ec L ⎠
1 W E L ⋅ VOV
≅ μCox VOV ⋅ c
2 L (EcL + VOV )
Think of this as a “parallel combination"
V
Minimum-length
Minimum length NMOS: Ec L = 6 7 ⋅ 106
6.7 ⋅0 18μm = 1
0.18 1.2V
2V
m
V
Minimum-length PMOS: EcL = 16.75 ⋅ 106 ⋅ 0.18μm = 3V
m

Modified gm/ID Expression
Assuming VOV << EcL, we can show that (see text, pp. 63-64)
gm 2 1
≅ ⋅
ID VOV ⎛ VOV ⎞
⎜1+ ⎟
⎝ Ec L ⎠
E.g.
E forf an NMOS device
d i with
ith VOV=200mV
200 V
gm 2 1 2
≅ ⋅ = ⋅ 0.86
ID VOV ⎛ 0.2 ⎞ VOV
⎜ 1 + ⎟
⎝ 1.2 ⎠
Means that the square

q g inversion ((at VOV ≅ 200mV))
law model in strong
should be off by about 15%
This prediction agrees well with the simulation data
Mobility Degradation due to Vertical Field
In MOS technology, the oxide thickness has been continuously scaled

down with feature size
– ~6.5nm in 0.35μm, ~4nm in 0.18μm, ~1.8nm in 90nm CMOS
As a result, the vertical electric field in the device increases and tries to
pull the carriers closer to the "dirty" silicon surface
– Imperfections impede movement and thus mobility
This effect can be included by replacing the mobility term with an
"effective mobility"
μ 1
μ eff ≅ θ = 0.1...0.4
(1 + θVOV ) V
Yet another "fudge factor"

– Possible to lump with EcL parameter, if desired

Transit Frequency Plot
1 gm
fT =
2π Cgg
Observations - fT
Again the square-law model doesn't do a very good job

– Large fT discrepancy in subthreshold operation and in strong
inversion (large VOV)
The reasons for these discrepancies are exactly the same as the ones
we came across when looking at gm/ID
– Bipolar action in subthreshold operation and moderate inversion
– Short channel effects at large VOV
• Less gm, hence lower gm/Cgg
Same conclusion: we won't be able to make good predictions with a
simple square law relationship

gm/ID· fT Plot
gm 1 3μ
Square Law: ⋅ fT ≅
ID 2π L2
Sweet spot (?)
Short channel
Square law predicts effects
too much gm/ID
Intrinsic Gain Plot
Impossible to approximate with the “λ” model equation!

Gradual Onset of 1/gds
VDS = VOV
Gradual Onset of 1/gds (Zoom)
VDS = VOV VDS = 2/(gm/ID)

“VDSsat” Estimate Based on gm/ID
“VDSsat” defined
(arbitrarily) as VDS at
which 1/g gds is equal
q
to ½ of the value at
VDS = VDD/2 = 0.9V
≅4kT/q
V* = 2/(gm/ID) is a reasonable estimate of “V

VDSsat”
Observations – Intrinsic Gain
Device shows a rather gradual transition from triode to saturation

– Square law predicts an abrupt change from small to large intrinsic
gain at VDS = VOV
– V* = 2/(gm/ID) provides a reasonable estimate for the minimum VDS
that is needed to extract gain from a device
• Typically
T i ll wantt tto stay
t att lleastt 100
100mV
V above
b thi
this value
l ini practical
ti l
designs
The physics that govern the behavior of ro=1/gds are complex
– Channel length modulation
– Drain induced barrier lowering (DIBL)
– Substrate current induced body effect (SCBE)
• Not present in all technologies and/or PMOS devices
If you are interested in more details, please refer to EE316 or similar

The Challenge
Square-law model is inadequate for design in fine-line CMOS

– But simulation models (BSIM, PSP, …) are too complex for hand-
calculations
This issue tends to drive many designers toward a “spice monkey”
design methodology
– No hand calculations, iterate in spice until the circuit “somehow”
meetst the
th specifications
ifi ti
– Typically results in sub-optimal designs
Our goal
– Maintain a systematic design
methodology in absence of a set of
compact MOSFET equations
Strategy
– Design using look-up tables or charts
[[Courtesyy Isaac Martinez]]
The Problem

The Solution
Use pre-computed spice data in hand calculations
Technology Characterization for Design
Pl
Plott the
th following
f ll i parameters
t ffor a reasonable
bl range off gm/ID and
d
channel lengths
– Transit frequency (fT)
– Intrinsic gain (gm/gds)
– Current density (ID/W)
In addition, may want to tabulate relative estimates of extrinsic
capacitances
it
– Cgd/Cgg and Cdd/Cgg
Parameters are (to first order) independent of device width
– Enables "normalized design" and re-use of charts
– Somewhat similar to filter design procedure using normalized
coefficient tables
Do hand calculations using the generated technology data
– Can use Matlab functions to do table-look-up on pre-computed data

NMOS Simulation Data
PMOS Simulation Data

Transit Frequency Chart
L=0.18um
L=0.5um
Intrinsic Gain Chart
L=0.5um
L 0 18
L=0.18um

Current Density Chart
L=0.18um
L 05
L=0.5um
Lookup Functions in Matlab
% Set up path and load simulation data (for VDS=0.9V)

addpath('/usr/class/ee214/matlab');
load techchar.mat;
% Lookup fT for NMOS, L=0.18um, at gm/ID=10S/A

lookup_ft(tech, 'n', 0.18e-6, 10)
ans = 2.2777e+10
% Lookup gm/ID for NMOS, L=0.18um, at fT=20GHz

lookup_gmid(tech, 'n', 0.18e-6, 20e9)
ans = 11.5367
% Lookup ID/W for NMOS, L=0.18um, at gm/ID=10S/A

lookup_idw(tech, 'n', 0.18e-6, 10)
ans = 29.3281

VDS Dependence
VDS dependence
is relatively weak
Typically
yp y OK to
work with data
generated for
VDD/2
Extrinsic Capacitances (1)
NMOS, L=0.18um
1
Cdd/Cgg
Cgd/Cgg
0.8 Again, usually OK
to work with
0.60
estimates taken at
06
0.6
VDD/2
0.4
0 24
0.24
0.2
0
0 0.5 1 1.5
VDS [V]

NMOS, gm/I D=10S/A, VDS=0.9V

0.8
Cgd/Cgg
07
0.7
Cdd/Cgg
0.6
0.5
0.4
0.3
0.2
0.1
0
0.2 0.25 0.3 0.35 0.4 0.45 0.5
L [μm]
PMOS, gm/I D=10S/A, VDS=0.9V

0.8
Cggd/Cgg
07
0.7
Cdd/Cgg
0.6
05
0.5
0.4
0.3
0.2
0.1
0
0.2 0.25 0.3 0.35 0.4 0.45 0.5
L [μm]

Generic Design Flow
1) Determine gm (from design objectives)

2) Pick L
Short channel Æ high fT (high speed)
Long channel Æ high intrinsic gain
3) Pick gm/ID (or fT)
Large gm/ID Æ low power, large signal swing (low VDSsat)
Small gm/ID Æ high fT (high speed)
4) Determine ID (from gm and gm/ID)
5) Determine W (from ID/W, current density chart)
Many other possibilities exist (depending on circuit specifics, design

constraints and objectives)
Basic Design Example
Given specifications and objectives

– 0.18μm
0 18μm technology
– DC gain = -4
– RL=1k, CL=50fF, Ri=10k
– Maximize bandwidth while
keeping IB ≤ 300uA
• Implies L=Lmin=0.18um
– Determine device width
– Estimate dominant and non-
dominant pole

Small-Signal Model
Calculate gm and gm/ID
4 gm 4mS S
A v (0) ≅ gmRL = 4 ⇒ gm = = 4mS = = 13.3
1kΩ ID 300μA A
Why can we Neglect ro?
A v (0) = gm (RL || ro )
−1
⎛ 1 1⎞
= gm ⎜ + ⎟
⎝ RL ro ⎠
1 1 1
= +
A v (0) gmRL gmro
1 1 1
= +
4 gmRL gmro
Even at L=Lmin= 0.18μm, we have gmro > 30

ro will be negligible in this design problem

Zero and Pole Expressions
gm
High frequency zero ωz ≅ >> ωT
(negligible) Cgd
1
Dominant pole ωp1 ≅
(see Chapter 4) Ri ⎡⎣Cgs + Cgbb + (1 + gmRL ) ⋅ Cgdd ⎤⎦
1 1
Nondominant pole ωpp2 ≅
(see Chapter 4) ⎣ (
ωp1 Ri RL ⎡Cgs + Cgb ⎤ CL + ⎡Cgs + Cgd ⎤ Cdb + CLCgd
⎦ ⎣ ⎦ )
Calculation of capacitances from tabulated parameters:
Cgs + Cgb = Cgg − Cgd Cdb = Cdd − Cgd
Determine Cgg via fT Look-up
L=0 18um
L=0.18um
16.9 GHz

Find Capacitances and Plug in
1 gm 1 4mS
Cgg = = = 37.7fF
37 7fF
2π fT 2π 16.9GHz
Cgd
Cgd = Cgg = 0.24 ⋅ 37.7fF = 9.0fF
Cgg
Cdd
Cdd = Cgg = 0.60 ⋅ 39.4fF = 23.6fF
Cgg
∴ fp11 ≅ 196 MHz ∴ fp2 ≅ 6.0 GHz
Device Sizing
16.2 A/m L=0.18um

Circuit For Spice Verification
ID 300μA
Device width W= = = 18.5μm
ID 16.2A / m
W
Simulation circuit
B o
1F
Simulated DC Operating Point
element 0:mn1 Calculation

region Saturati
id 326.8330u 300 uA
vgs 624.9116m
vds 873.1670m
vdsat 113.7463m
vod 138.5878m
138 5878m
gm 4.1668m 4 mS Good agreement!
gds 108.2225u
...
cdtot 21.8712f 23.6 fF
cgtot 37.6938f 37.7 fF
cgd 8.9163f 9.0 fF
...
gm/ID 12.8 13.3 S/A

HSpice .OP Capacitance Output Variables
HSpice (.OP) Corresponding Small Signal

Model Elements
cdtot 21.8712f cdtot ≡ Cgd + Cdb

cgtot 37.6938f cgtot ≡ Cgs + Cgd + Cgb
cstot 44.2809f
cstot ≡ Cgs + Csb
cbtot 34.9251f
cgs 26.7303f bt t ≡ Cgb + Csb+ Cdb
cbtot
cgd 8.9163f cgs ≡ Cgs
cgd ≡ Cgd
Simulated AC Response
213 MHz
11.5 dB (3.8)
5.0 GHz
Calculated values: |Av(0)|=12 dB (4.0), fp1=196 MHz, fp2=6.0 GHz

Using .pz Analysis
Netlist statement
.pz v(vo) vi
Output
***************************************************
****** pole/zero analysis
input = 0:vi output = v(vo)
poles (rad/sec) poles ( hertz)

real imag real imag
-1.34190g 0. -213.569x 0.
-31.4253g 0. -5.00149g 0.
zeros (rad/sec)
( d/ ) zeros ( h
hertz)
t )
real imag real imag
458.247g 0. 72.9323g 0.
Observations
The design and pole calculations essentially right on target!

– Typical discrepancies are on the order of 10-20%, mostly due to VDS
dependencies, finite output resistance, etc.
We accomplished this by using pre-computed spice data in the design
process
Even if discrepancies are more significant, there’s always the possibility
to track down the root causes
– Hand calculations are based on parameters that also exist in Spice,
e.g. gm/ID, fT, etc.
– Different from square law calculations using μCox, VOV, etc.
• Based on artificial parameters that do not exist or have no
significance
i ifi iin th
the spice
i model
d l

References
F. Silveira et al. "A gm/ID based methodology for the design of CMOS
analog circuits and its application to the synthesis of a silicon-on-
insulator micropower OTA,
OTA," IEEE J. Solid State Circuits, Sep. 1996, pp.
Solid-State
1314-1319.
D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS transistor via
the inversion coefficient and the continuum of gms/Id," Proc. Int. Conf. on
El t i
Electronics, Circuits
Ci it and dS Systems
t , pp. 1179-1182,
1179 1182 SSep. 2002
2002.
B. E. Boser, "Analog Circuit Design with Submicron Transistors," IEEE
SSCS Meeting, Santa Clara Valley, May 19, 2005,
http://www ewh ieee org/r6/scv/ssc/May1905 htm
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
P. Jespers, The gm/ID Methodology, a sizing tool for low-voltage analog
CMOS Circuits, Springer, 2010.
T. Konishi, K. Inazu, J.G. Lee, M. Natsu, S. Masui, and B. Murmann,
“Optimization of High-Speed and Low-Power Operational
Transconductance Amplifier Using gm/ID Lookup Table Methodology,”
IEICE Trans. Electronics, Vol. E94-C,
E94 C, No.3, Mar. 2011.

Chapter 4
Review of Elementary Circuit
Configurations
B. Murmann
Stanford University
y
Reading Material: Sections 3.3.1, 3.3.3, 3.3.6, 3.3.8, 3.5, 7.2.3, 7.2.4.1, 7.3.2,
7.3.4, 4.2.2, 4.2.3, 4.2.4
Basic Single-Stage Amplifier Configurations
MOS
Common Common Common

Source Gate Drain
Bipolar
Common Common Common

Emitter Base Collector
Transconductance Current Voltage

Stage Buffer Buffer

Widely Used Two-Transistor Circuits
MOS
Cascode Current Differential

Stage Mirror Pair
Bipolar
p
Analysis Techniques (1)
N
Nodal
d l analysis
l i (KCL
(KCL, KVL)
– Write KCL for each node, solve for desired transfer function or port
impedance
– Most general method
method, but conveys limited qualitative insight and
often yields high-entropy expressions
Miller theorem
http://paginas.fe.up.pt/~fff/eBook/MDA/Teo_Miller.html
Miller approximation
pp
− Approximate the gain across Z as frequency independent, i.e. K(s) ≅ K
for the frequency range of interest
− This approximation
pp requires
q a check ((or g
good intuition))

Dominant
D i t pole
l approximation
i ti
1 1 1
= ≅
⎛ s ⎞⎛ s⎞ s s s2
s s2
⎜1 − ⎟⎜ 1 − ⎟ 1 − p − p + p p 1− +
p1 p1p2
⎝ p1 ⎠⎝ p2 ⎠ 1 2 1 2
1 1 b
Given 2
⇒ p1 ≅ − , p2 ≅ − 1
1 + b1s + b2s b1 b2
Zero value time constant analysis

− The coefficient b1 can be found by summing all zero value time
constants in the circuit
b1 = ∑ τi
Generalized time constant analysis

− Can also find higher order terms (e.g. b2) using a sum of time
constant products
− A. Hajimiri, “Generalized Time- and Transfer-Constant Circuit
Analysis,” IEEE Trans. Circuits Syst. I, pp. 1105-1121, June 2010.
Return ratio analysis

– See text pp. 599-612
Blackman’s impedance formula
Two
Two-port
port feedback analysis
– More later in this course

Chapter Overview
BJT-centric review of elementary circuit configurations

– Highlight differences to MOS circuits
Single-stage amplifiers
– Common emitter stage
– Common emitter stage g with source degeneration
g
– Common collector stage
– Common base stage
– Common gate stage (discussion of bulk connection)
BJT current mirrors
BJT differential pair
Common-Emitter Stage
VCC
Vo IB
RL VCC
RS +
Q1 VO+vo
vi ~ –
VI
Vi Vi
DC input bias voltage (VI) biases Q1 in the forward active region

Typically, want VO ≅ VCC/2
Main differences to consider versus common-source stage (MOS)
– Bias point sensitivity
– Finite input resistance (due to rπ)
– Base resistance (rb) often significant

Bias Point Sensitivity
IB IC = βFIB
RS + + R
VI VBE Vo L VCC
– –
Is e qVBE kT
VI − VBE(on) RL
IB ≅ VO = VCC − ICRL = VCC − βFIBRL = VCC − βF
RS
( VI − VBE(on) )
RS
The dependence on βF makes “direct voltage biasing” impractical

How to generate VI so as to control Vo?
Practical configurations are usually based on feedback, replica biasing,
ac coupling or differential circuits
Small-Signal Equivalent Circuit for CE Stage
RS rb 1 Cμ 2
+ +
vi ~ v1 rπ Cπ gmv1 ro RL CL vo
– –
For hand analysis, we will usually neglect rc and re

If significant, rb can be included with RS, i.e. RS* = RS + rb
Resulting
R lti llow-frequency
f gain
i
vo ⎛ r ⎞
A V (0) = − ⎜ * π ⎟⋅ gmRLtot Lt t = ro || RL
RLtot
vi ω=0 ⎝ RS + rπ ⎠
=1 for MOS

Gate Tunnel Conductance for MOSFETS
MOSFET
MOSFETs with ith extremely
t l thin
thi gate
t oxide
id draw
d a gate
t currentt due
d tot
direct tunneling
This leads to a finite current gain and input resistance
– Similar to BJT!
A Annema
A. Annema, et al
al., “Analog
Analog circuits in ultra-deep-submicron
ultra deep submicron CMOS
CMOS,” IEEE J.
J Solid
Solid-State Circuits pp.
State Circuits, pp 132-143
132 143, Jan.
Jan 2005
2005.
Frequency Response
Using nodal analysis, we find
⎛ s⎞
⎜ 1− ⎟
v o (s) ⎛ r ⎞ z1 ⎠
= − ⎜ * π ⎟⋅ gmRLtot ⎝
v i (s) ⎝ RS + rπ ⎠ 1 + b1s + b2s2
b1 = RS* (Cπ + Cμ ) + RLtot (CL + Cμ ) + gmRS* RLtotCμ
b2 = RS* RLtot (CπCL + CπCμ + CLCμ )

gm
z1 = +
Cμ
z1 is a feedforward zero in the RHP. If Cπ >> Cμ, then
gm gm
z1 = + >> = ωT
Cμ Cπ + Cμ

Dominant Pole Approximation
If a dominant
d i t pole
l condition
diti exists,
i t we can write
it
1 1
p1 ≅ − =− *
b1 RS (Cπ + Cμ ) + RLtot (CL + Cμ ) + gmRS* RLtotCμ
1
=−
RS* ⎡⎣Cπ + (1 + gmRLtot ) Cμ ⎦⎤ + RLtot (CL + Cμ )
b1 RS* (Cπ + Cμ ) + RLtot (CL + Cμ ) + gmRS* RLtotCμ

p2 ≅ − =−
b2 RS* RLtot ((CπCL + CπCμ + CLCμ )
If Cμ << Cπ, CL, then
RS* Cπ + RLtotCL + gmRS* RLtotCμ ⎛ 1 1 g C ⎞

p2 ≅ − = −⎜ * + + m⋅ μ⎟
RS* RLtotCπCL ⎝ RSCπ RLCL CL Cπ ⎠
Emitter Degeneration
VCC
RL
RS VO+vo
gm
Ro Gm ≅
1 + gmRE
vi ~
Ri Ro ≅ ro (1 + gmRE )
RE
VI
Degeneration resistor reduces the transconductance and increases the

p resistance of the device
output
– Same as in the MOSFET version of this circuit
For the BJT version, RE helps increase the input resistance

Calculation of Ri
For the complete nodal analysis, see text p. 196

A more intuitive way to find Ri is via the Miller theorem
ve RE g R
K= ≅ = m E
1
vb + RE 1 + gmRE
gm
rπ rπ
Ri = ≅ = rπ (1 + gmRE )
1− K ⎛ gmRE ⎞
⎜1− ⎟
⎝ 1 + gmRE ⎠
The same “bootstrapping” effect applies to Cπ, we see Cπ/(1+gmRE)

looking into the input
− Assuming K = constant in the frequency range of interest
Alternative Calculation of Ri
it it RE( +1)
+ +
+ v1 + v1
- ( +1)it -
vt vt
- RE -
Ri ≅ rπ + RE (1 + β ) = rπ + RE (1 + gmrπ ) ≅ rπ (1 + gmRE )
Tricks of this kind are useful for reasoning

g about low frequency
q y behavior
More detailed analyses must be used be taken when investigating
frequency dependence

Small-Signal Equivalent Circuit for Degenerated CE Stage
R S* Cμ
+ +
vi ~ v1 rπ Cπ gmv1 ro RL vo
– –
+
vE RE
R*S = RS + rb –
Deriving the transfer function of this circuit requires solving a 3x3 system
of equations
In order to obtain an estimate of the circuit’s bandwidth, it is more
convenient (and intuitive) to perform a zero-value time constant analysis
Useful Expressions
R C + RE
Ro ≅ ro (for β → ∞ )
(f
1 + gmRE
C
RB + RE
B R π ≅ rπ
o
1 + gmRE
Rμ = Rleft + Rright + GmRleftRright

E
Rleft ≅ RB rπ (1 + gmRE )
Rright ≅ RC
gm
Gm =
1 + gmRE

Bandwidth Estimate for Degenerated CE Stage (1)
R S* Cμ
+ +
vi ~ v1 rπ Cπ gmv1 ro RL vo
– –
+
vE (neglect)
RE
R*S = RS + rb –
Rμ = RS* rπ (1 + gmRE ) + RC + Gm ⎡⎣RS* rπ (1 + gmRE ) ⎤⎦ RC
≅ RS* + RC + GmRCRS* = RS* (1 + A v (0) ) + RC
RS* + RE RS* + RE
R π ≅ rπ ≅
1 + gmRE 1 + gmRE
Bandwidth Estimate for Degenerated CE Stage (2)
RE
1+ 1
RS* ω−3dB ≅
τ = ⎣⎡RS* (1 + A v (0) ) + RC ⎦⎤ Cμ + RS* Cπ τ
1 + gmRE
Compare to the case of RE = 0
1
τ ≅ ⎡⎣RS* (1 + A v (0) ) + RC ⎤⎦ Cμ + RS* Cπ ω−3dB ≅
τ
Adding RE can help improve the bandwidth, provided that gm > 1/RS*
− Note,, however,, that gm ((and hence the p
power dissipation
p must be
increased) to maintain the same Av(0)
Consider another special case where gmRE>>1 and the time constant
due to Cμ is negligible
⎛ R* ⎞ C ⎛ C + Cμ ⎞ ⎛ RE ⎞
τ ≅ ⎜1+ S ⎟ π ω−3dB ≅ ωT ⎜ π ⎟⎜ * ⎟
⎝ RE ⎠ gm ⎝ C π ⎠ ⎝ RE + R S ⎠

Common-Collector Stage (Emitter Follower)
VCC
RS
Q1
vi ~
VO+vo
VI IB RL CL
Behavior is very similar to MOS common drain stage, except that

– We do not need to worry about backgate effect
– There is finite input resistance due to rπ
– The output resistance depends on RS (in addition to 1/gm)
Input and Output Resistance
Input
I t resistance
i t (by
(b inspection)
i ti )
Ri ≅ rπ (1 + gmRL )
Output
O resistance
i ((using
i push-through
h h h trick)
i k)
RS* = RS + rb
1 R* 1 ⎛ RS* ⎞
Ro ≅ + S ≅ ⎜1+ ⎟
gm β + 1 gm ⎝ rπ ⎠

Low Frequency Voltage Gain
RS* vb
vi
vo
Ri ≅ rπ (1 + gmRL ) RL
vo vb vo rπ (1 + gmRL ) gmRL
A v0 = = ≅
vi v i v b rπ (1 + gmRL ) + Rs* 1 + gmRL
gmRL
≅ for rπ (1 + gmRL ) >> Rs*
1 + gmRL
≅1 for gmRL >> 1 and rπ (1 + gmRL ) >> R s*
Frequency Response
vo vb vo Zi v
= ⋅ = ⋅ o
vi v i v b Zi + R S v b
Zi
Detailed analysis gives a very complex result for the general frequency
response expression
i
Must typically apply approximations based on given component values

Frequency Response
Assuming that RS is large (often the case, and the reason why the stage
is used), we expect that the dominant pole is introduced at node vb
For the frequency
q y range
g up
p until the dominant p
pole,, we can therefore
approximate
vo gmRL 1 1
≅ =K Zi ≅ =
v b 1 + gmRL s ( Cπ [1 − K ] + Cμ ) sCi
1
ωp ≅
(Rs Rin ) Ci
See text, pp. 503 for a more detailed analysis, which also captures the
feedforward zero introduced by Cπ
Common Collector Output Impedance
Detailed analysis of the common-collector output impedance shows

potentially inductive behavior for large RS
The inductive behavior can lead to undesired “ringing”
ringing (or oscillations)
during circuit transients
In other cases, the inductive behavior is utilized for bandwidth extension
((“inductive
inductive peaking”)
peaking )
The capacitance Cμ tends to reduce the inductive frequency range
– Cμ appears in parallel with RS, and creates a low impedance
termination for high frequencies
– Makes it difficult to use the circuit as a “good inductor”
For a discussion on common collector output impedance and a detailed

KCL-based analysis, see EE114 or section 7.2.3

Common-Base Stage
VCC
io iC β
RL Ai = Ai (0) = =
ii iE β + 1
VO+vo
io Ro
Neglecting rb, rc, re and rπ, we have
Ri Ro ≅ ro (1 + gmRS )
Ii + ii RS (large) 1 ⎛ RL ⎞ 1
Ri ≅ ⎜1 + ⎟≅
gm ⎝ ro ⎠ gm
Behavior is very similar to MOS common base stage

stage, except that
– We do not need to worry about backgate effect
– The DC current gain is not exactly unity, due to finite β
Simplified Small-Signal Model for High-Frequency Analysis
vo RL gm Cπ + Cμ 1
= ωp2 = = ωT ωp1 =
ii ⎛ s ⎞⎛ s ⎞ Cπ Cπ RL CL
⎜ 1 − ⎟⎜ 1 − ⎟
⎝ p1 ⎠⎝ p2 ⎠
The time constant associated with the load usually dominates the
frequency response, i.e. ωp1 < ωp2
Note, however, that ωp2 can be important in feedback circuits (phase
margin)

Common Gate Stage – Bulk Connection Scenarios
Cgb Cgb
Cdb Cbsub (DWELL) Cdb Cbsub (DWELL)

VDD VDD
Csb Csb
Cgs Cgs
ii ii
gm gm + gmb
ωp2,a = ωp2,b =
Cggs + Cggb + Cbsub + Cdb [1 − K(s)] Cggs + Csb
ωp2,a is always less than ωp2,b Æ Usually a bad idea to connect source to
bulk in a common g gate stage
g
Backgate Effect in the EE214 Technology (1)

Backgate Effect in the EE214 Technology (2)
Basic BJT Current Mirror
IIN IOUT = IC2

VBE
VT ⎛ VCE2 ⎞
+ IS2e ⎜1+ ⎟
IC2 ⎝ VA ⎠ IS2 ⎛ VCE2 VCE1 ⎞
Q1 Q2 Vo = VCE2 = VBE
≅ ⎜1+ − ⎟
+ IC1 ⎛ VCE1 ⎞ IS1 ⎝ VA VA ⎠
VBE – VT
IS1e ⎜1+ ⎟
– ⎝ VA ⎠
Error due to base current
IC1 IC2 ⎛ I ⎞
IIN = IC1 + IB1 + IB2 = IC1 + + ≅ IC2 ⎜ 1 + 2 C2 ⎟ for IS1 = IS2
β β ⎝ β ⎠
IOUT 1 2
≅ ≅ 1−
IIN ⎛ 2⎞ β
⎜1+ β ⎟
⎝ ⎠

BJT Current Mirror with “Beta Helper”
IIN VCC
IOUT
Q3
+ IC1 IC2 I
IE3 − IE3 = + ≅ 2 C2 assumin g IS1 = IS2
Q1 Q2 VOUT β β β
IE3 2IC2 2IC2 ⎡ 2 ⎤

IB3 = − ≅ IIN = IC1 + IB3 ≅ IC1 + ≅ IC2 ⎢1 + ⎥
β + 1 β(β + 1) β(β + 1) ⎣ β(β + 1) ⎦
IOUT 1 2
≅ ≅ 1−
IIN ⎛ 2 ⎞ β2
1+ ⎜ 2 ⎟⎟
⎜β +β
⎝ ⎠
BJT Current Mirror with Degeneration
IIN IOUT
+ Neglecting base currents

Q1 Q2
VOUT VBE1 + IC1R1 = VBE2 + IC2R2
R1 R2
–
1 ⎧⎪ ⎡⎛ IC1 ⎞ ⎛ IS2 ⎞ ⎤ ⎫⎪ R1 IOUT R1

IC2 = ⎨IC1R1 + VT ln ⎢⎜ ⎟ ⎜ ⎟ ⎥⎬ ≅ IC1 ≅
R2 ⎩⎪ ⎣⎝ IC2 ⎠ ⎝ IS1 ⎠ ⎦ ⎭⎪ R2 IIN R2
Degeneration brings two benefits

– Increased output resistance
– Reduces sensitivity of mirror ratio to mismatches in IS
Minimum VOUT for which Q2 remains forward active is increased

Differential Circuits
Vi1 + – Vo1
Vi2 – + Vo2
Enables straightforward biasing without AC coupling

Information is carried in “differential” signals that are insensitive to
“common-mode” perturbations, such as power supply noise
Fully differential circuits are increasingly used for I/O and clock-and-data
recovery (CDR) circuits to allow the use of small signals at high speeds
BJT Differential Pair
VCC
RC1
Differential Input Voltage
RC2
Vid Vi1 − Vi2
Vo1 Vo2
IC1 IC2 Differential Collector Current
Icd Ic1− Ic2
Vi1 Q1 Q2 Vi2
Differential Output Voltage
ITAIL RTAIL Vod Vo1 − Vo2
VEE
The following large signal analysis neglects rb, rc, re, finite REE and
assumes that the circuit is perfectly symmetric

Large Signal Analysis
Vbe1 Vbe2
VT VT
Vi1 − Vbe1 + Vbe2 − Vi2 = 0 IC1 ≅ IS1 e IC2 ≅ IS2 e
Vbe1 − Vbe2 Vi1 − Vi2 Vid

I VT VT VT
⇒ c1 = e =e =e
Ic2
1 αITAIL αITAIL
ITAIL = − (Ie1+ Ie2) = (Ic1+ Ic2) ⇒ Ic1 = V
Ic2 = V
α − id
VT
+ id
VT
1+ e 1+ e
⎡ ⎤
⎢ 1 1 ⎥ ⎛ Vid ⎞
Icd = Ic1 − Ic2 = αFITAIL ⎢ Vid
− V ⎥ = αFITAIL tanh ⎜ 2V ⎟
⎢ −
VT
+ id
⎥ ⎝ T⎠
⎣1 + e 1 + e VT ⎦
⎛ V ⎞
Vod = IodRL = αITAILRL tanh ⎜ id ⎟
⎝ 2VT ⎠
Plot of Transfer Characteristics
Text, p. 215 Text, p. 216
Linear region in Vod vs.

vs Vid characteristic is narrow compared to MOS
– Recall that full steering in a MOS pair occurs for Vid = 2VOV
BJT differential pair is linear only for |Vid| < VT ≅ 26 mV

Emitter Degeneration
C
Can use emitter
itt degeneration
d ti resistors
i t tto iincrease th
the range off iinputt
voltage over which the transfer characteristic of the pair is linear
For large RE, linear range is approximately equal to ITAILRE
VCC
RC RC Text, p. 217
Vo1 Vo2
Vi1 Q1 Q2 Vi2
RE RE
ITAIL
VEE
Voltage Decomposition
Common-Mode Voltages
VCC
1
Vic (Vi1 + Vi2 )
2 RC1 RC2
1
Voc (Vo1 + Vo2 ) Voc+Vod/2
2 Voc–Vod/2
Q1 Q2
Inputs Vi1 and Vi2 can be
decomposed into a combination
of differential-
differential and common
common-mode
mode Vid/2 ITAIL –V
Vid/2
voltage sources
VEE
1
Vi1 = Vic + Vid
2
Vic
1
Vi2 = Vic − Vid
2

Small Signal Model for vic = 0
Text, p. 224
v od
Define differential mode gain as A dm
v id vic = 0
Differential Mode Half Circuit
Text, p. 225
v od v v od
= −gmR id A dm = = −gmR
2 2 v id

Small Signal Model for vid = 0
Text, p. 227
v od
Define common mode gain as A cm
v id vid = 0
Common Mode Half Circuit
Text, p. 227
v oc gmR
v oc = −GmRv ic A cm = = −GmR = −
v ic 1 + 2gmRTAIL

Interaction of Common Mode and Differential Mode
v od v oc
A cdm and A dcm
v ic v id vic = 0
i vid = 0
In a perfectly balanced (symmetric) circuit, Acdm = Adcm = 0

In practice, Acdm and Adcm are not zero because of component mismatch
Acdm is
i iimportant
t t because
b it iindicates
di t th the extent
t t tto which
hi h a common-
mode input will corrupt the differential output (which contains the actual
signal information)
See
S ttext,
t section
ti 3.5.6.9
3 5 6 9 ffor a d
detailed
t il d analysis
l i
Common-Mode Rejecton
For fully differential circuits, the common-mode rejection ratio (CMRR) is

traditionally defined as
A dm
CMRR
A cdm
However, the text defines the ratio as
A dm
CMRR Text
T

A cm
This latter definition is appropriate for circuits with a differential input and
single-ended output, such as operational amplifiers.

Input-Referred DC Offsets
In
I a perfectly
f tl symmetric
t i circuit,
i it Vid = 0 yields
i ld Vod = 0
Imbalances can be modeled as input referred offsets
VCC VCC
RC1 RC2 RC RC
Vo1 Vo2 Vo1 Vo2
IB1 Vos
– +
Vi1 Q1 Q2 Vi1 Q1 Q2
Ios/2
Vi2 Vi2
IB2
IEE IEE
OFFSETS
VEE VEE
PAIR W/ MISMATCH IDEAL PAIR
Analysis
Vos − VBE1 + VBE2 = 0

⎛I ⎞ ⎛I ⎞
∴ Vos = VT ln ⎜ C1 ⎟ − VT ln ⎜ C2 ⎟
⎝ IS1 ⎠ ⎝ IS2 ⎠
⎡⎛ I ⎞ ⎛ I ⎞ ⎤ kT
= VT ln ⎢⎜ C1 ⎟ ⎜ S2 ⎟ ⎥ , where VT =
⎢⎣⎝ IC2 ⎠ ⎝ IS1 ⎠ ⎥⎦ q
If Vod = 0, then
IC1RC1 = IC2RC2
IC1 RC2
∴ =
IC2 RC1
Thus
⎡⎛ R ⎞ ⎛ I ⎞ ⎤
Vos = VT ln ⎢⎜ C2 ⎟ ⎜ S2 ⎟ ⎥
⎢⎣⎝ RC1 ⎠ ⎝ IS1 ⎠ ⎥⎦

Result
For small mismatches ΔRC << RC and ΔIS << IS, it follows that
−1
⎛ ΔRC ΔIS ⎞ ⎛ gm ⎞ ⎛ ΔRC ΔIS ⎞
Vos ≅ VT ⎜ − − ⎟=⎜ ⎟ ⎜− − ⎟
⎝ RC IS ⎠ ⎝ ID ⎠ ⎝ RC IS ⎠
And similarly
IC ⎛ ΔRC Δβ ⎞
Ios ≅ − ⎜ + ⎟ (see text, pp. 231)
β ⎝ RC β ⎠
Mismatch in IS results primarily from mismatches in the emitter areas

and the base doping
Mismatch in β results primarily from mismatches in the base width
The standard deviations of device-to-device variations in IS and β is
typically on the order of 5%
Offset Voltage Drift
dVos d ⎡ kT ⎛ ΔRC ΔIS ⎞ ⎤ Vos

= ⎢ − − ⎥=
dT dT ⎢⎣ q ⎜⎝ RC IS ⎟⎠ ⎥⎦ T
Example
– VOS was determined
d t i d tto b
be 2 mVV th
through h a measurementt att 300°K
– Means that the offset voltage will drift by 2 mV/300°K = 6.6 μV/°C
For a MOS differential pair, the offset drift is less predictable and turns
outt to
t be
b a complex
l function
f ti off severall process parameters t

Comparison of VOS for MOS and BJT Differential Pairs
−1
⎛ g ⎞ ⎛ ΔR ΔIS ⎞
VOS,BJT ≅ ⎜ m ⎟ ⎜− − ⎟
⎝ ID ⎠ ⎝ R IS ⎠
−1
⎛g ⎞ ⎛ ΔR Δ ( W / L ) ⎞
VOS,MOS ≅ ΔVt + ⎜ m ⎟ ⎜⎜ − − ⎟
⎝ ID ⎠ ⎝ R ( W / L ) ⎟⎠
? Worse Similar to BJT
The standard deviation of ΔVt can be estimated using the following

expression (Pelgrom, JSSC 10/1989)
A Vt
σΔVt ≅
WL
where Avt ≅ 5mV-μm for a typical 0.18 μm process
Numerical Example
Ignoring
I i resistor
i t mismatch
i t h ffor simplicity
i li it
Assume (gm/ID)MOS = 10 S/A, W = 5 μm, L= 0.2 μm
⎡⎛ g ⎞−1 ⎛ ΔI ⎞ ⎤
std ( VOS,BJT ) ≅ std ⎢⎜ m ⎟ ⎜ S ⎟ ⎥ = 26mV ⋅ 5% = 1.3mV
⎢⎝ ID ⎠ ⎝ IS ⎠ ⎥
⎣ ⎦
⎡ ⎛ gm ⎞ ⎛ Δ ( W / L ) ⎞ ⎤
−1
std ( VOS,MOS ) ≅ std ΔVt + ⎜
⎢ ⎟ ⎜⎜ ⎟⎟ ⎥
⎢
⎣
I
⎝ D ⎠ ⎝ ( W / L ) ⎠ ⎥⎦
2
⎛ 5mV − μm ⎞ 2
⎜ 5μm ⋅ 0.2μm ⎟⎟ (
≅ ⎜ + 100mV ⋅ 5% )
⎝ ⎠
≅ ( 5mV )2 + ( 5mV )2 = 7.1mV
MOS offset is typically 5

5-10
10 times worse than BJT

AVt Data
[Chang, TED 7/2005]

AVt improves with technology scaling
But, unfortunately, AVt scales not as fast as minimum device area
– Hence
H Vt mismatch
i t h ffor minimum
i i size
i d devices
i worsens

Ch t 5
Chapter
Two-Port
Two Port Feedback Circuit Analysis
B Murmann
B. M
Stanford University
Reading Material: Sections 8.1, 8.2, 8.3, 8.4, 8.5, 8.6, 8.8
Benefits and Costs of Negative Feeback
Negative feedback provides a means of exchanging gain for

improvements in other performance metrics
Benefits
• Reduced sensitivity (improved precision)

• Reduced distortion (more later)
• Scaling of impedance levels (up or down)
• Increased bandwidth
Costs
• Lower gain
• Potential instability

Ideal Feedback (1)
+ Sε
Si Σ a So
–
Sfb
f
Assumptions for an ideal feedback system:

1. No loading
2. Unilateral transmission in both the forward amplifier
and feedback network
So = a ⋅ Sε
Sfb = f ⋅ So ⇒ So = (Si − Sfb ) = a(Si − f ⋅ So )
Sε = Si − Sfb
Ideal Feedback (2)

So a
Closed-Loop Gain: A =
Si 1 + af a
⇒ A=
Sfb 1+ T
Loop Gain: T af =
Sε
If T >> 1, then
a 1
A≅ =
T f
The feedback loop acts to minimize the error signal, Sε, thus forcing
Sfb to
t track
t k Si. In
I particular,
ti l
⎛ a ⎞ ⎛ af ⎞
Sε = Si − f ⋅ So = Si − f ⋅ ⎜ ⎟ Si = ⎜ 1 − ⋅S
⎝ 1 + aff ⎠ ⎝ 1 + aff ⎟⎠ i
Sε T 1 Sfb ⎛S ⎞ T
∴ = 1− = and = a⋅f⎜ ε ⎟ =
Si 1+ T 1+ T Si ⎝ Si ⎠ 1+ T

Gain Sensitivity
Th
The ffeedback
db k network
t k is
i ttypically
i ll a precision
i i passivei network
t k with
ith an
insensitive, well-defined transfer function f. The forward amplifier gain is
generally large, but not well controlled.
F
Feedback
db k acts t to
t reduce
d nott only
l the
th gain,
i b butt also
l ththe relative,
l ti or
fractional, gain error by the factor 1+T
dA d ⎛ a ⎞ 1 d ⎛ 1 ⎞
= ⎜ ⎟ = +a ⎜
da da ⎝ 1+ af ⎠ 1+ af da ⎝ 1+ af ⎟⎠
(1+ af) − af 1 1
= 2
= 2
=
(1+ af) (1+ af) (1+ T)2
For a change δa in a
dA δa
δ =
δa δ =
δa
da (1+ T)2
δA δa ⎛ 1+ T ⎞ ⎛ 1 ⎞ δa
∴ = =
A (1+ T)2 ⎜⎝ a ⎟⎠ ⎜⎝ 1+ T ⎟⎠ a
The Two-Port Approach to Feedback Amplifier Design
A practical approach to feedback amplifier analysis and design is based

on constructing two-port representations of the forward amplifier and
feedback network
The two port approach relies on the following assumptions:
two-port
– Loading effects can be incorporated in the two-port model for the
forward amplifier
– Transmission through the forward amplifier is nearly unilateral
– Forward transmission through the feedback network is much less
than that through the forward amplifier
When the preceding assumptions break down, the two-port approach
deviates from
from, and is less accurate than
than, the return ratio approach
devised by Henrik Bode
But, the two-port approach can provide better physical tuition, especially
with respect
p to what happens
pp in the frequency
q y domain when the
feedback loop is “closed”
– It is basically an effort to model feedback amplifiers in the way that
Harold Black conceived them

Feedback Configurations
IIn the
th two-port
t t approachh to
t feedback
f db k amplifier
lifi analysis
l i ththere are ffour
possible amplifier configurations, depending on whether the two-port
networks are connected in SHUNT or in SERIES at the input and output
p
of the overall amplifier
At the OUTPUT
– A shunt connection senses the output voltage
– A series connection senses the output current
At the INPUT
– A shunt connection feeds back a current in parallel with the input
– A series connection feeds back a voltage in series with the input
The four possible configurations are referred to as SERIES-SHUNT,

SERIES SHUNT,
SHUNT-SHUNT, SHUNT-SERIES, and SERIES-SERIES feedback
The following pages illustrate these configurations using ideal two-port
networks
Series-Shunt Feedback
+ +
+ vε a vo
– –
vi
+ +
vfb f
– – –
vo v
a= , f = fb
vε vo
vo a a
A= = =
v i 1+ af 1+ T
In this case a, A and f are all voltage gains

Shunt-Shunt Feedback
iε
+
ii a vo
–
ifb
vo i
a= , f = fb
iε vo
vo a a
A= = =
ii 1+ af 1+ T
a and A are transimpedances; f is a transadmittance
Shunt-Series Feedback
iε
ii a io
ifb
io i
a= , f = fb
iε io
io a a
A= = =
ii 1+ af 1+ T
a, A, and f are current gains

Series-Series Feedback
+ +
vε a io
–
vi
+ +
–
vfb f
– –
io v
a= , f = fb
vε io
io a a
A= = =
v i 1+ af 1+ T
a and A are transadmittances; f is transimpedance
Note: T = af is always
y dimensionless
Closed Loop Impedances
T
To illustrate
ill t t theth influence
i fl off feedback
f db k on the
th input
i t and
d output
t t impedances
i d off an
amplifier, consider the following:
– Include finite input and output impedances in a simple, idealized two-port
model of the forward amplifier
– Assume that the feedback network has ideal input and output impedances so
as not to load the forward amplifier
Consider two examples, series-shunt and shunt-series amplifiers
SERIES-SHUNT
io
vε avε

“Ideal” Series-Shunt Impedances
Input Impedance O t t Impedance

Output I d
vi vo
Zi Zo
ii io = 0 io
vi = 0
With io = 0 With vi = 0
v o = av ε v ε + fv o = v i = 0
v i = v ε + fv o = (1+ af)v ε v o − av ε 1
= (1+ T)v ε
io =
zo
=
zo
( )
1+ af v o
vε 1⎛ 1 ⎞ 1
ii = = v = (1+ T)v o
zi zi ⎜⎝ 1+ T ⎟⎠ i zo
vi vo z
Zi = = (1+ T)z i Zo = = o
ii io 1+ T
“Ideal” Shunt-Series Impedances

Basic amplifier
p io
iε
+
ii zi
aiε zo
vo
ifb
f io
–
Input Impedance
vi
Zi
ii
v o =0
With vo = 0
io = aiε
i i= iε + fio = (1+ af) iε = (1+ T)iε vi zi
⇒ Zi = =
⎛ i ⎞ i i (1+ T)
v i = iε zi = ⎜ i ⎟ zi
⎝ 1+ T ⎠
O t t Impedance
Output I d
vo
Zo
io
i i= 0
With ii = 0
iε + fio = 0
vo
v o = (io + aiε )zo = (io + afio )zo ⇒ Zo = = (1+ T)zo
io
= io (1+ T)zo
In general:
• Negative feedback connected in series increases
the driving point impedance by (1+T)
• Negative feedback connected in shunt reduces the
driving point impedance by (1+T)
Loading Effects – Introductory Example
Consider
C id ththe ffollowing
ll i ffeedback
db k circuit
i it
Analysis methods
− Closed loop transfer function using nodal analysis
− Return ratio analysis (see EE114)
− Two-port feedback circuit analysis

Nodal Analysis
Given
v1 − vo
0 − ii
RF
vo − v1 vo
0 + g m⋅ v 1 +
RF RL
⎛⎜ RF⋅ ii + RL⋅ ii ⎞⎟ ⎛1− 1 ⎞

⎜ RL⋅ g m + 1 ⎟ vo RL − RF⋅ RL⋅ g m
⎜ g m⋅ RF
⎟
Find( v 1 , v o ) → ⎜ ⎟ A −RF⋅ ⎜ ⎟
⎜ RL⋅ ii − RF⋅ RL⋅ g m⋅ ii ⎟ ii RL⋅ g m + 1 ⎜ 1 ⎟
⎜ ⎟ ⎜1+ g m⋅ RL ⎟
⎝ RL⋅ g m + 1
⎠ ⎝ ⎠
No information about loop gain (which we need e.g. for stability analysis)
Return Ratio Analysis

RR d
A A inf ⋅ + A inf −RF d RL RR g m⋅ RL
1 + RR 1 + RR
⎛ R ⎞
⎛1− ⎞
⎜ g m⋅ RL − L ⎟ ⎜
1
⎟
g m⋅ RL RL ⎜ RF⎟ g m⋅ RF
−RF + −RF⎜ −RF⋅ ⎜ ⎟
1 + g m⋅ RL ⎟
A
1 + g m⋅ RL 1 + g m⋅ RL
⎝ ⎠ ⎜ 1 ⎟
⎜1+ g m⋅ RL ⎟
⎝ ⎠
The result for the closed loop gain (A) matches the nodal analysis perfectly
In addition,
addition we have determined (along the way) the loop gain (RR)
– This is useful for stability analysis
The return ratio method is accurate and general
The two-port method aims to sacrifice some of this accuracy and generality
in exchange for better intuition and less computational effort
– The involved approximations follow from the typical design intent for
each of the four possible approximations

Shunt-Shunt Feedback Model
iε
+
ii a vo
–
ifb
RF feeds back a current that is proportional to the output voltage

– The appropriate two-port model to use for this amplifier is therefore
the “shunt-shunt” configuration
We wish to identify proper “a”
a and “ff “ blocks that model our circuit
The key issue is that “a” and “f” are not perfectly separable without
making any approximations
– RF is responsible for feedback
feedback, but also affects the behavior of “a”
a
y-Parameter Model for the Feedback Network (1)

1 1
y11f = y12f = −
RF RF
1 1
y 21f = − y 22f =
RF RF
Final steps
– Absorb y11 and y22 into forward amplifier
– Neglect feedforward through feedback network (y21)
• This is justified by the usual design intent: we do not want the
feedforward through the feedback network to be significant!

Identification of “a” and “f”
iε
+
ii a vo
–
ifb
1 vo v1 RL⋅ RF RL⋅ RF
f − a ⋅ −g m⋅ ⋅ RF af g m⋅
RF v 1 ie RL + RF RL + RF
1 1 1
A ⋅ RF
f
1+
1 1 RF + RL
aff 1+ ⋅
g m RF⋅ RL
Comparison and Generalization
Note that for RL << RF (i.e. small feedforward)

– The product of a and f approaches the true loop gain (RR)
– The two-port closed-loop gain expression (A) approaches the nodal
analysis and return ratio result
The approach illustrated in the previous example can be generalized to

cover all four feedback configurations
For all four configurations,
configurations the following analysis steps apply
– Identify input and output variables and feedback configuration
– Find feedback function “f”
– Add loading impedances to input and output port of the basic
amplifier “a”
– Perform calculations using ideal two-port feedback equations

General Analysis for Shunt-Shunt Feedback
Forward amplifier
p
iS

Summing currents at the input and output of the overall amplifier
iS = (yS + y11a + y11f )v i + (y12a + y12f )v o

0 = (y21a + y21f )v i + (yL + y22a + y22f )v o
Define
yi y S + y11a + y11f
yo yL + y 22a + y 22f
Then
yo
vi = − v
y21a + y21f o
⎛ −yo ⎞
iS = yi ⎜ ⎟ v o + (y12a + y12f )v o
⎝ y21a + y21f ⎠
⎛ 1 ⎞
=⎜ ⎟ ⎡⎣ −yiyo + (y21a + y21f )(y12a + y12f ) ⎤⎦ v o
⎝ y21a + y21f ⎠
vo −(y
(y21a + y21f )
∴ =
iS yiyo − (y21a + y21f )(y12a + y12f )
⎛ y + y21f ⎞
− ⎜ 21a ⎟
⎝ yiyo ⎠
=
⎛ y + y21f ⎞
1− ⎜ 21a ⎟ (y12a + y12f )
⎝ yiyo ⎠
Comparing this result with the ideal feedback equation

vo a
=A=
is 1+ af
it is apparent that a feedback representation can be used by defining
y 21a + y 21f
a −
yi y o
f y12a + y12f

For the preceding definitions of a and ff, it is difficult to establish equivalent
circuits for these functions. However, the situation can be simplified by
realizing that it may often be possible to neglect reverse transmission in
the forward amplifier and forward transmission in the feedback network.
That is, it can often be assumed that
y12a << y12f
and
y21a >> y21f
in which case
⎛ −y21a ⎞
⎜ yy ⎟ y21a
vo ⎝ i o ⎠ a=−
A= = ⇒ yiyo
iS ⎛ −y ⎞
1+ ⎜ 21a ⎟ y12f f = y12f
⎝ yiyo ⎠
For the simplified definitions,

definitions it is possible to identif
identify separate eq
equivalent
i alent
circuits for a and f :
yi yo
New forward amplifier
iS
yi = yS + y11a + y11f
yo = yL + y22a + y22f
New feedback network
The admittances yS, y11a, y22f and yL have been “pulled” into the forward
amplifier. Basically, the “loading” of the feedback network, as well as the
source and load admittances, is absorbed in the equivalent forward
amplifier.

Example – Op Amp w/ Shunt-Shunt Feeback
iS
Small-signal equivalent circuit:

Feedback network
ro
iS ri
I order
In d to d determine
i theh lloading
di off the
h ffeedback
db k networkk on the
h fforward
d
amplifier, the y parameters of the feedback network are first determined
using the following circuit :
i1 1
y11f = =
v1 RF
v 2 =0
i2 1
y22f = =
v2 RF
v1 =0
i1 1
y12f = =− =f
v2 RF
v1 =0
Also, y21f = –1/RF, but it is neglected in comparison with y21a

Th overallll circuit
The i i can now b be separated
d iinto fforward
d and
d ffeedback
db k paths,
h
with the loading of the feedback network included within the forward path
Forward amplifier
f
ro
iS ri
To determine the forward amplifier gain

gain, a
a, break the feedback loop at the
“output” of the feedback network by setting ifb = 0.
Then ⎛ r i RF ⎞
v1 = (r i PRF )iS = ⎜ ⎟ iS
⎝ r i + RF ⎠
⎛ R ⎞
vo = − ⎜ ⎟ a v v1 where R RF RL
⎝ R + ro ⎠
Thus
vo ⎛ r i RF ⎞ ⎛ R ⎞
a= = −a
av ⎜ ⎟⎜ ⎟
iS
i fb = 0 ⎝ r i + RF ⎠ ⎝ R + ro ⎠
Since f = –1/RF, the loop

p gain,
g , T = af,, is
⎛ r i ⎞ ⎛ R PR ⎞ ⎛ ri ⎞ ⎛ RLRF ⎞
F L
T = av ⎜ ⎟⎜ ⎟ = av ⎜ ⎟⎜ ⎟
⎝ r i + RF ⎠ ⎝ RF PRL + ro ⎠ ⎝ r i + RF ⎠ ⎝ RLRF + roRF + roRL ⎠

The input and output impedances of the equivalent forward amplifier are
zia = RF || ri
zoa = ro || RF || RL
Since the feedback network is connected in shunt at both the input and
output of the forward amplifier, the closed-loop input and output
impedances are
zia
i
RF || ri
Zi = =
1+ T 1+ T
zoa ro || RF || RL
Zo = =
1+ T 1+ T
Series-Series Feedback
In a series-series feedback amplifier,
p the forward amplifier
p and feedback
network share common currents at the input and output. Therefore, open
circuit impedance parameters (z parameters) are used to characterize the
two-port networks.
v1 = z11 i1 + z12 i2
v 2 = z 21 i1 + z 22 i2
where
v1 v1
z11 z12
i1 i i2 i
2 =0 1=0
v2 v2
z21 z22
i1 i2 = 0
i2 i1 = 0

Series-Series Feedback, cont’d
The two-port representation of a series-series feedback amplifier is then

Forward amplifier
io
ii
vS
Series-Series Feedback, cont’d
Summing voltages at the input and output

v S = (z S + z11a + z11f )ii + (z12a + z12f )io
0 = (z
( 21a + z 21f )i i + (z
( L + z 22a + z 22f )io
Define
zi zS + z11a + z11f
zo zL + z22a + z22f
Again,
g , neglect
g reverse transmission through
g the forward amplifier
p and
feedforward through the feedback network; that is, assume
z12a << z12f

and
z 21a >> z 21f

Series-Series Feedback Equations
Under the preceding assumptions, the series-series feedback amplifier

can be represented by a two-port model with
⎛ −z ⎞
21a
⎜ ⎟
io ⎝ z i zo ⎠ a
A= = =
vS ⎛ −zz ⎞ 1+ af
1+ ⎜ 21a ⎟ z12f
⎝ z i zo ⎠
where
z 21a
a=−
z i zo
f = z12f
Series-Series Feedback Equivalent Two-Port Networks
Equivalent two
two-port
port networks can now be identified for a and f in which the
loading of the feedback network is included in the forward amplifier
vS

Series-Series Triple
io
AC circuit :
Q3 RL
RS Q2
RC2
Q1 iE3
+ RC1
ii iE1
vS ~
–
RF
RE1 RE2
Feedback Network
The forward amplifier in this circuit is NOT a two-port network because

iE1 ≠ ii and iE3 ≠ io. However,
However because iE1 and iE3 are closely related to ii
and io, a two-port approach to feedback analysis can still be used.
Begin
g byy representing
p g the feedback network as a two-port
p network.
io
Q3 RL
RS Q2
RC2
Q1 iE3
+ RC1
ii iE1
vS ~
–
z11f z22f
+ +
~ z12f iE3 z21f iE1 ~
– –
At the output, simply recognize that the feedback network “senses” iE3
rather than io, and that
i
iE3 = o
α3
In effect, α3 is outside the feedback loop

At the input,
input consider the following small-signal equivalent circuit
RS
+ ii +
vS vπ1 rπ1 gm1vπ1
– –
iE1 z11f
+
z12f iE3
–
v S = iiRS + v π1 + iE1z11f + z 12f iE3

io
∴ v S − z 12f ⋅ = i R + v π1 + iE1z11f
α3 i S
From this equation it is apparent that, although the z12f feedback voltage
generator is in the emitter of Q1, it is still in series with, and subtracts
from, the input voltage source, vS. Thus, the z12f generator can be moved
f
from the
th emitter
itt tot the
th base
b off Q1
Next,
N t to
t determine
d t i the
th z parameters
t for
f the
th feedback
f db k network,
t k consider
id the
th
following circuit
RF v1
z 11f = = RE1 || (RF + RE2 )
+ + i1
i2 =0
i1 v1 RE1 RE2 v2 i2
– – v2
z 22f = = RE2 || (RF + RE1)
i2
i1 =0
⎛ ⎞
v ⎛ RE1 ⎞ v 2 ⎛ RE1 ⎞
z 12f = 1 =⎜ ⎜ ⎟= z
⎟ ⎟ ⎜⎝ RE1 + RF ⎟⎠ 22f
i2 ⎝ RE1 + RF ⎠ ⎜ i 2
i1 =0 ⎝ i1 =0 ⎠
⎛ RE1 ⎞ ⎡ RE2 (RE1 + RF ) ⎤ RE1 RE2

=⎜ ⎟ ⎢ ⎥=
⎝ RE1 + RF ⎠ ⎣ RE1 + RE2 + RF ⎦ RE1 + RE2 + RF
z21f = z12f, but z21f is neglected in comparison with z21a

Based
B d on th
the preceding
di results,
lt th
the series-series
i i ttriple
i l can b
be modeled
d l d
with the following equivalent circuit
io
Q3 RL
RS Q2
RC2
Q1 iE3
RC1
–
~ vfb=vf
+
+
vS ~ RE1 RF RF RE2
–
+
RE2 vf RE1
–
In this circuit we have managed to “break” the loop at the output of the
feedback network.
network Thus
Thus, the circuit can be used to determine a
a, f and T
T.
Note that a and f for the series-series triple can be defined in terms of
either io or iE3. If
io i
A= = α 3 E3
vS vS
and a and f are defined with respect to io, then
z12f 1 ⎛ RE1RE2 ⎞
f= =
α3 α 3 ⎝ RE1 + RE2 + RF ⎟⎠
⎜
As T = af becomes large
1 ⎛ R + R + RF ⎞
A≅ = α3 ⎜ E1 E2 ⎟
f ⎝ RE1RE2 ⎠
Thus,, A is not desensitized to α3 by

y the feedback loop
p

Series-Shunt Feedback
In a series
series-shunt
shunt feedback amplifier,
amplifier the forward amplifier and feedback
network share the same input current and output voltage. Therefore a
hybrid h-parameter representation is used for the two-port networks.
v1 = h11 i1 + h12 v 2
i2 = h21 i1 + h22 v 2
where
v1 v1
h11 h12
i1 v 2 =0
v2 i1 = 0
i2 i2
h21 h22
i1 v 2 =0
v2 i1 = 0
Series-Shunt Feedback, cont’d
Thus, the two-port model for a series-shunt feedback circuit is
Forward amplifier
ii
vS

Series-Shunt Feedback, cont’d
Summing voltages at the input and currents at the output,
v S = (zS + h11a + h11f )ii + (h12a + h12f ) v o

0 = (h21a + h21f )i i + (yL + h22a + h22f )io
Define
zi zS + h11a + h11f
yo yL + h22a + h22f
and neglect reverse transmission through the forward amplifier and

h12a << h12f

and
h21a >> h21f
Series-Shunt Feedback Equations
With the simplifying assumptions, the series-series feedback amplifier can

be represented by a two-port model with
⎛ −h ⎞
21a
⎜ ⎟
vo z y
⎝ i o ⎠ a
A= = =
vS ⎛ −hh ⎞ 1+ af
1+ ⎜ 21a ⎟ h12f
⎝ z i yo ⎠
where
h21a
a=−
z i yo
f = h12f

Series-Shunt Feedback Equivalent Two-Port Networks
Equivalent
E i l t ttwo-portt circuits
i it can now b be id
identified
tifi d for
f a and
d f in
i which
hi h th
the
loading of the feedback network is included in the forward amplifier

ii
+
zi yo vo
–
vS
Shunt-Series Feedback
In a shunt-series feedback circuit,
circuit the forward amplifier and feedback
network share the same input voltage and output current. Thus, a hybrid g-
parameter representation is used for the two-port networks.
i1 = g11v1 + g12 i2
v 2 = g21v1 + g22 i2
where
i1 i1
g11 g12
v1 i i2
2 =0 v1 = 0
v2 v2
g21 g22
v1 i2 =0
i2 v1=0

Shunt-Series Feedback, cont’d
The two-port model for a shunt-series feedback amplifier is thus
Forward amplifier
iS
Shunt-Series Feedback, cont’d
Summing currents at the input and voltages at the output,
iS= (yS + g11a + g11f )v i + (g12a + g12f )io

0 = (g21a + g21f )v i + (zL + g22a + g22f )io
Define
yi y S + g11a + g11f
zo zL + g22a + g22f
and neglect reverse transmission through the forward amplifier and

g12a << g12f

and
g21a >> g21f

Shunt-Series Feedback Equations
With the simplifying assumptions the shunt-series feedback circuit can

described in the form of the ideal feedback equation
⎛ −g21a ⎞
⎜ yz ⎟
i ⎝ i o ⎠ a
A= o = =
iS ⎛ −gg ⎞ 1+ af
1+ ⎜ 21a ⎟ g12f
⎝ yi zo ⎠
where
g21a
a=−
y i zo
f = g12f
Shunt-Series Feedback Equivalent Two-Port Networks
Based on the above definitions and assumptions, equivalent two-port

networks for a shunt-series amplifier can be defined as follows
N
New fforward
d amplifier
lifi
zo
+ io
iS vi yi
–

Shunt-Series Feedback Pair
io
AC circuit:
Q2
RL
Q1
+ RC1
iS vi RS iE2
–
RF
RE
Feedback network
The forward amplifier in this circuit is not a two-port network

b
because io ≠ iE2. However,
H th
the circuit
i it can bbe analyzed
l d iin a ffashion
hi
similar to the series-series triple. The feedback network can be
represented by a two-port characterized by g parameters.
io
Q2 RL
Q1
+ RC1
iS vi iE2
RS
–
g22f
+
g11f g12f iE2 ~ g21f vi
–
The g parameters for the feedback network can be determined from the
following circuit :
i1 RF
+ +
v1 ~ RE v2 i2
– –

i1 1
g11f = =
v1 RE + RF
i2 = 0
v2
g 22f = = RE || RF
i2
v1 = 0
i1 RE
g12f = =−
i2 RE + RF
v1 = 0
v2
g21f = = − g12f
v1
i2 = 0
g21f is neglected in comparison with g21a
The shunt-series p
pair can then be redrawn as follows :
io
Q2 RL
Q1
+ RC1
iS vi iE2
RF+RE RS
–
iE2 = –iiF iF RF RE
A i we’ve
Again, ’ managed d tto b
break
k th
the lloop att th
the output
t t off th
the ffeedback
db k
network. If a and f are defined in terms of io, then
io i
A= = α 2 E2
iS iS
ifb iF g 1 ⎛ RE ⎞
f= = − = 12f = −
io io α2 α 2 ⎜⎝ RE + RF ⎟⎠

Chapter 6
Frequency Response of
Feedback Amplifiers
B. Murmann
Stanford University
y
Reading Material: Section 9.1, 9.2, 9.3, 9.4, 9.5
Gain and Bandwidth
Consider a feedback amplifier with a single pole in the response of the

forward-path amplifier and feedback that is frequency independent.
+
vi – a(s) vo
–
vfb
f
a0
a(s) =
1− s p1
v o (s) a(s) a(s)

A(s) = =
v i (s) 1+ a(s) ⋅ f 1+ T(s)
where
T(s) a(s) ⋅ f = "Loop
Loop Gain
Gain"

a0
1− s p1 a0
A(s) = =
a0 f s
1+ 1− + a0 f
1− s p1
1 p1
a0 1
= ⋅
1+ a0 f s⎛ 1 ⎞
1−
p1 ⎜⎝ 1+ a0 f ⎟⎠
1
= Ao ⋅
⎡ s ⎤
⎢1
1− ⎥
⎣ p1(1+ T0 ) ⎦
where
a0
A 0 = A(0) =
1+ a0 f
T0 = T(0) = a(0) ⋅ f = a0 f = "Low Frequency Loop Gain"
Thus, feedback reduces the gain by (1+T0) and increases the –3dB
bandwidth by (1+T0) for a “one-pole” forward-path amplifier.
The Gain x Bandwidth (GBW) product remains constant.
20 log10 a0
20 log10 |a(jω)|
20 log10 (1+T0)
20 log10 |A(jω)|
20 log10 A0
|p1|
(1+T0)|p1|

Locus of the pole of A(s) in the s-plane:
jω
s plane
s-plane
x x σ
(1+T0)p1 p1
Pole “moves” from p1 to (1+T0)p1
Note that
⎛a ⎞
20 ⋅ log
g10 a0 − 20 ⋅ log g10 ⎜ 0 ⎟
g10 A0 = 20 ⋅ log
⎝ A0 ⎠
= 20 ⋅ log10 (1+ T0 )
≅ 20 ⋅ log
g10 T0 when T0 >> 1
At the frequency ω0 = (1+T0)|p1|
a(jω 0 ) = A0
and therefore
a0 f
T(jω 0 ) = a(jω 0 ) ⋅ f = A 0 f =
1+ a0 f
≈1
Thus, ω0 is the unity-gain bandwidth of the loop gain, T(s).

Instability
At a frequency where the phase shift around the loop of a feedback

amplifier reaches ±180o the feedback becomes positive. In that case,
pg
if the loop gain is g
greater than unity,
y, the circuit is unstable.
For a “single-pole” forward path amplifier stability is assured because

the maximum phase shift is 90o. However, if a(s), or in general T(s),
has multiple poles
poles, the amount of loop gain that can be used is
constrained.
y of a feedback amplifier
The stability p can be assessed from:
– Nyquist diagram (polar plot of loop gain with frequency as a parameter)
– Bode
B d plot
l t (plot
( l t off loop
l gain
i and
d phase
h as ffunctions
ti off ffrequency))
– Locus of poles (root locus) of A(s) in the s-plane
Bode Stability Criterion
A feedback system is unstable when |T(jω)| > 1 at the frequency where

Phase[T(jω)] = -180°
Phase margin
1 Æ ω0
– Defined at the frequency where |T(jω)| =1
PM = 180° + Phase ⎡⎣T ( jω0 ) ⎤⎦
Gain margin
– Defined at the frequency where Phase[T(jω)] = -180° Æ ω180
1
GM =
T ( jω180 )

Example
20 log10 A0
Gain Margin
ω0 | p2 |
Phase Margin
Practical Phase Margins
P
Practical
ti l circuits
i it ttypically
i ll use phase
h margins
i greater
t 45°
– For continuous time amplifiers, a common target is ~60°
– For switched capacitor circuits, a phase margin of ~70° is desirable
• See
S EE315A
In order to see the need for phase margin >45°, investigate the closed-
loop behavior of the circuit at ω = ω0
1
T( jω0 ) = a( jω0 ) ⋅ f = 1 ⇒ a( jω0 ) = (assuming f is real)
f
a( jω0 )
A( jω0 ) =
1 + a( jω0 ) a( jω0 )
a( jω0 ) a( jω0 )
= jφ[a( jω0 )]
=
1+ e 1 + e j(PM−180°)

PM = 45o
a(jω 0 ) a(jω 0 )
(jω 0 ) =
A(jω − j135°
=
1+ e 1− 0.7 − 0.7j
a(jω 0 )
=
0.3 − 0.7j
a(jω 0 ) 1.3
∴ A(jω 0 ) = = ≅ 1.3A0
0.76 f
Thus, |A(jω0)| “peaks” at ω = ω0, it’s nominal –3dB bandwidth.
PM = 60o
a(jω 0 ) a(jω 0 )
A(jω 0 ) = − j120°
=
1+ e 1− 0.5 − 0.87j
a(jω 0 )
=
0.5 − 0.87j
1
∴ A(jω 0 ) = a(jω 0 ) = ≅ A0
f
PM = 90o
a(jω 0 ) a(jω 0 )
A(jω 0 ) = − j90°
=
1+ e 1− j
a(jω 0 ) 0.7
∴ A(jω 0 ) = = ≅ 0.7A0
1.4 f

Closed-Loop Response for Various Phase Margins
Text, p. 632
Frequency Compensation (1)
Frequency compensation refers

f to the means by which the frequency
f
response of the loop gain in a feedback amplifier is altered so as to ensure
adequate phase margin under the expected closed-loop conditions.
Because operational amplifiers must often be compensated for use with a

variety of feedback networks, compensation is usually accomplished by
modifying only the forward path of the loop (i.e. the op-amp itself). In
special
i l purpose wideband
id b d amplifier
lifi ddesign,
i th
the response off th
the feedback
f db k
network may also be altered.
Several types
yp of frequency
q y compensation
p are used in p
practice,, e.g.
g
Narrowbanding (lag compensation)
Feedforward (lead compensation)
Pole splitting (Miller compensation, cascode compensation)
Feedback (phantom) zero compensation

Narrowbanding (1)
C
Create
t addominant
i t pole
l iin a(s)
( ) tto rollll off
ff |T(j
|T(jω)|
)| att a frequency
f low
l
enough to ensure adequate phase margin
(f=1)
Text, p. 634
Narrowbanding (2)
N
Note
t th
thatt in
i the
th example
l off the
th previous
i slide
lid ((with
ith ff=1,
1 and
d PM
PM=45°),
45°) the
th
closed-loop bandwidth is limited to approximately ωp1, the frequency of the
closest non-dominant pole
Thi
This can b t bl if ωp1 is
be acceptable i sufficiently
ffi i tl llarge, as th
the e.g. case ffor th
the
pole introduced by a cascode
Consider e.g. the amplifier below
– Cp introduces
i t d a non-dominant
d i t pole
l att hi
high
h ffrequencies
i
– CL is adjusted until the circuit achieves the desired phase margin
• Therefore, this type of narrowbanding is called “load compensation”

Two-Stage Amplifier
But, what if we would like to stabilize an amplifier that has two poles at
relatively low frequencies?
Consider e.g. the two-stage amplifier shown below, and assume that
ωp1=1/R1C1 and ωp2=1/R2C2 are comparable
Pole Splitting (1)
R1 R2
Cc vo
vi C1 C2
gm1 gm2
Purposely connect an additional capacitor between gate and drain of M2

(Cc = “compensation capacitor")
Two interesting things happen
– Low frequency input capacitance of second stage becomes large –
exactly what we need for low ωp1
– At high frequencies, Cc turns M2 into a “diode connected device” –
low impedance,
p g ωp2 !
, i.e. large

Pole Splitting (2)
F
From the
th generall CS/CE stage
t analysis
l i off Ch
Chapter
t 4
4, we can
approximate resulting poles and zeros as follows
– See also text, section 9.4.2
1 gm2CC gm2
p1 ≅ − p2 ≅ − z=+
gm2R2 R1CC C1C2 + CC (C1 + C2 ) CC
Increasing Cc reduces ωp1, and increases ωp2

− A very nice “knob” for adjusting the phase margin of the circuit
The zero introduced due to Cc occurs at high frequencies and is not
always troublesome
In cases where the zero affects stability,
y several options
p exists to
mitigate the problem
− Nulling resistor, cascode compensation, etc.
− See EE114, EE315A
Pole Splitting (3)
Text, p. 642
c
c c

Intuitive Derivation of Pole Split Using Shunt-Shunt Feedback
gm2R2R1
a(s) = − f(s) = −sCf
(1 + sR1 [C1 + Cc ]) (1 + sR2 [C2 + Cc ])
Mag ( jω)
a(s)
1
f(s)
ω
Nested Miller Compensation
Text,, p.
p 655
Mag ( jω) Cm2

Cm1
gm1, gm2
gm0, gm1, gm2

Feedforward Compensation
e.g. Thandri, JSSC 2/2003
|a(jω)|
Parallel path through gm3 dominates
transfer function at high frequencies
and returns the circuit behavior back
to first order
ω
|pd| |p1| |z1| The doublet p1, z1 can make it
φ(jω) difficult to achieve a fast transient
ω response
– π/2
– See Kamath, JSSC 12/1974
–π
Feedback Zero Compensation
Example:
Mag ( jω)
a(s)
( ) Due to the zero introduced in the
feedback network
network, T(j
T(jω)) behaves like a
first order system near unity crossover
1
f(s) Closed-loop bandwidth is approximately
equal to the frequency of the zero in the
ω feedback network
– Can be far beyond second pole

Introduction to Root Locus Techniques: Three Pole Amplifier
C
Consider
id a ffeedback
db k network
t k consisting
i ti off a fforward
d amplifier
lifi with
ith th
three
identical poles, and a feedback network with a constant transfer function f
a0
3
⎛ s⎞
⎜1− ⎟
a0 a(s) ⎝ p 1⎠ a0
a(s) = A(s) = = = T0 = a0 f
⎛ s⎞
3
1 + a(s)f a0 ⎛ s⎞
3
1+ a f
⎜1− ⎟ ⎛ s⎞
3
⎜ 1 − ⎟ + T0
⎝ p1 ⎠ ⎜ 1 − ⎟ ⎝ p1 ⎠
⎝ p 1⎠
The poles of A(s) are therefore the solution to
3
⎛ s⎞
⎜ 1 − ⎟ + T0 = 0
⎝ p1 ⎠
3
⎛ s⎞
⎜ 1 − ⎟ = −T0
⎝ p1 ⎠
⎛ s⎞ ⎛ s⎞ ⎛ s⎞
⎜ 1 − ⎟ = 3 −T0 = − 3 T0 or ⎜ 1 − ⎟ = 3 T0 e j60° or ⎜ 1 − ⎟ = 3 T0 e− j60°
⎝ p1 ⎠ ⎝ p1 ⎠ ⎝ p1 ⎠
(
s1 = p1 1 + 3 T0 )
s2 = p (1 −
1
3 T0 e j60° ) “root locus”
s3 = p (1 −
1
3 T0 e − j60°
)
0 = 1 − Re ( 3 T0 e j60° )
0 = 1 − 3 T0 cos(60°)
⇒ T0 = 8

Root-Locus Method
We can generalize the above example to gain insight into the frequency
response of any feedback amplifier by examining the “movement” of the closed-
loop poles in the s-plane as a function of the low-frequency loop gain, T0.
Consider a generalized feedback amplifier with both a and f dependent on
frequency.
+
vi – a(s) vo
–
vfb
f(s)
v o (s) a(s) a(s)

A(s) = =
v i (s) 1+ a(s)f(s) 1+ T(s)
The poles of A(s) are the roots of 1 + T(s) = 0

0.
In general,
1+ a1s + a 2s2 + ⋅ ⋅ ⋅ Na (s)

a(s) = a0 2
= a0
1+ b1s + b 2s + ⋅ ⋅ ⋅ Da (s)
and
1+ c1s + c 2s2 + ⋅ ⋅ ⋅ Nf (s)
f(s) = f0 2
= f0
1+ d1s + d2s + ⋅ ⋅ ⋅ D f (s)
Thus,
a0 Na (s)D f (s)
A(s) =
Da (s)D f (s) + T0 Na (s)Nf (s)
where T0 = a0f0 .

The zeros of A(s) are the zeros of a(s) and the poles of f(s).
Th poles
The l off A(s)
A( ) are the
th roots
t off :
Da (s) D f (s) + T0 Na (s)Nf (s) = 0
As T0 increases from 0 to ∞, the poles of A(s) move in the

s-plane from the poles of T(s) to the zeros of T(s).
The Root Locus is the paths the roots of 1 + T(s) = 0 trace in

the s-plane
s plane as T0 varies from 0 to ∞.
The root-locus construction rules follow from the equation

Na (s) ⋅Nf (s)
1+ T(s) = 1+ T0 ⋅ =0
Da (s) ⋅D f (s)
or equivalently
q y
Na (s) ⋅Nf (s)
T0 ⋅ = −1
Da (s) ⋅D f (s)
Thus
(1− s za1)(1− s za2 ) ⋅ ⋅ ⋅ (1− s z f1)(1− s z f 2 ) ⋅ ⋅ ⋅
T0 ⋅ = −1
)( s pa2 ) ⋅ ⋅ ⋅ ((1− s p f1)(1−
((1− s pa1)(1− )( s p f 2 ) ⋅ ⋅ ⋅
where
za1,za2 ,... = zeros of a(s)
zeros of T(s)
z f1,zf2 ,... = zeros of f(s)
pa1,pa2 ,... = poles of a(s)
poles of T(s)
pf1,pf2 ,... = poles
l off f(s)
f( )

The above equation can be rewritten as
⎡ (−pa1)(−pa2 ) ⋅ ⋅ ⋅ (−p f1)(−p f 2 ) ⋅ ⋅ ⋅ ⎤

T0 ⋅ ⎢ ⎥
⎣ (−za1)(−z a2 ) ⋅ ⋅ ⋅ (−z f1)(−z f 2 ) ⋅ ⋅ ⋅ ⎦
⎡(s − za1)(s − za2 ) ⋅⋅⋅ (s − zf1)(s − zf 2 ) ⋅⋅⋅⎤
×⎢ ⎥ = −1
⎣(s − pa1)(s − pa2 ) ⋅⋅⋅ (s − pf1)(s − pf 2 ) ⋅⋅⋅⎦
Expect all poles of T(s) to be in the left half plane (LHP).
If all zeros of T(s) are in the LHP, or if there are an even

number of zeros in the RHP RHP, then the first bracketed term in
the above equation is positive, in which case
⎡ p p ⋅ ⋅ ⋅ p f1 p f 2 ⋅ ⋅ ⋅ ⎤
T0 ⋅ ⎢ a1 a2 ⎥
⎢⎣ z a1 z a2 ⋅ ⋅ ⋅ z f1 z f 2 ⋅ ⋅ ⋅ ⎥⎦
⎡(s − za1)(s − za2 ) ⋅⋅⋅ (s − zf1)(s − zf 2 ) ⋅⋅⋅⎤
×⎢ ⎥ = −1
⎣(s − pa1)(s − pa2 ) ⋅⋅⋅ (s − pf1)(s − pf 2 ) ⋅⋅⋅⎦
Values of s satisfying the above equation are the poles of A(s)

A(s).
These values simultaneously fulfill both a phase condition and
a magnitude condition, and these conditions define the points
of the root locus.
Phase Condition
⎡⎣ ∠(s − za1) + ∠(s − za2 ) + ⋅ ⋅ ⋅ + ∠(s − z f1) + ∠(s − z f 2 ) + ⋅ ⋅ ⋅⎤⎦

− ⎡⎣ ∠(s − pa1) + ∠(s − pa2 ) + ⋅ ⋅ ⋅ + ∠(s − p f1) + ∠(s − p f 2 ) + ⋅ ⋅ ⋅⎤⎦
= (2n − 1)π
Magnitude Condition
⎡ p p ⋅ ⋅ ⋅ p f1 p f 2 ⋅ ⋅ ⋅ ⎤ ⎡ s − z a1 s − z a2 ⋅ ⋅ ⋅ s − z f1 s − z f 2 ⋅ ⋅ ⋅ ⎤
T0 ⋅ ⎢ a1 a2 ⎥ ⋅⎢ ⎥ = +1
⎢⎣ z a1 z a2 ⋅ ⋅ ⋅ z f1 z f 2 ⋅ ⋅ ⋅ ⎥⎦ ⎢⎣ s − pa1 s − pa2 ⋅ ⋅ ⋅ s − p f1 s − p f 2 ⋅ ⋅ ⋅ ⎥⎦

For the case where there are an odd number of zeros in the RHP,
the magnitude condition remains the same as above, but the
phase condition is changed. Specifically,
⎡ p p ⋅ ⋅ ⋅ p f1 p f 2 ⋅ ⋅ ⋅ ⎤ ⎡ s − z a1 s − z a2 ⋅ ⋅ ⋅ s − z f1 s − z f 2 ⋅ ⋅ ⋅ ⎤
T0 ⋅ ⎢ a1 a2 ⎥ ⋅⎢ ⎥ = +1
⎢⎣ z a1 z a2 ⋅ ⋅ ⋅ z f1 z f 2 ⋅ ⋅ ⋅ ⎥⎦ ⎣⎢ s − pa1 s − pa2 ⋅ ⋅ ⋅ s − p f1 s − p f 2 ⋅ ⋅ ⋅ ⎥⎦
and
⎡⎣ ∠(s − za1) + ∠(s − za2 ) + ⋅ ⋅ ⋅ + ∠(s − z f1) + ∠(s − z f 2 ) + ⋅ ⋅ ⋅⎤⎦

− ⎡⎣ ∠(s − pa1) + ∠(s − pa2 ) + ⋅ ⋅ ⋅ + ∠(s − p f1) + ∠(s − p f 2 ) + ⋅ ⋅ ⋅⎤⎦
= 2nπ
The rules for constructing the root locus are based on the phase
condition. The magnitude condition determines where, for a
given T0, the poles of A(s) actually lie on along the locus.
To determine if a point X in the s-plane lies on the root locus, draw

vectors from the poles and zeros of T(s) to the point X. The
angles of these vectors are then used to check the phase
condition.

Root-Locus Construction Rules
Rule 1:
Branches of the root locus start at the poles of T(s), where
T0 = 0,
0 and terminate on the zeros of T(s)
T(s), where T0 = ∞.
If T(s) has more poles than zeros, some branches
terminate at infinity.
Rule 2:
The root locus is located along the real axis whenever
there is an odd number of poles and zeros of T(s) between
that portion of the real axis and the origin of the s-plane.
Rule 3:
All segments of the locus on the real axis between pairs of
poles, or pairs of zeros, must branch out from the real
axis
axis.
Rule 4:
Locus is symmetric with respect to the real axis because
complex roots occur only in conjugate pairs.
Rule 5:
Branches leaving the real axis do so at right angles to it.
Rule 6:
Branches break away from the real axis at points where
the vector sum of reciprocals of distances to the poles of
( ) equals
T(s) q the vector sum of reciprocals
p of distances to
the zeros of T(s).
Rule 7:
Branches
B h th thatt terminate
t i t att infinity
i fi it do
d so asymptotically
t ti ll tto
straight lines with angles to the real axis of
(2n –1)π/(Np – Nz),
where Np = # of poles of T(s) and Nz = # of zeros of T(s)
T(s).

R l 8:
Rule 8
The asymptotes of the branches terminating at infinity all
intersect the real axis at a single point given by
σa =
[ ] [
Σ poles of T(s) − Σ zeros of T(s) ]
Np − Nz
2-Pole Example
jω
p2 p1 σ

3-Pole Example
Assume
T0
T(s) =
(1− s / p1)(1− s / p 2 )(1− s / p3 )
where
p1 = −1× 106 sec−1
p2 = −2 × 106 sec−1
p3 = −4 × 106 sec−1
3-Pole Example, cont’d
σa
σi

Breakaway Point, σi
From Rule 6
1 1 1
+ + =0
σi + 1 σi + 2 σi + 4
2
∴ 3σ
3 i + 14σ
14 i + 14 = 0
2
⎛ 7⎞
7
σi = − ± ⎜ ⎟ −
3 ⎝ 3⎠
14
3
1
= − 7± 7
3
( )
= −3.22 or − 1.45
Since σi lies bet

between
een p1 and p2,
σi = −1.45 × 106 sec−1
Asymptote Intercept, σa
From Rule 8
(−1− 2 − 4) − 0
σa = 2 33 × 106 sec−1
= −2.33
3
To find the loop gain, T0, at which the poles moving from p1 and p2
b
become complex,
l substitute
b tit t th
the b
breakaway
k i t s = σi = –1.45,
point, 1 45
into the magnitude condition and solve for T0.
p1 p 2 p3
T0 =1
s − p1 s − p 2 s − p3
−1 45 + 1 −1
1.45 45 + 2 −1
1.45 45 + 3
1.45
∴ T0 =
(1)(2)(4)
(0.45)(0.55)(2.55)
= = 0.08
8

The complex poles enter the RHP at approximately the points
where their asymptotes cross the jω axis. At these points
s = ± j(2.33)
j(2 33) tan(60 ) = ±4j
Substituting into the magnitude condition and solving for T0
s − p1 s − p2 s − p3
T0 =
p1 p2 p3
4j + 1 4j + 2 4j + 4
=
(1)(2)(4)
=
( 42 + 1 )( 4 2 + 22 )( 42 + 42 )= 17 ⋅ 20 ⋅ 32
8 8
(4.1)(4.5)(5.7)
= = 13.2
8
Plotting the Root Locus in Matlab
% root locus example

s = tf('s');
p1=-1; p2=-2; p3=-4;
a = 1 / [(1-s/p1)*(1-s/p2)*(1-/p3)]
rlocus(a)
Root Locus
10
2
Axis
Imaginary A
-2
-4
-6
-8
-10
-14
14 -12
12 -10
10 -8
8 -6
6 -4
4 -2
2 0 2 4
Real Axis

3 Poles and 1 Zero
jω
p2 p1 σ
Introducing a zero in T(s) can be used to stabilize a feedback amplifier.

The use of zeros in the feedback path is an important aspect of wideband
amplifier design.
Matlab Plot
% root locus example
s = tf('s');
z=-5; p1=-1; p2=-2; p3=-4;
a = (1-s/z) / [(1-s/p1)*(1-s/p2)*(1-s/p3)]
rlocus(a)
ocus(a)
Root Locus
15
10
5
Axis
Imaginary A
-5
-10
-15
-66 -5
5 -4
4 -3
3 -2
2 -1
1 0 1
Real Axis

Chapter 7
Wideband Amplifiers
B. Murmann
Stanford University
Reading Material: Section 9.5.3, 9.5.4
Overview
How to build amplifiers with large gain and bandwidth?
Options we’ll look at

– Cascade of first order amplifier stages
– Multi-stage
Multi stage amplifiers with global feedback
– Multi-stage amplifiers with local feedback

Cascade of N First-Order Stages
Consider a cascade of N identical stages, each with the single-

pole response
A0
A(jω) = GBW = A 0ωB
1+ jω ωB
If there is no interaction among the stages, then the overall

transfer function of the cascade is
N
⎛ A0 ⎞
AN (jω) = ⎜ ⎟
⎝ 1+ jω ωB ⎠
In this case
A 0N = AN0
Th –3dB
The 3dB b
bandwidth
d idth off th
the cascade
d iis the
th frequency,
f ωBN, att which
hi h
A 0N
AN (jωBN ) =
2
N
Thus, ⎡ ⎤ N
⎢ A0 ⎥ = A0
⎢ 1+ (ω ω B )2 ⎥ 2
⎣ BN ⎦
2
1+ (ωBN ωB ) = 21 N
ωBN = ωB ⋅ 21 N − 1 GBWN = A N0 ωB ⋅ 21 N − 1 < A N0 ωB

Bandwidth Shrinkage
0.8
1
N 0.6
2 −1
0.4
0.2
0 2 4 6 8 10
N
Ideal Lowpass Response
Suppose each stage in the cascade of N identical stages had an ideal

lowpass response; that is, a magnitude response with an abrupt band
edge transition between the passband and the stopband:
|A(jω)|
A0
⇒ GBWN = A N0 ωB
ωB ω
In the design of wideband amplifiers it is therefore often desirable to

h
have a muchh sharper
h b
band-edge
d d ttransition
iti than
th iis obtained
bt i d with
ith a
cascade of identical single-pole stages.

Maximally Flat Magnitude (MFM) Response
An approximation to the ideal lowpass response that is commonly used in

broadband amplifier design is the Maximally Flat Magnitude (MFM), or
Butterworth, response.
response
The MFM response provides a magnitude (gain) that is flat over as much
of the passband as possible and decreases monotonically with frequency
(i no peaking).
(i.e. ki ) It iis obtained
bt i d bby setting
tti as many dderivatives
i ti off th
the
magnitude with respect to frequency as possible to zero at ω = 0.
For an nth-order MFM response,
dk H(jω)
=0 for 1 ≤ k ≤ 2n − 1
dω k
ω =0
Th resulting
The lti magnitude
it d response iis
1
H(jω) =
( B)2n
1+ (ω
where n is the order of the response, B is the bandwidth of the ideal

p
lowpass response,
p , and the magnitude
g has been normalized to unity y
at ω = 0.
|H(jω)|
n=2
n=1
n=3
B
ω

There is no peaking in the MFM response, and as n increases the band
edge transition becomes sharper. In the limit as n t ∞, the MFM response
approaches the ideal lowpass response.
To determine the location of the poles of H(s), note that
2
H(jω) = H(jω) ⋅H(− jω)
= H(s) ⋅H(−s)
s= jω
Thus,, for an MFM response

p
1 j2n
H(s) ⋅H(−s) = =
1+ (s jB)2n j2n + (s B)2n
(−1)n
=
(−1)n + (s B)2n
The poles of H(s)×H(–s) are the 2n roots satisfying
2n
⎛ s⎞
⎜⎝ B ⎟⎠ = −(−1)n = (−1)n+1
Th
These roots
t lie
li equally
ll spaced
d on a circle
i l ini th
the s-plane
l centered
t d att
the origin with radius B.
The LHP roots are taken to be the poles of H(s), while those in the
RHP are regarded
d d as th
the poles
l off H(
H(–s).
)

MFM Pole Locations
n=1
jω
p1 = − B
σ
–B
n=2
pi = Be j3π 4 , Be j5π 4
jω
B
45º
n=3
pi = Be j2π 3 , Be jπ , Be j4π 3
jω
60º

MFM Transient Response
A potential disadvantage of the MFM response is that there is an

overshoot in the step response when n ≥ 2. This may be an important
consideration in applications such as pulse amplifiers.
For a step input at t=0
Vo(t) n=3
3
n=1
n=2
n = 2 Æ 4% overshoot
n = 3 Æ 8% overshoot
Comparison of 2-Pole Responses
Angle of –3dB 10-90%

Overshoot
Poles BW Rise Time
Coincident
0° 0.64B 0 3.4/B
poles
MFM
45° B 4% 2.2/B
(Butterworth)
Chebyshev
60° 1.3B 16% 1.6/B
(1-dB ripple) More in
EE315A
Bessel 30°
30 0 8B
0.8B 0 4%
0.4% 2 7/B
2.7/B

Wideband Amplification Using Multi-Stage Feedback
At most three gain stages can be effectively used within a single feedback
loop. Therefore, there are four basic configurations.
+
+
vo
–
+
vi ~
– RF
RE
v o RF
Series-Shunt Pair A V0 = ≈
v i RE
io
i o RF
ii AI0 = ≈
ii RE
RF
RE
Shunt-Series Pair

+
io
+
vi ~
–
RF
RE1 RE2
i o RF + RE1 + RE2
A0 = ≈
vi RE1 ⋅RE2
Series-Series Triple
+
vo
–
ii
RF
vo
A0 = ≈ RF
ii
Shunt-Shunt Triple

Analysis of Shunt-Series Pair
RC1 RC2 io
Q2
ZL
Q1
ii
RF
RE
Assume ZL ≈ 0 and RS ≈ ∞
Application Example: Optical Fiber Links (1)
K. Ohhata et al., “A Wide-Dynamic-Range, High-

Transimpedance Si Bipolar Preamplifier IC for 10-Gb/s
Optical Fiber Links,” JSSC 1/1999.

Circuit Implementation
Ohhata,
JSSC 1/1999
Small-signal equivalent circuit for evaluating the open-loop

response of the shunt-series pair:
io
RC1
Q2
Q1 iE2
ifb
ii ifb
RF
RE RF RE

Note that in BJT amplifiers with a series output stage, the feedback
network does not sample the output, io, directly, but rather the
emitter current of Q2, iE2. Thus, a(s) and f(s) are defined as follows:
iE2
a(s)
ii
ifb
f(s)
iE2
For these definitions
io ⎛ a(s) ⎞
A(s) = −α 2 ⎜
ii ⎝ 1+ a(s)f(s) ⎟⎠
where α2 is the common-base current gain of Q2
The feedback response

response, f(s)
f(s), for the shunt-series pair
(w/o compensation) is simply
ifb RE
f(s) = =−
iE2 RE + RF
To estimate the forward ppath response,

p a(s),
( ) begin
g with
the following small-signal equivalent circuit:
Cμ1 Cμ2 io
+ + +
ii R1 v1 RC1 v rπ2
Cπ1 2 vb Cπ2
– gm1v1 – – gm2vb
RE* iE2
R1 = (RF + RE ) || rπ1
RE* = RE || RF

First consider the transmission from the base to the emitter
of the second stage
iE2 = (v 2 − iE2RE* )(gm22 + Yπ 2 )
where
Yπ22 gπ22 + sC π22
Thus,
iE2 ⎡1+ ( m2 + Yπ 2 ) ⎤ = v 2 (g
1 RE* (g ( m2 + Yπ 2 )
⎣ ⎦
iE2 gm2 + Yπ 2
∴ =
v 2 1+ RE* (gm2 + Yπ 2 )
gm2
gm2 + Yπ 2 = gm2 + + sC π 2 ≅ gm2 + sC π 2
β0
⎛ C ⎞
= gm2 ⎜ 1+ s π 2 ⎟ = gm2 1+ sτ T2
⎝ gm2 ⎠
( )
Therefore,
Therefore
iE2 gm2 (1+ sτ T2 )

=
v 2 1+ gm2RE* + sRE* C π2
⎡ ⎤ ⎡ ⎤
⎢ ⎥ ⎢ ⎥
⎛ g ⎞⎢ 1+ sτ ⎥ ⎛ g ⎞⎢ 1+ sτ ⎥
m2 T2 m2 T2
=⎜ * ⎟ ⎢ ⎥= ⎜ ⎟⎢ ⎥
⎝ 1+ gm2RE ⎠ ⎢ ⎛ R C* ⎞ ⎥ ⎝ 1+ gm2RE ⎠ ⎢
* ⎛ g R ⎞⎥*
E π2 m2 E
⎢ 1+ s ⎜ 1+ g R* ⎟ ⎥ 1+ sτ T2 ⎜ * ⎟
⎢ ⎝ 1+ gm2RE ⎠ ⎦⎥
⎣ ⎝ m2 E ⎠ ⎦ ⎣

jω
–ωT2
⎛ 1+ g R* ⎞
m2 E
−ω T2 ⎜ * ⎟
⎝ gm2RE ⎠
Thus, the second stage is very broadband, and the pole-zero

pair associated with it can usually be neglected. In that case,
iE2 gm2
≅ gm2eq
v 2 1+ gm2RE*
Also,, io = − α 2iE2 ≅ − iE2
The main influence of the series feedback stage on a(s) is the

loading on Q1. We can model the loading using the following
approximation for the input impedance of the series feedback stage:
+
v2 Cμ2 rπ2eq Cπ2eq
–
where
rπ2eq = rπ2 (1+ gm2RE* ) ≅ rπ2gm2RE* = β02RE*

C π2 C π2 ⎛ 1 ⎞ τ T2
C π2eq = ≅ ⎜ ⎟=
1+ gm2RE* gm2 ⎝ RE* ⎠ RE*

Thus, the equivalent circuit for determining the open-loop response
v2(s)/ii(s) is simply:
Cμ1
+ +
ii R1 v1 Cπ1 gm1v1 RL1 CL1 v2
– –
where
R1 = rπ1 || (RF + RE )
RL1 = RC1 || rπ2eq ≅ RC1 || β02RE*

τ T2
CL1 = Ccs1 + Cμ 2 + C π 2eq ≅ Ccs1 + Cμ 2 +
RE*
Since
iE2 ⎛ iE2 ⎞ ⎛ v 2 ⎞
a(s) =⎜ ⎟⎜ ⎟
ii ⎝ v 2 ⎠ ⎝ ii ⎠
iE2 gm2 1
and ≅ gm2eq
2
= ≅ *
v2 *
1+ gm2RE RE
we find
⎡ ⎛ R ⎞ ⎤ ⎡ 1− s z1 ⎤
a(s) = − ⎢gm1R1 ⎜ L1 ⎥⎢
( ⎥
)
* ⎟ 2
⎢⎣ ⎝ RE ⎠ ⎥⎦ ⎢⎣ 1+ b1s + b 2s ⎥⎦
Where (see Chapter 4)
b1 = R1(Cπ1 + Cμ1) + RL1(CL1 + Cμ1) + gm1R1RL1Cμ1
b 2 = R1RL1(C π1CL1 + C π1Cμ1 + CL1Cμ1)

gm1
z1 = +
C μ1

If a dominant pole condition exists, with |p1| << |p2|, then
1
p1 ≅ −
b1
1
=−
R1C π1 + RL1CL1 + gm1R1RL1Cμ1
and
1 R1C π1 + RL1CL1 + gm1R1RL1Cμ1

p2 = ≅−
b 2p1 R1C π1RL1CL1
⎛ 1 1 gm1Cμ1 ⎞
= −⎜ + + ⎟
⎝ R1C π1 RL1CL1 C π1CL1 ⎠
In the s-plane
jω
p2 p1 σ
Unfortunately, non-dominant poles (and RHP zeros) of T(s)

tend to push the poles of A(s) toward the RHP

Feedback (Phantom) Zeros
The flat bandwidth and loop gain achievable in a shunt-series pair

can be increased significantly by introducing a feedback (phantom)
zero. This
Thi is
i accomplished
li h d by
b iincluding
l di a capacitor,
it CF, in
i shunt
h t with
ith
RF; the feedback network then becomes:
CF
ifb
RF
RE iE2
Neglecting the loading of CF at the input and the emitter of Q2 in the

forward path (since it appears in shunt with RE), a(s) remains the
same as w/o CF. However,
⎛ RE ⎞ ⎛ 1 − s zF ⎞
f(s) = − ⎜ ⎟⎜ ⎟
⎝ RE + RF ⎠ ⎝ 1 − s pF ⎠
where
1
zF = −
RFCF
1 R + RE
pF = − =− F
(RF || RE )CF RFRECF
Since A 0 ≅ (RF + RE ) RE
pF = A0 zF

Since CF is chosen so that |zF| is on the order of the bandwidth of
A(s), pF can be ignored unless the low-frequency closed loop gain,
A0, is small. Thus,
⎛ RE ⎞
( ) ≅ −⎜
f(s) ⎟ ((1− sRFCF )
⎝ RE + RF ⎠
CF is chosen so as to obtain the desired closed-loop pole

positions. For example,
p p , for an MFM response:
p
jω
σi
zF p2 σ
45º p1
If zF is reasonably remote from p1 and p2, then
p1 + p 2
σi =
2
The root locus is a circle of radius |zF – σi| centered at zF. For each
branch of the locus there are two intersections with the two lines at
45° to the negative real axis that correspond to an MFM response
45 response.
If |zF| >> |σi|, then for an MFM response
B = 2 zF
and the closed-loop

pppole p
positions,, s1 and s2, are
B
s1,s2 ≅ zF (−1± j) = (−1± j)
2

The loop gain, T0, needed to place the closed-loop poles at these
positions is
s1 − p1 s2 − p 2 B2
T0 = =
p1 p 2 p1 p 2
2
2 zF 2R1C π1RL1CL1
= =
p1 p 2 (RFCF )2
Broadband Amplifier Design with Local Feedback
Rein & Moller, JSSC 8/1996
In a cascade of amplifier stages, the interaction (loading) between adjacent

stages can be reduced by alternating local series and shunt feedback circuits.

Advantages & Disadvantages of Local Feedback Cascades
Advantages
• No
N iinstability
bili
• Lower gain sensitivity to component and device parameter
variations than amplifiers without local feedback
Disadvantages
• Hi
Higher
h gaini sensitivity
iti it (less
(l lloop gain)
i ) th
than multi-stage
lti t
feedback amplifiers (i.e. multi-stage amplifiers with global
feedback)
• Bandwidth obtainable is typically slightly less than that
possible in multi-stage feedback amplifiers
Application Example (1)
Poulton, ISSCC 2003

Poulton, ISSCC 2003
Poulton, ISSCC 2003
BW ~ 6 GHz

Cherry-Hooper Amplifier
RF
RE
Shunt F/B
Series F/B Stage
Stage
E. Cherry and D. Hooper, Proc. IEE, Feb. 1963
Analysis
vo ⎛ 1 ⎞ RF
A(0) = ≅ ⎜− ⎟ ( −RF ) =
v in ⎝ RE ⎠ RE
Thus, the low-frequency gain is approximately equal to the ratio of the

two feedback resistors,, and is therefore insensitive to component
p and
device parameter values
While the series feedback stage usually has a large bandwidth, there is
p and output
considerable interaction between the input p nodes of the
shunt feedback stage. However this interaction can be controlled and
can be used to position the poles to achieve a particular response, such
as MFM.
To see how the pole positions in a local feedback cascade can be
controlled, we first consider the local feedback stages individually

Series Feedback Stage
Small-signal equivalent circuit:
RS Cμ io
+
vi ~ v1 rπ Cπ gmv1 ZL
–
+
vE RE
–
Include transistor rb in RS
Neglect rμ, ro, re, and rc
Assume that ZL ≈ 0; then there is no Milller effect and Cμ is just a

(small) capacitance to ground which often has negligible impact.
Define
1
Yπ + sC π
rπ
Then
v i − (v1 + vE )
= v1Yπ
RS
vE
v1Yπ + gmv1 =
RE
Substituting for vE in the first of these two equations
v i − v1 ⎡⎣1+ (gm + Yπ ) RE ⎤⎦ = v1YπRS
v1 1
∴ =
v i 1+ (gm + Yπ ) RE + YπRS

Since io = –gmv1
io gm
=−
vi 1+ gmRE + (RS + RE )Yπ
⎡ ⎤
⎢ ⎥
⎛ gm ⎞ ⎢ 1 ⎥
= −⎜ ⎟ ⎢ ⎛ R +R ⎞ ⎛ ⎥
⎝ 1+ g R
m E⎠ 1 ⎞
⎢ 1+ ⎜ S E
⎟⎜ + sC π⎟
⎥
⎢⎣ ⎝ 1+ gmRE ⎠ ⎝ rπ ⎠ ⎥⎦
⎡ ⎤
⎢ ⎥
⎛ gm ⎞ ⎢ 1 ⎥
= −⎜ ⎟ ⎢
⎝ 1+ gmRE ⎠ ⎛ R + RE ⎞ ⎛ 1 ⎞ ⎛ RS + RE ⎞ ⎥
⎢ 1+
1 ⎜ S ⎟⎜ ⎟ + sC
C π⎜ ⎟⎥
⎢⎣ ⎝ rπ ⎠ ⎝ 1+ gmRE ⎠ ⎝ 1+ gmRE ⎠ ⎦⎥
Usually,
Usually
⎛ RS + RE ⎞ ⎛ 1 ⎞ gm (RS + RE ) ⎛ 1 ⎞
⎜ r ⎟ ⎜ 1+ g R ⎟ = β0 ⎜ ⎟ << 1
⎝ π ⎠⎝ m E⎠ ⎝ 1+ gmRE ⎠
Then
io ⎛ 1 ⎞
≅ −gmeq ⎜ ⎟
vi ⎝ 1− s p1 ⎠
where
gm
gmeq =
1+ gmRE
⎛ 1+ gmRE ⎞ ⎛ 1 ⎞
p1 = − ⎜ ⎟⎜ ⎟
⎝ C π ⎠ ⎝ RE + RS ⎠

If gmRE >> 1
1
gmeq ≅
RE
and
gm ⎛ RE ⎞ ⎛ Cπ + Cμ ⎞⎛ RE ⎞ ⎛ RE ⎞
p1 ≅ − ⎜ ⎟ = − ωT ⎜ ⎟⎜ ⎟ ≅ − ωT ⎜ ⎟
Cπ ⎝ RE + RS ⎠ ⎝ Cπ ⎠⎝ RE + RS ⎠ ⎝ RE + RS ⎠
Note that this result corresponds to the dominant time constant

found via ZVTC analysis in handout 7.
Thus, for RE >> RS, p1 → – ωT. In some cases, the bandwidth

may then be actually limited by Cμ (which was neglected in this
analysis).
Emitter Peaking
The bandwidth of the series feedback stage can be increased by

introducing an “emitter peaking” capacitor in shunt with RE.
io
RS
+ Q1
vi ~ N a large
Not l b
bypass
– capacitor
RE CE
To analyze this circuit, substitute ZE for RE in the preceding

analysis where
analysis,
1 RE
ZE = =
YE 1+ sRECE

Cπ
Then, defining τE RECE and assuming τ T ≅
gm
io gm
=−
vi 1
1+ gmZE + (RS + ZE )( + sC π )
rπ
gm
=−
RS ⎛ RE ⎞ ⎛ 1 ⎞
1+ + sC πRS + ⎜ ⎟ ⎜ gm + + sC π ⎟
rπ ⎝ 1+ sτE ⎠ ⎝ rπ ⎠
gm
−
R ⎛ g R ⎞⎛ C ⎞
1+ S + sC πRS + ⎜ m E ⎟ ⎜ 1+ s π ⎟
rπ ⎝ 1+ sτE ⎠ ⎝ gm ⎠
1
since gm >>
rπ
io gm
∴ ≅−
vi RS ⎛ 1+ sτ T ⎞
1+ + sC πRS + gmRE ⎜ ⎟
rπ ⎝ 1+ sτE ⎠
If CE is chosen so that
τE = τ T
and it is true that

RS gmRS
gmRE >> =
rπ β0
Then
⎡ ⎤
⎢ ⎥
io ⎛ gm ⎞ ⎢ 1 ⎥
≅ −⎜ ⎟⎢
vi ⎝ 1+ g R ⎛ ⎞ ⎥
m E⎠ RS
⎢ 1+ sC π ⎜ ⎟⎥
⎢⎣ ⎝ 1+ gmRE ⎠ ⎥⎦

Th result
The lt is
i a single-pole
i l l response with
ith
1+ gmRE ⎛R ⎞
p1 = − ≅ −ω T ⎜ E ⎟
RSC π ⎝ RS ⎠
In this case, if RE > RS, then |p1| > ωT (!)
Note that τE > τT results in a pole-zero separation that can cause

peaking in the frequency response
jjω
p1 z1 σ
p2
|io/vi|
|z1| |p1| |p2| ω

Shunt Feedback Stage
Small-signal equivalent circuit
CF
RF
+ +
ii v1 rπ Cπ gmv1 RL CL vo
– –
Include transistor Cμ in CF
Neglect RS or include it in rπ
Neglect rb, rc, re, and rμ
Include ro and Ccs in RL and CL
D fi
Define
τF RFCF
τL RLCL
and
1 1 1
YF = + sCF = (1+ sCFRF ) = (1+ sτF )
RF RF RF
1 1
YL = + sCL = ((1+ sτL )
RL RL
1
Yπ = + sC π
rπ

From the equivalent circuit:
ii + (v o − v1)YF = v1Yπ (1)
v o YL + gmv1 + (v o − v1)YF = 0 (2)
Then from (2)

⎛ Y + YF ⎞
v1 = −v o ⎜ L ⎟
⎝ gm − YF ⎠
Substituting in (1)
⎡ ⎛ Y + YF ⎞ ⎤
ii + v o ⎢ YF + ⎜ L ⎟ (Yπ + YF ) ⎥ = 0
⎣⎢ ⎝ gm − YF ⎠ ⎦⎥
vo gm − YF
∴ =−
ii (gm − YF )YF + (YL + YF )(Yπ + YF )
Assuming that gm >> 1/RF = GF
gm − YF = gm − (GF + sCF ) ≅ gm − sCF
Then
vo gm − sCF
≅−
ii ( L + CF ) ⎤⎦ ⎡⎣(gπ + GF ) + s(C
)(GF + sCF ) + ⎡⎣((GL + GF ) + s(C
(gm − sCF )( ( π + CF ) ⎤⎦
Thus
vo gm − sCCF
≅−
ii a0 + a1s + a 2s2
where
a0 = gmGF + (GL + GF )(gπ + GF )
a1 = (gm − GF )CF + (GL + GF )(C π + CF ) + (gπ + GF )(CL + CF )
a 2 = CLC π + CLCF + C π CF

Further assuming
g that gm >> GL, RF >> rπ, Cπ >> CF, and noting
g
that gm >> gπ
a0 ≅ gm RF
a1 ≅ gmCF + (GL + GF )C π + gπ (CL + CF )
a 2 ≅ C π (CL + CF )
Then
vo R (1− s z1)
≅− F
ii 1+ b1s + b 2s2
where
⎛ R + RL ⎞ R
b1 = a1 a0 ≅ RFCF + ⎜ F ⎟ τ T + F (CL + CF )
⎝ RL ⎠ β0
b 2 = a 2 a1 ≅ RF (CL + CF )τ T
z1 = + gm CF
Often b1 ≅ RFCF
z1 is a feedforward zero that is located in the RHP.

RHP
Since it was assumed that Cπ >> CF
gm
z1 >> ≅ ωT
Cπ
In these circumstances the feedforward zero can usually be

neglected, and the shunt feedback stage has an approximate
2-pole response.
vo RF
=−
ii (1 − s p1 )(1 − s p2 )
The poles p1 and p2 may be complex

complex.
CF can be used to alter the positions of the poles.

For example, CF can be chosen to provide a 2-pole MFM
response:
jω
p1
45º
σ
–B
p2
1 1 1
b2 = = = 2
p1p 2 p 2
B
1
Thus,
1 1
ω−3dB = =
b2 RF (CF + CL )τT
If CF << CL
1
ω−3dB ≅
RFCL τT
Further insight can be gained from this result by considering the input
capacitance of the overall Cherry-Hooper amplifier, which is
approximately
i t l Cπ/(g/( mRE). th t CL ≅ k·C
) If we assume that k Cπ/(g
/( mRE) = kk·τT/RE
⎛ 1 RE ⎞ 1 ⎛ 1 RE ⎞ ωT
ω−3dB ≅ ⎜ =⎜ ⎟⎟ ωT =
⎜ k R ⎟⎟ τ ⎜ kR k ⋅ A(0)
⎝ F ⎠ T ⎝ F ⎠

Since the overall low-frequency gain, A02, of the cascade is
RF
A 02 =
RE
the p
per-stage
g ggain-bandwidth p
product, GB2, is
GB2 = (A 02 )1/2 ⋅ ω−3dB

⎛ RF ⎞ ⎛ 1 RE ⎞ ωT
=⎜ ⋅ ⎟⎟ ωT =
⎜ R ⎟⎟ ⎜⎜ k R k
⎝ E ⎠ ⎝ F ⎠
Thus, the amplifier approaches the ideal gain-bandwidth product

limit for a cascade of identical stages (k=1); there is no
bandwidth shrinkage.
The value of CF that provides a 2-pole MFM response can be found

as follows. Realize that
⎛ 1 1⎞ p + p2
b1 = − ⎜ + ⎟ = − 1
⎝ p1 p 2 ⎠ p1p 2
p1 and p2 are complex conjugates at 45° for an MFM response
p1 = σ1 + jω1
p 2 = σ1 − jω1
where
B
−σ1 = ω1 =
2

Thus
Th
b1 ≅ RFCF =
2 B( 2 )= 2
2 B
B
From the earlier analysis, for CF << CL
1 1
B= ≅
b2 RFCL τT
Therefore
1 ⎛ 2⎞ 2RFCL τT 2CL
CF = ⎜ ⎟= = ⋅ τT
RF ⎝ B ⎠ RF RF

Chapter 8
Noise Analysis
y
B. Murmann
Stanford University
Reading Material: Sections 11.1, 11.2, 11.3, 11.4, 11.5, 11.6, 11.7, 11.9
Types of Noise
"Man made noise” or interference noise

– Signal coupling
– Substrate coupling
– Finite power supply rejection
– Solutions
• Fully differential circuits
• Layout techniques
"Electronic
Electronic noise
noise" or "device
device noise"
noise (focus of this discussion)
– Fundamental
• E.g. "thermal noise" caused by random motion of carriers
– Technology related
• "Flicker noise" caused by material defects and "roughness"

Signal-to-Noise
g Ratio
2
Psignal Vsignal
SNR = ∝ 2
Pnoise
i Vnoise
Th
The "fidelity"
"fid lit " off electronic
l t i systems
t is
i often
ft determined
d t i d by
b their
th i SNR
– Examples
• Audio systems
• Imagers,
Imagers cameras
• Wireless and wireline transceivers
Electronic noise directly trades with power dissipation and speed
Noise has become increasingly important in modern technologies with
reduced supply voltages
– SNR ~ Vsignal2/Vnoise2 ~ (αVDD)2/Vnoise2
Topics
− How to model noise of circuit components
− How to calculate/simulate the noise performance of a complete circuit
• In which circuits and applications does thermal noise matter?

Ideal Resistor
i(t)
()
1V/1kΩ
Constant current, independent of time

Non-physical
– In a physical resistor, carriers "randomly" collide with lattice atoms,
giving rise to small current variations over time
Physical Resistor
i(t)
1V/1kΩ
"Thermal Noise" or "Johnson Noise"

– J.B. Johnson,, "Thermal Agitation
g of Electricity
y in Conductors,"
, Phys.
y
Rev., pp. 97-109, July 1928
Can model random current component using a noise current source in(t)

Properties of Thermal Noise
Present in any conductor

Independent
p of DC current flow
Instantaneous noise value is unpredictable since it is a result of a large
number of random, superimposed collisions with relaxation time
constants of τ ≅ 0.17ps p
– Consequences:
• Gaussian amplitude distribution
• Knowing g in((t)) does not help
pp ), unless Δt is on the
predict in((t+Δt),
order of 0.17ps (cannot sample signals this fast)
• The power generated by thermal noise is spread up to very high
frequencies (1/τ ≅ 6,000Grad/s)
The only predictable property of thermal noise is its average power!
Average Power
For
F a deterministic
d t i i ti currentt signal
i l with
ith period
i dTT, th
the average power iis
T /2
1
Pav = ∫ i2 ( t ) ⋅ R ⋅ dt
T −T /2
This definition can be extended to random signals

Assuming a real, stationary and ergodic random process, we can write
T /2
1
∫ in ( t ) ⋅ R ⋅ dt
2
Pn = lim
→ T
T →∞
− T /2
For notational convenience, we typically drop R in the above expression

and work with "mean
mean square"
square currents (or voltages)
T /2
1
in2 = lim ∫ in ( t ) ⋅ dt
2
T →∞ T
− T /2

Thermal Noise Spectrum
Th
The so-called
ll d power spectral
t ld density
it (PSD) shows
h h
how much
h power a
signal caries at a particular frequency
In the case of thermal noise, the power is spread uniformly up to very
hi h ffrequencies
high i ((about
b t 10% d drop att 2
2,000GHz)
000GH )
PSD(f)
n0
The total average noise power Pn in a particular frequency band is found

by integrating the PSD
f2
Pn = ∫ PSD ( f ) ⋅ df
f1
Thermal Noise Power
Nyquist showed that the noise PSD of a resistor is
PSD ( f ) = n0 = 4 ⋅ kT
k is the Boltzmann constant and T is the absolute temperature

4kT = 1.66·10-20 Joules at room temperature
The total average noise power of a resistor in a certain frequency band
is therefore
f2
Pn = ∫ 4kT ⋅ df = 4kT ⋅ ( f2 − f1 ) = 4kT ⋅ Δf
f1

Equivalent Noise Generators
We can model the noise using either an equivalent voltage or current

generator
Pn 1
v n2 = Pn ⋅ R = 4kT ⋅ R ⋅ Δf in2 = = 4kT ⋅ ⋅ Δf
R R
For R = 1kΩ: For R = 1kΩ:
v n2 V2 in2 A2
= 16 ⋅ 10−18 = 16 ⋅ 10−24
Δf Hz Δf Hz
v n2 in2
= 4nV / Hz = 4pA / Hz
Δf Δf
Δf = 1MHz ⇒ v n2 = 4μV Δf = 1MHz ⇒ in2 = 4nA
Two Resistors in Series
( )
2
v n2 = v n1 − v n2 2
= v n1 2
+ v n2 − 2 ⋅ v n1 ⋅ v n2
Since vn1(t) and vn2(t) are statistically independent, we have
v n2 = v n1
2 2
+ vn2 = 4 ⋅ kT ⋅ (R1 + R2 ) ⋅ Δf
Al
Always remember
b to t add
dd iindependent
d d t noise
i sources using
i mean
squared quantities
– Never add RMS values!

MOSFET Thermal Noise (1)
The noise of a MOSFET operating in the triode region is approximately

equal to that of a resistor
In the saturation region,
g , the thermal noise of a MOSFET can be
modeled using a drain current source with spectral density
i2d = 4kT ⋅ γ ⋅ gm ⋅ Δf
For an idealized long channel MOSFET, it can be shown that γ=2/3

For the past 10-15 years, researchers have been debating the value of γ
in short channels
Preliminary (wrong) results had suggested that in short channels γ can
be as high as 5 due to “hot carrier” effects
MOSFET Thermal Noise (2)
[Scholten]
At moderate gate bias in strong inversion, short-channel MOSFETS

have γ ≅ 1
– A. J. Scholten et al., "Noise modeling for RF CMOS circuit simulation," IEEE
Trans. Electron Devices, pp. 618-632, Mar. 2003.
– R. P. Jindal, "Compact Noise Models for MOSFETs," IEEE Trans. Electron
Devices,
e ces, pppp. 2051-2061,
05 06 , Sep Sep. 2006.
006

Thermal Noise in EE214 MOSFET Devices
γ ≅ 0.85
γ ≅ 0.7
Parameter γ depends on biasing conditions, but is roughly constant within

a reasonable range of gm/ID used for analog design
The EE214 HSpice models become inaccurate for sub-threshold operation
Spice Simulation (1)
* EE214 MOS device noise simulation
vd
d dd 0 0.9
0 9
vm dd d 0
vg g 0 dc 0.7 ac 1
mn1 d g 0 0 nmos214 L=0.18u W=10u
h1 c 0 ccvs vm 1
.op
.ac dec 100 10k 1gig
.noise v(c) vg
.options post brief

.inc './ee214_hspice.sp'
.end

Spice Simulation (2)
(gm=3.14mS)
1/f Noise
Also called "flicker noise" or "pink noise"

– Caused by traps near Si/SiO2 interface that randomly capture and
release carriers
– Occurs in virtuallyy anyy device,, but is most pronounced
p in MOSFETS
Several (empirical) expressions exist to model flicker noise
– The following expression is used in the EE214 HSpice models
2
2 K f gm Δf
i1/ f =
Cox W ⋅ L f
For other models, see HSpice manual or

– D. Xie et al., "SPICE Models for Flicker Noise in n-MOSFETs from
Subthreshold to Strong Inversion," IEEE Trans. CAD, Nov. 2000
Kf is strongly dependent on technology; numbers for EE214:
– Kf,NMOS = 0.5·10-25 V2F
– Kf,PMOS = 0.25·10-25 V2F

1/f Noise Corner Frequency
B
By definition,
d fi iti the
th frequency
f att which
hi h the
th flicker
fli k noise
i density
d it equals
l th
the
thermal noise density
2
K f gm Δf
= 4kTγ ⋅ gm ⋅ Δf
Cox W ⋅ L fco
Kf 1 gm Kf 1 1 ⎛ gm ⎞ ⎛ ID ⎞
⇒ fco = = ⎜ ⎟
4kTγ Cox W ⋅ L 4kTγ Cox L ⎝ ID ⎠ ⎝⎜ W ⎠⎟
For a given gm/ID (e.g. based on linearity considerations), the only way to
achieve lower fco is to use longer channel devices
− In the above expression, both 1/L and ID/W are reduced for
increasing L
Example
– EE214 NMOS, L = 0.18μm, gm/ID = 12 S/A , ⇒ID/W = 20 A/m
⇒fco = 560 kHz
In
I newer technologies,
t h l i fco can be
b on th
the order
d off 10 MH
MHz
1/f Noise Contribution (1)
JJustt as with
ith white
hit noise,
i th
the ttotal
t l 1/f noise
i contribution
t ib ti isi found
f d by
b
integrating its power spectral density
f2 2
K f gm Δf
∫ Cox W ⋅ L f
2
i1/ f,tot =
f
1
2 2
K f gm ⎛ f ⎞ K gm ⎛f ⎞
= ln ⎜ 2 ⎟ = f 2.3log ⎜ 2 ⎟
Cox W ⋅ L ⎝ f1 ⎠ Cox W ⋅ L ⎝ f1 ⎠
The integrated flicker noise depends on the number of frequency

decades
– The frequency range from 1Hz …10Hz contains the same amount
of flicker noise as 1GHz …10GHz
– Note that this is very different from thermal noise
So, does flicker noise matter?
– Let’s look at the total noise integral (flicker and thermal noise)

1/f Noise Contribution (2)
In the example shown

on the left, the noise
spectr m is integrated
spectrum
from 100Hz to 10GHz
The contribution of
the flicker noise is
relatively small, even
though its PSD
dominates at low
frequencies
For circuits with very
large bandwidth,
flicker noise is often
insignificant
Lower Integration Limit
Does the flicker noise PSD go to infinity for f → 0?

– See e.g. E. Milotti, "1/f noise: a pedagogical review," available at
http://arxiv org/abs/physics/0204033
http://arxiv.org/abs/physics/0204033
Even if the PSD goes to infinity, do we care?
– Say we are sensing a signal for a very long time (down to a very low
frequency), e.g. 1 year ≅ 32 Msec, 1/year ≅ 0.03 μHz
– Number of frequency decades in 1/year to 100Hz ≅ 10
– For the example on the previous slide, this means that the integration
band changes from 8 to 8+10=18 decades
– sqrt(18/8) = 1.5 → Only 50% more flicker noise!

MOS Model with Noise Generator
Noiseless!
(merely a modeling
resistor that lets us
account for finite
i2d 2
K f gm 1 dID/dVDS)
= 4kT ⋅ γ ⋅ gm ⋅ +
Δf Cox W ⋅ L f
Other MOSFET Noise Sources
G
Gate
t noise
i
– "Shot noise" from gate leakage current
– Noise due to finite resistance of the gate material
– Noise
N i due
d tto randomly
d l changing
h i potential/capacitance
t ti l/ it b
between
t th
the
channel and bulk
• Relevant only at very high frequencies
• See EE314
Bulk noise
Source barrier noise in very short channels
– Shot noise from carriers injected across source barrier
– R. Navid, C. Jungemann, T. H. Lee and R. W. Dutton, “High-
frequency noise in nanoscale metal oxide semiconductor field effect
transistors,” Journal of Applied Physics, Vol. 101(12) , pp. 101-108,
June 15, 2007

Shot Noise in a PN Junction
Shot noise is generally associated with the flow of a DC current

In a forward biased diode, shot noise occurs due to randomness in the
carrier transitions across the PN jjunction ((energy
gy barrier))
The power spectral density of this noise is white up to very high
frequencies
The noise can be included in the small
small-signal
signal model as shown below
i2 = 2qID ⋅ Δf
Constant
(“white”)
PSD
Shot Noise in a Bipolar Transistor
In a bipolar transistor, the flow of DC current into the base and collector
causes shot noise
The noise can be modeled via equivalent
q current g
generators
ic2 = 2qIC Δf = 2kTgm Δf

ic2
g 1
ib2 = 2qIB Δf = 2kT m Δf = 2kT Δf ib2
β rπ
The base and collector noise currents are statistically

y independent
p as
they arise from separate physical mechanisms
– This will be important in the context of circuit noise calculations

BJT Small Signal Model with Noise Generators
Thermal noise due to physical rb:
Collector shot noise: Typically negligible
Base noise components:
Noise in Circuits (1)
Most circuits have more than one relevant noise source

In order to quantify the net effect of all noise sources, we must refer the
noise sources to a single "interesting" port of the circuit
– Usually the output or input
In the following discussion, we will first consider only circuits with a
perfect voltage drive, i.e. no source resistance RS
– Inclusion of finite RS will be discussed later

Noise in Circuits (2)
Output referred noise Input referred noise

– Refer noise to output via – Represent total noise via a
individual noise transfer fictitious input source that
functions captures all circuit-internal
– Physical concept, exactly noise sources
what one would measure in – Useful for direct comparisons
the lab with input signal, or “general
purpose” components in which
the output noise depends on
how the component is used
Circuit Example
For simplicity, let’s neglect

– Source impedance
– All capacitances
it
– Burst and flicker noise
– ro, rb, and rμ

Output Referred Noise PSD
2 ⎛ 1 ⎞
v out = ⎜ 4kT Δf + 2qIC Δf ⎟ ⋅ R2
⎝ R ⎠
(
= 2kTΔf 2R + gmR2 )
⎛ 2 ⎞
= 2kTgm Δf ⋅ R2 ⎜ + 1⎟
⎝ gmR ⎠
Shot noise due to base current is absorbed by the input source and does
not contribute to noise at the output
For large gain (gmR), the collector shot noise dominates
Input Referred Noise PSD
From the previous calculation, we know that

2 ⎛ 2 ⎞
v out = 2kTgm Δf ⋅ R2 ⎜ + 1⎟
⎝ gmR ⎠
Since
v out = A v vin
2
v out = A 2v v in
2
where A v = gmR
We can write
⎛ 2 ⎞
2kTgm Δf ⋅ R2 ⎜ + 1⎟
2
v in = ⎝ gmR ⎠ = 2kT 1 Δf ⎛ 2 + 1⎞
⎜ ⎟
( gmR )2 gm ⎝ gmR ⎠
Larger gm translates into lower input

referred voltage noise

Spice Simulation
*** EE214 BJT noise example

*** biasing
ib vcc vb 100u gm=3.67mS, R=10k, Av=36.7
q1 vb vb 0 npn214
c1 vb 0 1
*** main circuit

v1 vcc 0 2.5
vi vi vb ac 1
rl vcc vo 10k
q2 vo vi 0 npn214
.op
.ac dec 100 100 10e9
.noise v(vo) vi
.options post brief
.inc ‘ee214_hspice.sp'
.end
d
Output Referred Noise PSD with Load Capacitance
2
2 ⎛ 1 ⎞ 1
v out = ⎜ 4kT Δf + 2qIC Δf ⎟ ⋅ R ||
⎝ R ⎠ jωC
2
⎛ 1 ⎞ 1
= ⎜ 4kT Δf + 2qIC Δf ⎟ ⋅ R2
⎝ R ⎠ 1 + jωRC
2
⎛ 2 ⎞ 1
= 2kTgm Δf ⋅ R2 ⎜ + 1⎟ ⋅
⎝ gmR ⎠ 1 + jωRC
Same calculation as before

before, except that now the noise current drops into
parallel combination of R and C
Output PSD is shaped by squared magnitude of first order response

Input Referred Noise PSD with Load Capacitance
S
Same calculation
l l ti as b
before,
f exceptt th
thatt th
the voltage
lt gain
i iis now
frequency dependent
2
2
v out ( ω) 2 1
2
vin ( ω) = 2
where A v ( jω ) = A v (0)
A v ( jω ) 1 + jωRC
2
⎛ 2 ⎞ 1
2kTgm Δf ⋅ R2 ⎜ + 1⎟ ⋅
g
⎝ m R ⎠ 1 + j ω RC
= 2
1
A 2v ( 0 )
1 + jωRC
Input referred noise is frequency independent, because the output noise

and gain have the same frequency roll
roll-off
off
2 1 ⎛ 2 ⎞
∴ vin = 2kT Δf ⎜ + 1⎟
gm ⎝ gmR ⎠
Spice Simulation
*** EE214 BJT noise

i example
l
*** biasing
ib vcc vb 100u
q1 vb vb 0 npn214
gm=3.67mS, R=10k, Av=36.7, C=10pF
c1 vb 0 1
*** main circuit

v1 vcc 0 2.5
2 5
vi vi vb ac 1
rl vcc vo 10k
Cl vo 0 10p
q2 vo vi 0 npn214
.op
.ac dec 100 100 10e9
.noise v(vo) vi
.options post brief
.inc 'ee214_hspice.sp'
.end

Signal-to-Noise Ratio
Assuming a sinusoidal signal, we can compute the SNR at the output of

the circuit using
1 2
Psignal v̂ out
v
SNR = =f 2
Pnoise 2 2
v
∫ Δoutf ⋅ df
f 1
Over which bandwidth should we integrate the noise?

Two interesting cases
– The output is measured or observed by a system with finite
bandwidth (e.g. human ear, or another circuit with finite bandwidth)
q
• Use frequency y range
g of that system
y as integration
g limits
• Applies on a case by case basis
– Total integrated noise
g
• Integrate noise from zero to “infinite” frequency
q y
A Closer Look at The Circuit’s Noise Integral
The noise integral converges

for upper integration limits that
lie beyond the circuit’s pole
frequency
The total integrated noise (from
“0” to “infinity”) is a reasonable
metric
t i tto use
– For convenience in
comparing circuits without
making bandwidth
assumptions
– In a circuit where the output
is observed without any
significant band limiting
• E.g. in a sampling circuit
• See EE315A,B

Total Integrated Noise Calculation
Let us first consider the noise from the resistor
∞ 2
1
2
v out,tot = ∫ 4kTR ⋅ df
0
1 + j2 πf ⋅ RC
∞
df du −1
= 4kTR ∫ 2
; ∫ 1 + u2 = ttan u
0 1+ ( 2πfRC )
1
= 4kTR ⋅
4RC
kT
=
C
Interesting result
– The total integrated noise at the output depends only on C (even
g R is g
though generating
g the noise))
Effect of Varying R
Increasing R increases
the noise power spectral
density, but also
decreases the
bandwidth
– R drops out in the
end result
For C=1pFp ((examplep to
the right), the total
integrated noise is
approximately 64μVrms

Alternative Derivation
The equipartition theorem of statistical mechanics says that each degree

of freedom (or energy state) of a system in thermal equilibrium holds an
average energy of kT/2
– See e.g. EE248 for a derivation
In our circuit, the quadratic degree of freedom is the energy stored on
th capacitor
the it
1 1
Cv out 2 = kT
2 2
kT
v out 2 =
C
Equivalent Noise Bandwidth
2 kT ⎫
v out,tot = ⎪
C
⎪
2 ⎪ π
v out,tot 4kTR ⋅ ΔfENBW ⎬ ΔfENBW = f−3dB
⎪ 2
1 ⎪
f−3dB = ⎪
2πRC ⎭
The equivalent noise bandwidth is generally defined as the bandwidth of

a brick-wall filter which results in the same total noise power as the filter
in question
For a simple RC filter, the equivalent noise bandwidth is approximately
1.57 times its 3-dB corner frequency

Total Integrated Noise Calculation for the Complete Circuit
∞ 2
∫( )
2 1
v out,tot = 4kTR + 2kTgmR2 ⋅ df
0
1 + jj2πf ⋅ RC
Was 4kTR in previous analysis
2 kT 4kTR + 2kTgmR2
v out,tot = ⋅
C 4kTR
kT ⎛ 1 ⎞
= ⎜ 1 + gmR ⎟
C⎝ 2 ⎠
Taking the BJT’s collector shot noise into account, the total integrated
noise becomes a multiple of kT/C
Example SNR Calculation
Assumptions
– Output carries a sinusoid with 1V peak amplitude
– We observe the output without significant band limiting and thus use
th total
the t t l integrated
i t t d noise
i ini the
th SNR expression
i
1 2
v̂ out
Psignal 2 0.5V 2 0.5V 2
SNR = = = = 2
8 59 ⋅ 106
= 8.59
kT ⎛ ⎞ ⎛ ⎞
1 + 3.67mS ⋅ 10kΩ ⎟ ( 763μV )
Pnoise 1 kT 1
1+ g R
C ⎜⎝ 2 m ⎟⎠ 10pF ⎜⎝ 2 ⎠
(
SNR [ dB] = 10log 8.59 ⋅ 106 = 69.3dB )
Typical system requirements
– Audio: SNR ≅ 100dB
– Video: SNR ≅ 60dB
– Gigabit Ethernet Transceiver: SNR ≅ 35dB

Noise/Power Tradeoff
Assuming that we're already using the maximum available signal swing,
improving the SNR by 6dB means
– Increase C by 4x
– Decrease R by 4x to maintain bandwidth
– Increase gm by 4x to preserve gain
– Increase collector current by 4x
Bottom line
– Improving the SNR in a noise limited circuit by 6dB ("1bit")
QUADRUPLES power dissipation !
MDS and DR
Minimum detectable signal (MDS)

– Quantifies the signal level in a circuit that yields SNR=1,
SNR 1, i.e. noise
power = signal power
Dynamic range (DR) is defined as
Psignal,max
DR =
MDS
If the noise level in the circuit is independent of the signal level (which is
often, but not always the case), it follows that the DR is equal to the
"
"peak k SNR
SNR,"" i.e.
i theth SNR withith the
th maximum
i signal
i l applied
li d

Does Thermal Noise Always Matter?
Let’s look at the SNR of an RC circuit with a 1-V sinusoid applied,

considering the total integrated noise (kT/C)
SNR [dB] C [pF]

20 0.00000083
Hard to make such small capacitors…
40 0.000083
60 0.0083 Designer will be concerned about thermal
80 0 83
0.83 noise;
i componentt sizes
i often
ft sett by
b SNR
100 83
120 8300 A difficult battle with thermal noise …
140 830000
Rules of thumb
– Up to SNR ~ 30-40dB, integrated circuits are usually not limited by
thermal noise
– Achieving SNR >100dB is extremely difficult
• Must usually rely on external components, or reduce bandwidth
and remove noise by a succeeding filter
• See
S e.g. oversampling
li ADC
ADCs iin EE315B
More on Input Referred Noise
Suppose you wanted to sell this amplifier as a

“general purpose” building block
R How would you communicate information

about its noise performance to the customer?
None of the metrics that we have used so far
will work to describe the circuit independent of
the target application
– The computed input and output referred
voltage noise assumed that the circuit is
driven by an ideal voltage source

Two-Port Representation Using Equivalent Voltage and
Current Noise Generators
Short
Short-circuit
circuit both inputs and equate output noise
– This yields vi2
Open-circuit both inputs and equate output noise
– This yields ii2
This representation is valid for “any” source impedance
Sometimes need to consider correlation between equivalent voltage and
current generator, but often times only one of the two generators matters
in the target application
If both generators matter (and they are correlated), it is usually best
to avoid working with input referred noise representations
Datasheet Example

Examples
Single BJT device

Single
g MOS device
CE stage
CB stage
BJT Input Voltage Noise (1)
To find input referred voltage generator

generator, short the input of both circuit
models and equate output noise
Neglecting Cμ, rc and re for simplicity
Text, p. 757
2
io1 ≅ ic2 + gm (
2 2 2
ib ⋅ rb + v b2 )
2 2 2
io2 ≅ gm vi
2 2 ic2
io1 = io2 ⇒ v i2 ≅ v b2 + 2
+ ib2 ⋅ rb2
gm

BJT Input Voltage Noise (2)
The PSD of the BJT input voltage noise generator is therefore
vi2 2qI
≅ 4kTrb + 2C + 2qIBrb2
Δf gm
2qIC ⎡ gm 2 2⎤
rb
≅ 4kTrb + 2 ⎢1 + ⎥
gm ⎢⎣ β ⎥⎦
qC
2qI
≅ 4kTr
4kT b + 2
gm
⎛ 1 ⎞
≅ 4kT ⎜ rb + ⎟
⎝ 2gm ⎠
BJT Input Current Noise (1)
To find input referred current generator, open circuit the input of both
circuit models and equate output noise
Text, p. 757
2 2
io1 = ic2 + gm
2 2
⋅ ib ⋅ z π
2 2 2 2
io2 = gm ⋅ ii ⋅ z π
2 2 ic2
io1 = io2 ⇒ ii2 = ib2 + 2
2
gm zπ

BJT Input Current Noise (2)
1
rπ ⋅
ii2 2qIC jωCπ rπ β ( jω )
= 2qIB + where z π = = =
Δf 2
gm zπ
2 1 1 + jωrπCπ gm
rπ +
jωCπ
2qIC
= 2qIB + 2
β ( jω )
⎛ ⎛ ⎞ ⎞
2
⎜ 1+ ⎜ ω ⎟ ⎟
⎜ ⎜ ωβ ⎟ ⎟ 1 ω
= 2qIB ⎜ 1 + ⎝ ⎠ ⎟ where ωβ = ≅− T
⎜ β0 ⎟ rπCπ β0
⎜ ⎟
⎜ ⎟
⎝ ⎠
The term due to IC is negligible at low frequencies
frequencies, but becomes
comparable to the base current contribution at
ωT
ωb = ωβ β0 ≅
β0
Plot of BJT Input Noise Current PSD
Text, p. 760
N l t (f
Neglect (for BJT)

MOS Input Voltage Noise
2
io1 = ic2
Text, p. 762
2 2 2
io2 = gm vi
ic2 v i2 1 Kf 1
v i2 = 2
= 4kTγ +
gm Δf gm WLCox f
MOS Input Current Noise
2
2 1 ⎛ω ⎞
io1 = ic2 2
+ gm ⋅ i2g ⋅ ≅ ic2 + i2g ⋅⎜ T ⎟
ω2C2gs ⎝ ω ⎠
2
2 ⎛ω ⎞
io2 ≅ ii2 ⋅⎜ T ⎟
⎝ ω ⎠
2 2
⎛ ω ⎞ 2 ii2 ⎛ f ⎞ ⎛ 2
K f gm 1⎞
ii2 = i2g +⎜ ⎟⎟ ic ≅ 2qIG + ⎜ ⎟⎟ ⎜⎜ 4kT γg + ⎟
⎜ Δf ⎜ m
WLCox f ⎠⎟
⎝ ωT ⎠ ⎝ fT ⎠ ⎝

BJT versus MOS (1)
Noiseless
Transistor
Consider low source impedance Æ voltage noise will dominate
⎡ v2 ⎤ ⎛ 1 ⎞ ⎡ v2 ⎤ 1 Kf 1
⎢ i ⎥ ≅ 4kT ⎜ rb + ⎟ ⎢ i ⎥ ≅ 4kTγ +
⎢⎣ Δf ⎥⎦ ⎝ 2gm ⎠ ⎢⎣ Δf ⎦⎥ gm WLCox f
BJT MOS
BJT is usually
y superior
p
– Need less gm for approximately same noise
– gm/I is higher, making it easier to achieve low noise at a given current
budget
BJT versus MOS (2)
Consider high source impedance Æ current noise will dominate
⎡ i2 ⎤ ⎛ ⎞ ⎡ i2 ⎤ 2
⎛ f ⎞ ⎛
IC ⎟ K g2 1⎞
⎢ i ⎥ ≅ 2q ⎜ IB + ⎢ ⎥
i ≅ 2qIG + ⎜ ⎟ ⎜ 4kTγgm + f m ⎟
⎜ ⎜ f ⎟⎠
β ( jω) ⎠⎟
Δf 2 Δf
⎣⎢ ⎦⎥BJT ⎣⎢ ⎦⎥MOS ⎝ fT ⎠ ⎝ WLCox
⎝
MOS is usually superior

– Gate leakage current (IG) is typically much smaller than BJT base
current
• Unless the gate oxide becomes very thinthin, as e
e.g.
g in a 45-nm
45 nm
CMOS process that does not use high-k gate dielectrics

Example Revisited (With finite RS)
1
⎛ ⎛ ⎞ 4kT
vi2 1 1 ⎞ ii2 I
≅ 4kT ⎜ rb + + 2 ⎟ = 2q ⎜ IB + C ⎟+ R
Δf ⎜ 2gm gmR ⎟⎠ Δf ⎜ 2⎟ 2
⎝ ⎝ β ( jω ) ⎠ β ( j ω )
Calculation of Equivalent Source Noise
v 2s = vRs
2
+ v i2 + R2s ii2
⎡ ⎛ ⎞ 4kT ⎤⎥
1
v 2s ⎛ 1 1 ⎞ 2⎢ I
= 4kTRS + 4kT ⎜ rb + + 2 ⎟ + Rs ⎢2q ⎜ IB + C ⎟+ R
2⎥
Δf ⎜ 2g ⎟ ⎜ 2⎟
⎝ m g R
m ⎠ ⎢ ⎝ β ( jω ) ⎠ β ( jω ) ⎥
⎣ ⎦

Alternative Method
Draw complete circuit with all noise sources

Compute transfer function from each noise source to the output
Refer to output using squared transfer function
Sum all output referred noise components
Divided obtained sum by squared transfer function from input source to
the output
Output Referred Noise PSD
v out zπ
H(s) = = −gmR
vs z π + Rs
gmR
=−
g R
1+ m s
β ( jω )
2
v out 2 ⎛ 1 ⎞
= 4kTRS* H(s) + ⎜ 4kT + 2qIC ⎟ ⋅ R2 (neglecting base shot noise for simplicity)
Δf ⎝ R ⎠
2
v out ⎛ 1 ⎞ 2
v 2s ⎜ 4kT R + 2qIC ⎟ ⋅ R
= Δf 2 = 4kTRS* + ⎝ 2
⎠
Δf H(s) H(s)

Source Referred Noise PSD
2
⎛ 1 ⎞ 2 gmRs
⎜ 4kT R + 2qIC ⎟ ⋅ R 1 + β jω
v 2s ⎝ ⎠ ( )
= 4kTRS* +
Δf ( gmR )2
⎛ ⎡ 1
2⎞
⎜ 1 ⎤ gmRs ⎟
= 4kTRS + 4kT rb + ⎢ + 2 ⎥ ⋅ 1+
⎜ ⎢⎣ 2gm gmR ⎥⎦ β ( jω ) ⎟
⎝ ⎠
This result does not match what we would expect from the analysis with
BJT input referred generators:
⎡ 1 ⎤
⎛ 4kT ⎥
v 2s 1 1 ⎞ ⎢ 2qI R
= 4kTRS + 4kT ⎜ rb + + 2 ⎟ + Rs2 ⎢ C
+ 2⎥
Δf ⎜ 2g ⎟ 2
⎝ m gmR ⎠ ⎢ β ( jω ) β ( jω ) ⎥
⎣ ⎦
Reason for Discrepancy
It turns
t outt that
th t the
th resultlt obtained
bt i d using
i the
th BJT input
i t referred
f d
generators is not quite correct
From vi2 From ii2
⎡ 1 ⎤
⎛ 4kT ⎥
v 2s 1 1 ⎞ 2 ⎢ 2qIC R
= 4kTRS + 4kT ⎜ rb + + 2 ⎟ + Rs ⎢ + 2⎥
Δf ⎜ 2
2g ⎟ 2
⎝ m g R
m ⎠ ⎢ β ( jω ) β ( jω ) ⎥
⎣ ⎦
Due to RS Due to rb Collector Due to R Collector Due to R

shot noise shot noise
In this expression,
expression we are adding the powers of correlated noise currents
without taking the correlation into account!
This leads to an expression that overestimates the noise

Conclusion on Input Referred Noise Generators
W
Working
ki withith input
i t referred
f d noise
i generators
t saves time
ti and
d works
k wellll
if the input source can be modeled close to a an ideal voltage source (RS
is small) or an ideal current source (RS is large)
– In this case,
case either the input referred noise voltage or current will
clearly dominate and only one of the two generators must be
considered
– Note that for RS=0, the two expression on slide 65 match perfectly
For any scenario in-between, working with input referred generators can
still work as long as the input referred current and voltage generators are
statistically independent, i.e. they are due physically distinct noise
mechanisms
– This is not the case for the expressions of slide 65
When all of these conditions fail, it is a must to analyze
y the circuit from
first principles, i.e. consider all noise sources at their root and refer them
to the point(s) of interest via their individual transfer functions
Noise Performance of Feedback Circuits: Ideal Feedback
Consider an amplifier with input referred noise sources placed into an

ideal series-shunt feedback
f configuration
f (no
( loading effects)
ff )
We can identify the equivalent input noise generators for the overall
circuit in the same way we have done this previously
– Short-circuit the input, find input noise voltage generator that yields
the same output noise in both circuits
– Open-circuit the input, find input noise current generator that yields

Input Shorted
Equal output noise in both circuits is obtained for
vi2 = via
2
Input Open
Equal output noise in both circuits is obtained for
ii2 = iia
2

Observation
For the idealized example studied on the previous slides, we see that
the equivalent input noise generators of the amplifier can be moved
unchanged
h d outside
t id th
the ffeedback
db k lloop
– Applying feedback has no effect on the circuit’s noise performance
– Note that this is very different from the effect of feedback on
distortion performance
This results holds for all four possible (ideal) feedback configurations
– Prove this as an exercise
In practical feedback configurations, the input referred generators must
be computed while taking loading effects into account
– Loading makes the calculations more complicated, and generally
worsens the
th noise
i performance
f
– In the best possible design outcomes, the noise performance can
approach (but not surpass) that of an idealized configuration
Including Loading and Noise from the Feedback Network
Th
The mostt generall way off including
i l di loading
l di and d noise
i ffrom th
the ffeedback
db k
network is to apply the same procedure as before
– Short-circuit the input, find input noise voltage generator that yields
– Open-circuit the input, find input noise current generator that yields
A more convenient way to include loading and noise from the feedback
network is to use the same two-port approximations we have already
utilized for transfer function analysis
Procedure
– Absorb loading effects into the basic amplifier and work with ideal
feedback network
– Re
Re-compute
compute the input referred noise generators of the basic amplifier
in presence of loading
– Using the previous result, the re-computed noise generators of the
basic amplifier can now be moved outside the feedback loop

Example: Practical Series-Shunt Circuit
Basic Amplifier with Loading
Step 1
– Redraw the basic amplifier with loading included

Input Referred Noise Current (Open-Circuited Input)
Step 2
– Compute input referred current noise
– The result corresponds to the desired ii
ii2 = iia
2
Input Referred Noise Voltage (Short-Circuited Input)
Step 3
– Compute input referred voltage noise
– The result corresponds to the desired vi
via2 iia2
RE||RF
2
vi2 = v ia
2 2
+ iia ⋅ (RE || RF ) + 4kT (RE || RF ) Δf
4kT(RE||RF)

Example: Practical Shunt-Shunt Circuit
v i2 = via
2
2
via 1
ii2 2
= iia + + 4kT Δf
RF2 RF
(assuming iia and via are uncorrelated)
High Frequency Issue
At low
l ffrequencies,
i it iis ttypically
i ll nott h
hard
d tto minimize
i i i ththe iinputt noise
i
current contribution due to via
However, at high frequencies, any shunt capacitance at the input tends
t make
to k the
th via contribution
t ib ti more significant
i ifi t
Means that via must be minimized in high speed circuits, typically by
increasing gm of the input device Æ higher power dissipation
2
1 1
ii2 2
= iia 2
+ v ia + jωCi + 4kT Δf (assuming iia and via are uncorrelated)
RF RF

Local Feedback Circuit Examples
vo g R io gm io g R
Av = = m Gm = = Ai = = m
vi 1 + gmR vi 1 + gmR ii 1 + gmR
Neglecting finite ro, backgate effect and flicker noise for simplicity
Source Follower
Th
The noise
i performance
f can be
b analyzed
l d by
b treating
t ti theth circuit
i it as a
series feedback stage (see text, sections 8.6.2 and 11.7.2)
– We will do a direct analysis instead
2
⎛ ⎞
(
v o2 = i2d + ir2 ) ⎜ 1 ⎟
⋅⎜
i2d + ir2 2
⎟ = 2 ⋅ Av
⎜ gm + 1 ⎟ gm
⎝ R⎠
Often negligible
i2d ir2 1 ⎛ 1 ⎞
v i2 = 2
+ 2
= 4kT Δf ⎜ γ + ⎟
gm gm gm ⎝ gmR ⎠
The noise in a resistively loaded source follower is typically dominated

by the contribution from the transistor
The input referred noise voltage can be approximated by the drain
current noise reflected through the device’s
device s transconductance

Degenerated Common Source Stage
gm
io = id + ( ir − id )
1
gm +
R
gmR 1
= ir + id
1 + gmR 1 + gmR
Gm
= ir GmR + id
gm
⎛ i2 ⎞ i2d 1
io2 = ⎜ d2 + ir2R2 ⎟ ⋅ Gm
2
v i2 = + ir2R2 = 4kTγ Δf + 4kTRΔf
⎜ gm ⎟ 2
gm gm
⎝ ⎠
The input referred voltage noise consists of drain current noise, reflected
through gm, plus the resistor’s voltage noise
Common Gate Stage
gmR 1
io = ir + id
1 + gmR 1 + gmR
Ai
= ir A i + id
gmR
Often negligible
⎛ i2 ⎞ i2d 1 ⎛ γ ⎞
io2 = ⎜ d + ir2 ⎟ ⋅ A i2 ii2 = + ir2 = 4kT Δf ⎜ 1 + ⎟
⎜ gm
2 2 ⎟ 2 2 R ⎝ gmR ⎠
⎝ R ⎠ gm R
Th
The input
i t referred
f d currentt noise
i from
f the
th transistor
t i t isi often
ft negligible
li ibl (at
( t
low frequencies)
The noise tends to be dominated by the devices providing the source
and
dddrain
i bi
bias currents
t ((resistors
i t or currentt sources))

Common Gate Stage at High Frequencies
2
1
+ j ωC
2 1 R
ii = 4kT Δf + 4kTγgm Δf 2
R gm
2
1 ⎛ ωC ⎞
≅ 4kT Δf + 4kTγgm Δf ⎜ ⎟
R ⎝ gm ⎠
The input referred current noise from the transistor can be significant at
high frequencies (near the cutoff frequency of the current transfer)
Summary – Noise in Feedback Circuits
Applying ideal feedback around an amplifier does not alter its input
referred noise performance
In practical circuits, loading and noise from the feedback network tend to
deteriorate the circuit’s overall noise performance
– This is especially true at high frequencies, where parasitic
capacitances
it can increase
i th
the noise
i ttransfer
f from
f sources that
th t are
typically negligible at low frequencies
Loading effects can be considered by applying the same two-port
approximation
i ti methodsth d used d iin th
the ttransfer
f ffunction
ti analysis
l i off practical
ti l
feedback amplifiers
– Absorb loading and feedback network noise sources into forward
amplifier and work with idealized feedback result

Additional Topics in Noise Analysis
Covered in EE314
– RF-centric metrics
• Noise figure
• Receiver sensitivity
– Phase noise in oscillators
Covered in EE315A,B
– Noise in filters and switched capacitor circuits
Other
– Cyclostationary noise
• Noise in circuits that are driven by a periodic waveform that
modulates the power spectral densities
• E.g. mixers

Chapter 9
Distortion Analysis
y
B. Murmann
Stanford University
Reading Material: Sections 1.4.1, 5.3.2
Overview
Low frequency distortion analysis

Effect of feedback on distortion
High frequency distortion analysis

Introduction
All electronic
l t i circuits
i it exhibit
hibit some llevell off nonlinear
li b
behavior
h i
– The resulting waveform distortion is not captured in small-signal
models
In the first section of this chapter, we will begin by looking at the basic
tools needed to analyze “memoryless” nonlinearities, i.e. nonlinearities
that can be represented by a frequency independent model
– Such models are valid in a frequency range where all capacitances
and inductances in the circuit of interest can be ignored
As a driving example, we will analyze the nonlinearity in the V-I
transduction of BJTs and MOSFETs
The general approach taken is to model the nonlinearities via a power
series that links the input and output of the circuit
– This approach is useful and accurate for the case of “small
small distortion”
distortion
and cannot be used to predict the effect of gross distortion, e.g. due
to signal clipping
Small-Signal AC Model
Io = IOQ + io io
+ gm⋅vi
+
Vi = VIQ + vi vi
- dIo -
gm =
dVi V = V
i IQ
Io = f(Vi) = f '(VIQ ) io
gm gm
vi
Vi
VIQ

Taylor Series Model
(3)
f '(VIQ ) f ''(VIQ ) 2 f (VIQ )
f(Vi ) = f(VIQ ) + (Vi − VIQ ) + (Vi − VIQ ) + (Vi − VIQ )3 + ...
1! 2! 3!
f2(Vi)
f3(Vi)
f(Vi)
f2(Vi)
Vi
VIQ
f3(Vi)
Relationship Between Incremental Variables
Using vi = Vi − VIQ and io = Io − IOQ = f(Vi ) − f(VIQ )
we obtain io = a1v i + a2 v i2 + a3 v i3 + ...
f (m) (VIQ
Q)
where am =
m!
1 ' 1 ''
Note that a1 ≡ gm a2 ≡ gm a3 ≡ gm
2 6
In practice, it is often sufficient to work with a truncated nth order power

series
io ≅ a1v i + a2 v i2 + ... + an v in

Graphical Illustration
io
n=2
vi
n→∞
n=3
A model that relates the incremental signal components (vi, io) though a
nonlinear expression is sometimes called “large-signal AC model”
The accuracy of a truncated power series model depends on the signal
range and the curvature of the actual transfer function
– Using a higher order series generally helps, but also makes the
analysis more complex
– As we will see, using a third order series is often sufficient to model
th relevant
the l t distortion
di t ti effects
ff t in
i practical,
ti l weaklykl nonlinear
li circuits
i it
Harmonic Distortion Analysis
Apply a sinusoidal signal and collect harmonic terms in the output signal
v i = vˆ i ⋅ cos ( ωt )
2 3
io = a1vˆ i cos ( ωt ) + a2 ⎡⎣ vˆ i cos ( ωt ) ⎤⎦ + a3 ⎡⎣ vˆ i cos ( ωt ) ⎤⎦ + ...
1 1
cos2 ( α ) = ⎡cos ( 2α ) + 1⎤⎦ cos3 ( α ) = ⎡cos ( 3α ) + 3 cos ( α ) ⎤⎦
2⎣ 4⎣
⎡1 ⎤
∴ io = ⎢ a2 vˆ i2 ⎥ DC shift
⎣2 ⎦
⎡ 3 ⎤
+ ⎢a1vˆ i + a3 vˆ i3 ⎥ cos ( ωt ) Fundamental
⎣ 4 ⎦
⎡1 ⎤ ⎡1 ⎤
+ ⎢ a2 vˆ i2 ⎥ cos ( 2ωt ) + ⎢ a3 vˆ i3 ⎥ cos ( 3ωt ) + ... Harmonics
⎣2 ⎦ ⎣4 ⎦

Observations
Th
The quadratic
d ti tterm ((a2) give
i rises
i tto an undesired
d i d second
dhharmonic
i ttone
and a DC shift
The cubic term (a3) give rises to an undesired third harmonic tone and it
also
l modifies
difi th
the amplitude
lit d off th
the ffundamental
d t l
– a3 < 0 Æ “gain compression”
– a3 > 0 Æ “gain expansion”
y x + 0.3x3
x
x - 0.3x
0 3x3
Waveforms with Gain Expansion
x = cos ( 2πt ) a1 = 1 a3 = 0.3

Waveforms with Gain Compression
x = cos ( 2πt ) a1 = 1 a3 = −0.3
Higher Order Terms
m
⎛m⎞
1
( ) 1
m − j( m − k ) α
cosm ( α ) = m
e jα + e − j α = m ∑ ⎜ k ⎟e jkα e
2 2 k =0 ⎝ ⎠
1
cos4 ( α ) = ⎡cos ( 4α ) + 4 cos ( 2α ) + 3 ⎤⎦
8⎣
1
cos5 ( α ) = ⎡cos ( 5α ) + 5cos ( 3α ) + 10 cos ( α ) ⎤⎦
16 ⎣
Can show that

– Terms raised to even powers of m affect the DC shift and even
harmonics up to m
– Terms raised to odd powers of m affect the fundamental and odd
harmonics up to m

Inspection of 4th and 5th Order Contributions
⎡1 3 ⎤ As long as
∴ io = ⎢ a2 vˆ i2 + a4 vˆ i4 ⎥
⎣2 8 ⎦
a 4 vˆ i4 << a2 vˆ i2 and a5 vˆ i5 << a3 vˆ i3
⎡ 3 5 ⎤
+ ⎢a1vˆ i + a3 vˆ i3 + a5 vˆ i5 ⎥ cos ( ωt )
⎣ 4 16 ⎦
or equivalently
⎡1 1 ⎤
+ ⎢ a2 vˆ i2 + a4 vˆ i4 ⎥ cos ( 2ωt )
⎣ 2 2 ⎦ a2 a3
vˆ i << and vˆ i <<
⎡1 5 ⎤ a4 a5
+ ⎢ a3 vˆ i3 + a5 vˆ i5 ⎥ cos ( 3ωt )
⎣4 16 ⎦
the 4th and 5th order terms can
⎡1 ⎤ be neglected
+ ⎢ a 4 vˆ i4 ⎥ cos ( 4ωt )
⎣8 ⎦
This condition is usually met in
⎡1 ⎤
+ ⎢ a5 vˆ i5 ⎥ cos ( 5ωt ) practical, weakly nonlinear
⎣ 16 ⎦ circuits
Fractional Harmonic Distortion Metrics
amplitude of second harmonic distortion signal

HD2 =
amplitude of fundamental
amplitude
amplit de of third harmonic distortion signal
HD3 =
amplitude of fundamental
IIncluding
l di only
l contributions
t ib ti ffrom tterms up tto 3rdd order,d th
these quantities
titi
become
1
a2 vˆ i2
2 1 a2
HD2 ≅ ≅ vˆ i
3 3 2 a
ˆ
a1v i + a3 vi ˆ 1
4
1
a3 vˆ i3
4 1 a3 2
HD3 ≅ ≅ vˆ i
3 3 4 a
a1vˆ i + a3 vˆ i 1
4

Total Harmonic Distortion
total power of distortion signals

THD =
power of fundamental
= HD22 + HD32 + HD24 + ...
THD iis often

ft d dominated
i t db by th
the HD2 and/or
d/ HD3 term
t
Typical application requirements
– Telephone audio: THD < ~10%
– Video: THD < ~1%
– RF low noise amplifiers: THD < ~0.1%
– High quality audio: THD < ~0.01%
Intermodulation Distortion (1)
Consider applying two tones to the nonlinear device
v i = vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t )
io = a1 ⎡⎣ vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t ) ⎤⎦
2
+a2 ⎣⎡ vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t ) ⎦⎤
3
+a3 ⎡⎣ vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t ) ⎤⎦ + ...
Inspect second-order term

2 2
a2 ⎡⎣ vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t ) ⎤⎦ = a2 ⎡⎣ vˆ i1 ⋅ cos ( ω1t ) ⎤⎦
C
Causes HD
2
+a2 ⎡⎣ vˆ i2 ⋅ cos ( ω2 t ) ⎤⎦
+2a2 ⎡⎣ vˆ i1vˆ i2 ⋅ cos ( ω1t ) cos ( ω2 t ) ⎤⎦ New

Second-Order Intermodulation
2a2 ⎡⎣ vˆ i1vˆ i2 ⋅ cos ( ω1t ) cos ( ω2 t ) ⎤⎦ = a2 vˆ i1vˆ i2 ⎡⎣cos ({ω1 + ω2 } t ) + cos ({ω1 − ω2 } t ) ⎤⎦
The output will contain tones at the sums and differences of the applied
frequencies
We define the fractional second-order intermodulation as
amplitude of second order IM components (for vˆ i1 = vˆ i2 = vˆ i )

second-order
IM2 =
amplitude of fundamentals
a2 vˆ i2 a2
= = vv̂ i
a1 vˆ i a1
= 2HD2
Third-Order Intermodulation (1)
3 3
a3 ⎡⎣ vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t ) ⎤⎦ = a3 ⎡⎣ vˆ i1 ⋅ cos ( ω1t ) ⎤⎦
Causes HD
3
+a3 ⎡⎣ vˆ i2 ⋅ cos ( ω2 t ) ⎤⎦
+3a3 ⎡ vˆ i1vˆ i2
2
⋅ cos ( ω1t ) cos2 ( ω2 t ) ⎤
⎣ ⎦
New
+3a3 ⎡ vˆ i1
⎣
2ˆ
v i2 ⋅ cos 2
( ω1t ) cos ( ω2t )⎤⎦
3 3 ⎡ vˆ i1vˆ i2
3a 2
⋅ cos ( ω1t ) cos2 ( ω2 t ) ⎤
⎣ ⎦
3
⎣2cos ( ω1t ) + cos ({2ω2 − ω1} t ) + cos ({2ω2 + ω1} t ) ⎦
2 ⎡ ⎤
= a3 vˆ i1vˆ i2
4
“Gain desensitization term” Third-order

For a3<0, large vi2 reduces Intermodulation
fundamental tone due to vi1 Products

Third-Order Intermodulation (2)
Third-order intermodulation products appear at (2ω2 ± ω1) and (2ω1 ± ω2)

We define the fractional third-order intermodulation as
amplitude of third-order IM components (for vˆ i1 = vˆ i2 = vˆ i )

IM3 =
amplitude of fundamentals
3 a3 vˆ i3 3 a3 2
= = v̂ i = 3HD3
4 a1 vˆ i 4 a1
Note that for ω2 ≅ ω1, the third-order

intermodulation products are close to the
original frequencies and cannot be
filtered out
– This is a significant issue in
narrowband systems
Distortion in a CE Stage (1)
Vbe Vbe
kT dIc I
Ic = Ise VT VT = a1 = = s e VT
q dVbe VT
Vbe = VBEQ
Vbe = VBEQ
ICQ
= ≡ gm
VT
1 d2Ic 1 ICQ
a2 = 2
=
2 dVbe 2 VT2
Vbe = VBEQ
1 ICQ
am =
m! VTm

Distortion in a CE Stage (2)
2
1 a2 1 vˆ be 1 a3 2 1 ⎛ vˆ be ⎞
HD2 ≅ vˆ be = HD3 ≅ vˆ be = ⎜ ⎟
2 a1 4 VT 4 a1 24 ⎜⎝ VT ⎟⎠
Low distortion in the collector current quires the B-E voltage excursion to
be much smaller than VT ≅ 26mV
Checking for the valid range of a third order model yields
a2 a3
vˆ be << = 12VT and vˆ be << = 20VT
a4 a5
For a B-E voltage swing of VT, we have
HD2 ≅ 25% HD3 ≅ 4.17%
Note that a typical application will demand much lower distortion
Distortion in a CS Stage (1)
dId W
Id =
1
2
μCox
W
L
(
Vgs − Vt )
2
a1 =
dVgs
= μCox
L
(
Vgs − Vt )
Vgs = VGSQ Vgs = VGSQ
W 2I
= μCox VOV = DQ ≡ gm
L VOV
1 d2Id 1 W IDQ
a2 = 2
= μCox = 2
2 dVgs 2 L VOV
Vgs = VGSQ
a3 = 0

Distortion in a CS Stage (2)
1 a2 1 v̂ gs
HD2 ≅ vˆ gs = HD3 = 0
2 a1 4 VOV
Small second harmonic distortion in the drain current requires the G-S
voltage excursion to be much smaller than the quiescent point gate
overdrive
d i (VOV=VVGS-VVt)
An idealized square-law device does not introduce high order distortion
– However, this is not true for a real short-channel MOSFET
Relevant effects
– Velocity saturation, mobility reduction due to vertical field
– Biasingg in moderate or weak inversion
– Nonlinearity in the device’s output conductance
– …
Distortion in Modern MOSFETS
Distortion in modern MOSFET devices is generally hard to model

accurately
A basic approach for devices operating in strong inversion is to include
short channel effects via basic extensions to the square law model
– E.g. model velocity saturation as resistive source degeneration
– See e e.g.
g Terrovitis & Meyer,
Meyer JSCC 10/2000
Another approach is to extract the coefficients from “known-to-be-
accurate” Spice models
– Find coefficients am by simulating the derivatives of I-V curves
– See e.g. Blaakmeer et al., JSSC 6/2008
Unfortunately, generating accurate Spice models for MOSFET distortion
is a very difficult task
– See e.g. R. van Langevelde et al., IEDM 2000
Never trust a Spice model blindly!

Distortion of EE214 NMOS Device
Distortion in a BJT Differential Pair (1)
⎛ V ⎞
Icd = Ic1 − Ic2 = αIEE tanh ⎜ id ⎟
⎝ 2VT ⎠
c1 c2
1 3 2 5
tanh ( x ) = x − x + x − +...
3 15
id
αIEE αIEE αIEE
a1 = ≡ Gm a3 = − a5 =
2VT 24VT3 240VT5
EE
Third-order model is accurate for
a3
v̂ id << = 10VT
a5

Distortion in a BJT Differential Pair (2)
A differential pair with perfectly matched transistors does not generate

any even-order distortion products
Any mismatch (e.g. in Is) will cause non-zero even-order terms
– The resulting even order distortion products are typically smaller than
the inherent odd-order distortion
The HD3 performance of a BJT differential pair is better than that of a

single BJT transistor
2 2
1 a3 2 1 ⎛ vˆ id ⎞ 1 ⎛ vˆ be ⎞
HD3,BJTdiff ≅ vˆ id = ⎜ ⎟ HD33,BJT ≅ ⎜ ⎟
48 ⎜⎝ VT ⎟⎠ 24 ⎜⎝ VT ⎟⎠
3 BJTdiff BJT
4 a1
Distortion in a MOS Differential Pair
2
⎛ V ⎞ ⎛ V ⎞
Iod = Id1 − Id2 = ISS⎜ id ⎟ 1 − ⎜ id ⎟
⎝ VOV ⎠ ⎝ 2VOV ⎠
d1 d2
2
⎛x⎞ 1 1 5
x 1 − ⎜ ⎟ = x − x3 − x + ...
⎝2⎠ 8 128
id
ISS ISS ISS
a1 = ≡ Gm a3 = − 3
a5 = 5
VO
OV 8VOV 128VOV
SS
Third-order model is accurate for
a3
v̂ id << = 4VOV
a5

Feedback and Distortion
Low-frequency distortion is a result of variations in the slope of an

amplifier’s transfer characteristic. Feedback reduces the relative
variation, and thus the distortion, to the same extent that it reduces
fractional changes in gain.
gain
Vout
Vin
Note that feedback reduces distortion without reducing the output

voltage range. The gain is also reduced, but additional gain can be
provided with a preamplifer the operates with smaller signal swings, and
therefore less distortion.
Power Series Analysis (1)
+ Sε
Si – a So
–
Sfb
f
So = a1Sε + a 2S2ε + a3S3ε + K

Sε = Si − f ⋅ So
∴ So = a1(Si − f ⋅ So ) + a 2 (Si − f ⋅ So )2 + a3 (Si − f ⋅ So )3 + K

Expressing So as a power series expansion in Si
So = b1Si + b 2Si2 + b3Si3 + K
Substitute this expression for So into the result on the previous page and
compare coefficients to find bi
b1Si = a1(Si − f ⋅ b1Si )
a1
b1 =
1+ a1f
Thus, the feedback reduces the coefficient of the fundamental term in

the forward amplifier by 1 + af
Second-order terms
b 2Si2 = −a1f ⋅ b 2Si2 + a 2 ((Si − f ⋅ b1Si )2

a 2 (1− b1f)2 a2
b2 = =
1+ a1f (1+ a1f)3
Third-order terms
b3Si3 = −a1f ⋅ b3Si3 − 2a 2Si3 f ⋅ b 2 (1− f ⋅ b1) + a3 (Si − f ⋅ b1Si )3

a3 (1− b1f)3 − 2a 2 f ⋅ b 2 (1− f ⋅ b1) a3 (1+ a1f) − 2a 22 ⋅ f
b3 = =
1+ a1f (1+ a f)51

Comments
Large loop gain (a1f) leads to small nonlinearity

b3 contains a term due to a2
– This is due to signal interaction with the second-order term fed back
to the input
It is possible to obtain b3 = 0 without large loop gain
An Interesting Example
VCC
IC = ICQ+ iC
So = iC = a1Sε + a 2S2ε + a3S3ε + L
Sε = vBE = v i − f ⋅ iC
Q
vi
~
1 IC 1 IC
Vi RE f = RE a1 = gm a2 = a3 =
2 V2 6 V3
T T
a1 gm 1 IC 1
b1 = = b2 =
1+ a1f 1+ gmRE 2
2 V (1+ g R )3
T m E
1 IC 1 IC
(1+ gmRE ) − g R
6 V3 2 V3 m E 1
b3 = T T gmRE = ⇒ b3 = 0 ⇒ HD3 = 0
(1+ gmRE )5 2

High Frequency Distortion Analysis
The power series approach studied previously ignores any frequency

dependence introduced by reactive elements
– Sufficient for 90% of typical circuits, including some operating at RF
Assuming weakly nonlinear behavior, the frequency dependence can be
included using a Volterra Series model
– Vito Volterra, 1887
The purpose of this handout is to provide a few basic examples that will
allow you to understand the general framework
Examples
– Memoryless nonlinearity followed by a filter
– Memoryless nonlinearity preceded and followed by a filter
– RC circuit with nonlinear capacitance
– RC circuit with nonlinear resistance
Example 1
R ic = a1vi + a2 vi2 + a3 vi3 + ...

ic
vo
1 ICQ 1 ICQ
a1 = gm a2 = a3 =
2 VT2 6 VT3
C
vi
vo −R
VI
K( jω) = =
ic 1 + jωRC
Ignoring device capacitances and finite output resistance for simplicity

Single-Tone Input
vi = vˆ i cos ( ωt )
Ignoring DC offset and gain expansion, we have
1 1
ic = a1vˆ i cos ( ωt ) + a2 vˆ i2 cos ( 2ωt ) + a3 vˆ i3 cos ( 3ωt ) + ...
2 4
The output voltage consists of the same tones, with their magnitude and
phase altered by the linear filter K(jω)
v o = K ( jω) ⋅ a1vˆ i cos ( ωt + φω )
1 φmω = ∠K ( m ⋅ jω)
+ K ( 2jω) ⋅ a2 vˆ i2 cos ( 2ωt + φ2ω )
2
1
+ K ( 3jω) ⋅ a3 vˆ i3 cos ( 3ωt + φ3ω ) + ...
4
Two-Tone Input
vi = vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2 t )
Substituting this input into the power series

series, and using the identities
shown below, the complete expression for the collector current is most
elegantly expressed as shown on the next slide
1
cos ( α ) cos ( β ) = ⎡cos ( α + β ) + cos ( α − β ) ⎤⎦
2⎣
1
cos ( α ) cos ( β ) cos ( γ ) = ⎡cos ( α + β + γ ) + cos ( α + β − γ )
4⎣
+ cos ( α − β + γ ) + cos ( α − β − γ ) ⎤⎦

Frequency
Components
ic = a1 ⎡⎣ vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2 t ) ⎤⎦ ω1, ω2
a2 ⎡ 2
+ vˆ 1 cos ([ ω1 ± ω1] t ) + vˆ 22 cos ([ ω2 ± ω2 ] t ) 0, 2ω1, 2ω2
2 ⎣
+2vˆ 1 vˆ 2 cos ([ ω1 ± ω2 ] t ) ⎤ ω1-ω2, ω1+ω2

⎦
a3 ⎡ 3
+ vˆ 1 cos ([ ω1 ± ω1 ± ω1] t ) + vˆ 32 cos ([ ω2 ± ω2 ± ω2 ] t ) ω1, ω2, 3ω
3 1, 3ω
3 2
4 ⎣
+ 3vˆ 12 vˆ 2 cos ([ ω1 ± ω2 ± ω2 ] t ) ω1, 2ω1-ω2, 2ω1+ω2
+ 3vˆ 1 vˆ 22 cos ([ ω1 ± ω1 ± ω2 ] t ) ⎤ + ... ω2, 2ω2-ω1, 2ω2+ω1

⎦
Filtered Output
( ) (
v o = a1 ⎡ vˆ 1 K ( jω1 ) cos ω1t + φω1 + vˆ 2 K ( jω2 ) cos ω2 t + φω2 ⎤
⎣ ⎦ )
a2 ⎡
+
2 ⎣ ( )
K ( 2jω1 ) ⋅ vˆ 12 cos 2ω1t + φ2ω1 + vˆ 12 K ( 0 )
( )
+ K ( 2jω2 ) ⋅ vˆ 22 cos 2ω2 t + φ2ω2 + vˆ 22 K ( 0 )
(
+ K ( j [ ω1 − ω2 ]) ⋅ 2vˆ 1 vˆ 2 cos [ ω1 − ω2 ] t + φω1−ω2 )
(
+ K ( j [ ω1 + ω2 ]) ⋅ 2vˆ 1 vˆ 2 cos [ ω1 + ω2 ] t + φω1+ω2 ⎤
⎦ )
a3
+
4
[...]

Short Hand Notation
v o = a1K ( jωa ) v i + a2K ( jωa + jωb ) v i2 + a3K ( jωa + jωb + jωc ) v i3 + ...
H1( jωa ) H2 ( jωa + jωb ) H3 ( jωa + jωb + jωc )
Operator “◦” means

– Multiply each frequency component in vim by
Hm ( jωa, jωb,...)
and shift phase by
∠Hm ( jωa, jωb,...)
The arguments ωa, ωb, ωc, … are auxiliary variables taking on all
permutations of ω1, ±ω2, … ±ωm
General Frequency Domain Volterra Series
v o = H1 ( jωa ) v i + H2 ( jωa , jωb ) v i2 + H3 ( jωa , jωb , jωc ) v i3 + ...
For the circuit example discussed previously, the coefficients are given
as follows
−a1R
H1(jωa ) =
1 + jωaRC
−a2R
H2 (jωa , jωb ) =
1 + ( jωa + jωb ) RC
−a3R
H3 (jωa , jωb , jωc ) =
1 + ( jωa + jωb + jωc ) RC

Distortion Metrics
Taylor Series Volterra Series
1 a2 1 H2 ( jω1, jω1 )
HD2 v̂ i
v v̂ i
v
2 a1 2 H1 ( jω1 )
1 a3 2 1 H3 ( jω1, jω1, jω1 ) 2

HD3 v̂i
v vi
v̂
4 a1 4 H1 ( jω1 )
3 a3 2 3 H3 ( jω1, jω1, − jω2 ) 2

IM3 v̂i v̂i
4 a1 4 H1 ( jω1 )
Volterra series model

– Second and third order distortion still vary with square and cube of input
amplitude, respectively
– But, there is no fixed relationship between HD2 and IM2, and HD3 and IM3
Distortion Metrics for Example 1
1
1 H2 ( jω, jω) 1 a2 1 + 2jωRC 1 a2 1 + jωRC
HD2 = vˆ i = vˆ i = vˆ i
2 H1 ( jω) 2 a1 1 2 a1 1 + 2jωRC
1 + jωRC
1 H3 ( jω, jω, jω) 2 1 a3 1 + jωRC 2

HD3 = vˆ i = vˆ i
4 H1 ( jω) 4 a1 1 + 3jωRC
3 H3 ( jω1, jω1, − jω2 ) 2 1 a3 1 + jωRC

IM3 = vˆ i = vˆ i2
4 H1 ( jω1 ) 4 a1 1 + j ( 2ω1 − ω2 ) RC

HD2 and HD3 Distortion Plots for Example 1
VT
ICQ = 1mA vˆ i =
5
IM3 Distortion Plot for Example 1
ICQ = 1mA
VT
vˆ i1 = vˆ i2 =
5
For ω2 → ω1, the IM3 distortion product is close to the fundamental tone
ω1, and therefore IM3 becomes nearly frequency independent

Example 2
2 3
ic = a1vbe + a2 vbe + a3 vbe + ...
vo −R
K(jω) = =
ic 1 + jωRC
vbe 1
K in (jω) = =
vi 1 + jωRinCin
Similar to example 1, but now including an additional filter at the input
Two-Tone Input
vi = vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2 t )
The two input tones are now processed by a linear filter before being
sent through the nonlinearity
At the base of the BJT, we have
( ) (
v be = K in ( jω1 ) ⋅ vˆ 1 cos ω1t + ψ ω1 + K in ( jω2 ) ⋅ vˆ 2 cos ω2 t + ψ ω2 )
ψmω = ∠K in ( m ⋅ jω)
In short hand notation, this can be written as
v be = K in ( jωa ) v i

v o = a1K ( jωa ) v be + a2K ( jωa + jωb ) v be
2
+ a3K ( jωa + jωb + jωc ) v be
3
+ ...
v o = a1K ( jωa ) ⎡⎣K in ( jωa ) v i ⎤⎦
2
+ a2K ( jωa + jωb ) ⎡⎣K in ( jωa ) v i ⎦⎤
3
+ a3K ( jωa + jωb + jωc ) ⎡⎣K in ( jωa ) v i ⎤⎦
First order term
a1K ( jωa ) ⎡⎣K in ( jωa ) v i ⎤⎦ = a1K ( jωa ) K in ( jωa ) v i
Second order term

2
a2K ( jωa + jωb ) ⎡⎣K in ( jωa ) v i ⎤⎦ = ?
2 2
⎡⎣K in ( jωa ) v i ⎤⎦ = ⎡⎣K in ( jωa ) {vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2t )}⎤⎦
2
( ) (
= ⎡ K in ( jω1 ) ⋅ vˆ 1 cos ω1t + ψ ω1 + K in ( jω2 ) ⋅ vˆ 2 cos ω2 t + ψ ω2 ⎤
⎣ ⎦ )
2
(
= K in ( jω1 ) ⋅ vˆ 12 cos {ω1 ± ω1} t + ψ ω1 ± ψ ω1 )
2
(
+ K in ( jω2 ) ⋅ vˆ 22 cos {ω2 ± ω2 } t + ψ ω2 ± ψ ω2 )
i ( jω1 ) K iin ( jω2 ) ⋅ v
+ K in (
ˆ 1 vˆ 2 cos {ω1 ± ω2 } t + ψ ω ± ψ ω
1 2 )
= K in ( jωa ) K in ( jωb ) v i2

Coefficients
1 −a1R
H1( jωa ) =
1 + jωaRC 1 + jωaRC
1 1 −a2R
H2 ( jωa , jωb ) =
1 + jωaRC 1 + jωbRC 1 + ( jωa + jωb ) RC
1 1 1 −a3R
H3 ( jωa , jωb , jωc ) =
1 + jωaRC 1 + jωbRC 1 + jωcRC 1 + ( jωa + jωb + jωc ) RC
Example 3
ij
[[Chun & Murmann,, JSSC 10/2006]]
Cj models the nonlinear capacitance of an electrostatic discharge (ESD)

protection device (e.g. a basic diode structure as shown to the right)

Junction Capacitance Model
C j0 C j0 1
Cj = M
= M M
⎛ VOQ + v o ⎞ ⎛ ψ0 + VOQ ⎞ ⎛ ψ0 + VOQ + v o ⎞
⎜1+ ⎟ ⎜ ⎟ ⎜ ⎟
⎝ ψ0 ⎠ ⎝ ψ0 ⎠ ⎝ ψ0 + VOQ Q ⎠
C j0
Using C jQ =
⎛ VOQ ⎞
M
1
(1 + x ) M
= 1 − Mx +
1
2
( )
M + M2 x 2 + ...
⎜1+ ⎟
⎝ ψ0 ⎠
M M + M2
VR = VOQ + ψ0 b1 = − b2 =
VR 2VR
we can write C jQ
Cj = = C jQ ⎡1 + b1v o + b2 v o2 + ...⎤
M ⎣ ⎦
⎛ vo ⎞
⎜1+ ⎟
⎝ VR ⎠
Circuit Analysis
dv o dv ⎡ dv 1 dv 2 1 dv 3 ⎤
ij = Cj = C jQ ⎡1 + b1v o + b2v o2 + ...⎤ o = C jQ ⎢ o + b1 o + b3 o ⎥
dt ⎣ ⎦ dt ⎢⎣ dt 2 dt 3 dt ⎥⎦
⎡ 2 3⎤
(
i = C jQ + CI ) dvdto + C jQ ⎢ 21 b1 dvdto + 31 b3 dvdto ⎥
⎣⎢ ⎦⎥
dv o ⎡ 1 dv 2 1 dv 3 ⎤
(
vi = v o + i ⋅ R = v o + R C jQ + CI ) dt
+ RC jQ ⎢ b1 o + b3 o ⎥
⎢⎣ 2 dt 3 dt ⎥⎦
d d d
vi = v o + RC0 v o + RC1 v o2 + RC2 v o3
dt dt dt
C0 = C jQ + CI
b
C1 = 1 C jQ = −
MC jQ b1
C2 = C jQ = −
M + M2 C jQ( )
2 2VR 3 6VR2

Volterra Series
We
W are looking
l ki ffor a Volterra
V lt series
i representation
t ti off the
th form
f
v o = H1 ( jωa ) v i + H2 ( jωa , jωb ) v i2 + H3 ( jωa , jωb , jωc ) v i3 + ...
The coefficients H1, H2 and H3 can be found by inserting the above

series into the nonlinear differential equation shown on the previous
slide and subsequently comparing the coefficients on the LHS and RHS
of the equation
vi = H1 ( jωa ) vi + H2 ( jωa , jωb ) vi2 + H3 ( jωa , jωb , jωc ) vi3
d⎡
+ RC0 H1 ( jωa ) vi + H2 ( jωa , jωb ) vi2 + H3 ( jωa , jωb , jωc ) vi3 ⎤
dt ⎣ ⎦
d⎡ 2
dt ⎣ ⎦
d⎡ 3
dt ⎣ ⎦
Coefficient Comparison (1)
First order
⎡ d⎤
1 vi = ⎢1 + RC0 ⎥ H1 ( jωa ) vi
⎣ dt ⎦
⎡ d⎤
1 = ⎢1 + RC0 ⎥ H1 ( jωa ) = ⎡⎣1 + RC0 jωa ⎤⎦ H1 ( jωa )
⎣ dt ⎦
1
∴ H1 ( jωa ) =
1 + RC0 jωa
This is just the linear transfer function as expected

Second order
⎡ d⎤ d 2
0 vi2 = ⎢1 + RC0 ⎥ H2 ( jωa , jωb ) vi2 + RC1 ⎡H1 ( jωa ) vi ⎤
⎣ dt ⎦ dt ⎣ ⎦
Simplify using the following rules
d
H2 ( jωa , jωb ) = ( jωa + jωb ) H2 ( jωa , jωb )
dt
2
⎡H1 ( jωa ) vi ⎤ = H1 ( jωa ) H1 ( jωb ) vi2
⎣ ⎦
d
⎡H1 ( jωa ) H1 ( jωb ) ⎤⎦ = ( jωa + jωb ) H1 ( jωa ) H1 ( jωb )
dt ⎣
0 = ⎡⎣1 + RC0 ( jωa + jωb ) ⎤⎦ H2 ( jωa , jωb ) + RC1 ( jωa + jωb ) H1 ( jωa ) H1 ( jωb )
−RC1 ( jωa + jωb ) H1 ( jωa ) H1 ( jωb )

H2 ( jωa , jωb ) =
1 + RC0 ( jωa + jωb )
∴ H2 ( jωa , jωb ) = −RC1 ( jωa + jωb ) H1 ( jωa ) H1 ( jωb ) H1 ( jωa + jωb )
f ω→0; this makes intuitive sense

H2 becomes zero for

Third order
⎡ d⎤
0 vi3 = ⎢1 + RC0 ⎥ H3 ( jωa , jωb , jωc ) vi3
⎣ dt ⎦
+ RC1
d⎡
dt ⎣
(
2 H1 ( jωa ) vi ) (H ( jω , jω ) v )⎤⎦
2 a b
2
i
Second-order
Interaction Term
d⎡ 3
+ RC2 H1 ( jωa ) vi ⎤
dt ⎣ ⎦
Simplifying and neglecting the second-order interaction term yields
∴ H3 ( jωa , jωb , jωc ) = −RC2 ( jωa + jωb + jωc ) H1 ( jωa ) H1 ( jωb ) H1 ( jωc )
⋅ H1 ( jωa + jωb + jωc )
Harmonic Distortion Expressions (1)
2
RC1 ( 2jω) ⎡⎣H1 ( jω) ⎤⎦ H1 ( 2jω)
1 H2 ( jω, jω) 1
HD2 = vˆ i = vˆ i = ωRC1 H1 ( jω) H1 ( 2jω) vˆ i
2 H1 ( jω) 2 H1 ( jω)
1 ⎛ v̂ ⎞
∴ HD2 = MωRC jQ H1 ( jω) H1 ( 2jω) ⎜ i ⎟
2 ⎜ VR ⎟
⎝ ⎠
HD2 improves for

– Lower swing (vi/VR)
– Lower frequency
– Lower drive resistance (R)
– Smaller capacitive nonlinearity (M→0) and smaller CjQ
Adding extra linear capacitance (CI) will lower the corner frequency of H1
– Assuming that we cannot tolerate much signal attenuation, this won’t
help reduce the distortion all that much in the useable frequency range

Harmonic Distortion Expressions (2)
RC2 ( 3jω) (H1 ( jω) ) H1 ( 3jω)

3
1 H3 ( jω, jω, jω) 2 1
HD3 = vˆ i = vˆ i2
4 H1 ( jω) 4 H1 ( jω)
3 2
= ωRC2 H1 ( jω) H1 ( 3jω) vˆ i2
4
2
⎛ v̂ ⎞
1
( )
∴ HD3 = M + M2 ωRC jQ H1 ( jω) H1 ( 3jω) ⎜ i ⎟
8 ⎜ VR ⎟
⎝ ⎠
HD3 behaves similar to HD2

– The distortion depends on similar quantities and cannot be improved
by adding additional linear capacitance (CI)
HD3 is often more critical than HD2, since the latter can be improved
significantly by employing a differential circuit topology
Plot
v̂ i = 0.5V
v 0 5V
R = 25Ω
CI = 0
C jQ = 1pF
M = 0.3
03
VR = VOQ + ψ0 = 2.2V

Example 4
An
A RC circuit
i it with
ith a lilinear capacitor,
it b butt nonlinear
li resistor
i t
The circuit below implements a track-and-hold circuit used in switched
capacitor circuits (filters, A/D converters, etc.)
– More in EE315A,B
The MOSFET is used as a switch and operates in the triode region,
exhibiting nonlinear resistive behavior
[W. Yu, IEEE TCAS II, 2/1999]

K 2
ID ≅ K ( VGS − Vt ) VDS − VDS
2
Analysis (1)
K 2
ID ≅ K ( VGS − Vt ) VDS − VDS
2
dVo K 2
C = K ( ϕ − Vo − Vt )( Vi − Vo ) − ( Vi − Vo )
dt 2
Solving for the coefficients of the Volterra series linking vo and vi, and
evaluating HD2 and HD3 yields
1 ⎛ v̂ i ⎞
HD2 = ωRC ⎜ ⎟
2 ⎝ VGS − Vt ⎠
2
1 ⎛ v̂ i ⎞
HD3 = ωRC ⎜ ⎟
4 ⎝ VGS − Vt ⎠
where VGS is the quiescent point gate-source voltage and R is the

quiescent point resistance of the MOSFET, i.e. K[VGS-Vt]-1

Analysis (2)
For low distortion

– Make signal amplitude much smaller than VGS-Vt
• Low swing, which is usually undesired
– Make 1/RC much larger than 2π·fin
• Small C or big MOSFET, which is usually undesired
Example HD3 calculation
1 1 ⎫
ω= ⎪
10 RC
⎪
vˆ i = 0.2V
0 2V ⎪
⎪
V ⎪⎪ 1 1 ⎛ 0.2 ⎞
2
VOQ = VIQ = DD = 0.9V ⎬ HD3 = = −46dB
2 ⎪ 4 10 ⎜⎝ 0.45 ⎟⎠
VGS − Vt = VDD − VOQ − Vt ⎪
⎪
⎪
= 1.8V − 0.9V − 0.4V = 0.45V ⎪
⎪⎭
Example 5
[Terrovitis & Meyer, JSSC 10/2000]

Additional Topics in Distortion Analysis
Covered in EE314
– RF-centric metrics
• Intercept points
• 1-dB gain compression point
Other
– Nonlinearities in passive components
– Distortion cancelation techniques
– Cascading nonlinearities
– Series reversion
– Distortion in clipped or amplitude limiting waveforms
• E.g. in oscillators

References (1)
D. O. Pederson and K. Mayaram, Analog Integrated Circuits for

Communication, Springer, 1991
P. Wambacq and W. M. C. Sansen, Distortion Analysis of Analog
Integrated Circuits, Springer, 1998
Hurst, Lewis, Gray
y & Meyer,
y 5th edition, pp
pp. 355-359
– Distortion analysis of a source follower
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill,
2000, Chapter 13
W. Sansen, “Distortion in elementary transistor circuits,” IEEE Trans.
Circuits and Systems II, vol. 46, pp. 315-325, March 1999
P
P. Wambacq,
Wambacq G. G Gielen,
Gielen and PP. Kinget,
Kinget “High-Frequency
“High Freq enc Distortion
Analysis of Analog Integrated Circuits,” IEEE Trans. Circuits and Syst. II,
pp. 335-345, March 1999
References (2)
W
W. Rugh,
R h Nonlinear
N li S
System
t Theory,
Th
http://rfic.eecs.berkeley.edu/ee242/pdf/volterra_book.pdf
R. G. Meyer and M. L. Stephens, "Distortion in variable-capacitance
di d " IEEE J.
diodes," J Solid-State
S lid St t Circuits,
Ci it pp. 47-54,
47 54 F Feb.
b 1975
K. L. Fong and R.G. Meyer, "High-frequency nonlinearity analysis of
common-emitter and differential-pair transconductance stages," IEEE J.
Solid State Circuits,
Solid-State Circuits pp
pp.548-555,
548 555 Apr
Apr. 1998
M. T. Terrovitis and R. G. Meyer, "Intermodulation distortion in current-
commutating CMOS mixers," IEEE J. Solid-State Circuits, pp.1461-
1473 Oct
1473, Oct. 2000
J. Chun and B. Murmann, "Analysis and Measurement of Signal
Distortion due to ESD Protection Circuits," IEEE J. Solid-State Circuits,
pp 2354-2358
pp. 2354-2358, Oct
Oct. 2006
W. Yu, S. Sen and B. H. Leung, "Distortion analysis of MOS track-and-
hold sampling mixers using time-varying Volterra series," IEEE Trans.
Circuits and Syst
Syst. II
II, pp
pp. 101-113
101 113, Feb
Feb. 1999

Ch t 10
Chapter
Operational Amplifiers and Output Stages
B. Murmann
Stanford University
Reading Material: Sections 5.2, 5.5, 6.8, 7.4, 9.4.5
http://www nxp com/documents/data sheet/NE5234 SA5234 pdf

http://www.nxp.com/documents/data_sheet/NE5234_SA5234.pdf

Architecture
Provides differential Provides Provides high

input with large additional current drive
common mode d voltage
lt gain
i capability
bilit
range
Output can
Provides some (approximately)
g g
voltage gain,, g rail-to-rail
swing
approximately
independent of
common mode

Basic PNP Differential Pair Input Stage
Circuit works for input common mode

down to VEE (0V), as long as
VBE > VCE(sat ) + VR1

VR1 < VBE − VCE(sat ) ≅ 0.8V
0 8V − 0 2V = 0
0.2V 0.6V
6V
This limits the gain we can extract from

this stage
IBIAS V 600mV
gm1R1 = R1 = R1 = = 23
2VT VT 26mV
26 V
Text, p. 449
PNP Folded Cascode Input Stage
Circuit still works for input

common mode down to VEE
(0V), as before
But, the low frequency voltage
gain is much larger
g g
v od R3
= gm1 R
v id 1 o
R3 +
gm
Ro ≅ ro6 (1 + gm6R6 ) ro3 (1 + gm3R3 )

NE5234 Input Stage
~0.9V
Provides rail-to rail common-mode input range by combining the

currents from a PNP and NPN pair
The NPN pair “steals” current from the PNP pair at node X whenever the
input common mode is greater than |VBE|
– Total Gm is approximately constant
Second Stage
0.5V 0.5V
0.5V
~0.9V
+ 0.4V -

Common Mode Operating Point of Stage 1 Output
Basic Emitter Follower (“Class-A”) Output Stage
Issues
– Output
p voltageg cannot ggo
higher than VCC – VBE
– Need large quiescent current
IQ to provide good current
sinking capability
– IQ flows even if no signal is
present, i.e. Io=0

Output Stage Nomenclature
Cl
Class-A
A
– Output devices conduct for entire cycle of output sine wave
Class-B
– Output devices conduct for ≅50% of sine wave cycle
Class-AB
– Output
p devices conduct for >50%,, but <100% of cycle
y
Class-A Class-B Class-AB
Class-AB Emitter Follower Output Stage
Small quiescent current, but

large drive capability
Remaining issue
– Output voltage swing is
severely limited

Class-AB Common Emitter Output Stage
Q1 and Q2 are large

devices
Want to set the quiescent
point such that IC1 and IC2
are small when no signal is
applied
Analysis
Assuming IC3 = IC4 = IREF by symmetry, we can write
VBE6 + VBE8 = VBE4 + VBE2
IREF IREF IREF IC2

=
Is6 Is8 Is4 Is2
Is2 Is4
IC2 = IREF
Is6 Is8
y IREF and emitter area ratios ((Is ∝ AE)

Quiescent current is set by
The same principle applies to CMOS implementations
– Original paper by Monticelli, JSSC 12/1986

CMOS Version
[Hogervorst, JSSC 12/1994]
Simulated Currents (Vo=0)
Output transistors
never turn off
Quiescent current set
Iout by transistor ratios
Current [A]
ID(M26)
Large drive capability
ID(M25)
Iin1=Iin2 [A]

NE 5234 Output Stage
Feedback through Q39-40 ensures that both transistors remain on at

extreme output swings
Simplified AC Schematic of Complete OpAmp
Nested Miller
Compensation

Compensation Issue (1)
The designer of a general purpose OpAmp knows nothing about the

feedback network that the user will connect around the amplifier
Therefore, general purpose OpAmps are typically compensated for the
"worst case", i.e. unity feedback configuration
This tends to be wasteful, since much less compensation
p mayy be
needed for other feedback configurations
– To overcome this issue, some general purpose OpAmps provide an
external pin to let the user decide on the required compensation
capacitor
it
Compensation Issue (2)
Wasted BW

Slewing
P
Previous
i analyses
l h
have been
b concernedd with
ith th
the small-signal
ll i lbbehavior
h i
of feedback amplifiers at high frequencies
Sometimes the behavior with large input signals (either step inputs or
sinusoidal
i id l signals)
i l ) iis also
l off interest
i t t
– See e.g. switched capacitor circuits in EE315A
Example using NE5234
Output Response – Expected versus Actual

Investigation
General Analysis
Slew Rate

“Internal” Amplifiers (1)
Most amplifiers used in large

systems-on-chip (SoC) are not as
complex as a typical general
purpose OpAmps
– Typically, no output stage is
needed, since the loads are
either small and/or purely
capacitive
Operational Transconductance
Amplifier (OTA) = OpAmp minus
Output Stage
More in EE315A (see also text,
section 6.1.7, and chapter 12) Mehta et al., "A 1.9GHz Single-Chip
CMOS PHS Cellphone," ISSCC 2006.
“Internal” Amplifiers (2)

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EE214 Advanced Analog Integrated Circuit Design: - Winter 2011 - Boris Murmann Stanford University Murmann@stanford - Edu

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EE214

Advanced Analog Integrated Circuit Design

Analog Circuit Sequence

Fundamentals for upper- Analysis and design

EE114 — EE214 — EE315A — VLSI

B. Murmann EE214 Winter 2010-11 – Chapter 1 2

EE101A,B EE114 EE214 EE314

B. Murmann EE214 Winter 2010-11 – Chapter 1 3

Electronic Noise Distortion

B. Murmann EE214 Winter 2010-11 – Chapter 1 4

B. Murmann EE214 Winter 2010-11 – Chapter 1 5

Significance of Electronic Noise (2)

Example: Noisy image

B. Murmann EE214 Winter 2010-11 – Chapter 1 6

B. Murmann EE214 Winter 2010-11 – Chapter 1 7

 All electronic circuits exhibit some level of nonlinear behavior

B. Murmann EE214 Winter 2010-11 – Chapter 1 8

 For a two-tone input, the nonlinear terms in a circuit’s transfer function

Example: Two interferer tones create an

B. Murmann EE214 Winter 2010-11 – Chapter 1 9

Noise and Distortion Analysis in EE214

 Leave application-specific examples for later

B. Murmann EE214 Winter 2010-11 – Chapter 1 10

MOSFET Bipolar Junction Transistor (BJT)

B. Murmann EE214 Winter 2010-11 – Chapter 1 11

Bipolar vs. CMOS (1)

 Advantages of bipolar transistors

 Disadvantages of bipolar transistors

B. Murmann EE214 Winter 2010-11 – Chapter 1 12

A.J. Joseph, et al., "Status and

• CMOS tends to require finer lithography to achieve same speed as

B. Murmann EE214 Winter 2010-11 – Chapter 1 13

Example that Leverages High-Speed BJTs:

B. Murmann EE214 Winter 2010-11 – Chapter 1 14

• 120-GHz fT / 100GHz fmax

B. Murmann EE214 Winter 2010-11 – Chapter 1 15

B. Murmann EE214 Winter 2010-11 – Chapter 1 16

Mehta et al., "A 1.9GHz Single-Chip

B. Murmann EE214 Winter 2010-11 – Chapter 1 17

45nm CMOS (Intel)

B. Murmann EE214 Winter 2010-11 – Chapter 1 18

Multi-Gate / FinFET Nanowire

Source Drain [Prof. P. Wong] Ferromagnetic

Thoughts on Device Technology

 In the future, innovative circuit designers must embrace “whichever”

 In EE214, we will use bipolar and MOS technology to illustrate the

B. Murmann EE214 Winter 2010-11 – Chapter 1 20

B. Murmann EE214 Winter 2010-11 – Chapter 1 21

Root Locus Techniques

B. Murmann EE214 Winter 2010-11 – Chapter 1 22

 BJT & short channel MOS device models

B. Murmann EE214 Winter 2010-11 – Chapter 1 23

Summary of Learning Goals

 Understand device behavior and models for transistors available in

B. Murmann EE214 Winter 2010-11 – Chapter 1 24

B. Murmann EE214 Winter 2010-11 – Chapter 1 25

Text and Prerequisites

B. Murmann EE214 Winter 2010-11 – Chapter 1 26

B. Murmann EE214 Winter 2010-11 – Chapter 1 27

 Please remember you are bound by the honor code

B. Murmann EE214 Winter 2010-11 – Chapter 1 28

W. Brinkman, D. Haggan, and W. Troutman, “A history of the invention

All electronic circuits exhibit some level of nonlinear behavior

For a two-tone input, the nonlinear terms in a circuit’s transfer function

Leave application-specific examples for later

Advantages of bipolar transistors

Disadvantages of bipolar transistors

In the future, innovative circuit designers must embrace “whichever”

In EE214, we will use bipolar and MOS technology to illustrate the

BJT & short channel MOS device models

Understand device behavior and models for transistors available in

Please remember you are bound by the honor code

In order to understand the operation principle of a BJT, we will look at

The treatment in the following slides is meant to be short and qualitative

Depletion region narrows, diffusion processes are no longer balanced by

Since there must be charge neutrality in the

In each region, there are now two types of currents

Reverse bias increases the

Make the p-region of the pn+ junction very thin

Primary current is due to electrons captured by the collector

In the EE214 technology,

Much larger than the intrinsic gain of typical MOSFET devices

Complete picture of BJT operating regions

Base-Collector junction is forward biased

Region III (high current density)

Region I (low current density)

τF is called the base transit time (in forward direction)