A S-VHS compatible 1/3” 720(H) * 588(V) FT-CCD

with low dark current by surface pinning

Jan T. Rosiers, Herman L. Peek, Agnes C. Kleimann, Noortje J. Daemen,
Edwin Roks, Arjen C;. van der Sijde, RenC M . Jansen, Peter Opmeer

Philips Research Laboratories Eindhoven - WAG-1

P.O. Box 80 000, 5600 dA. Eindhoven, The Netherlands

ABSTRACT A cross-section along the transport direction is shown in

Fig.2.
A CCD imager for a low-cost compact S-VHS camcorder
is presented. With the introduction in a frame-transfer CCD
of mosaic color filters, fast frame shift, on-chip drivers and
surface pinning, the optical format for S-VHS resolution coulld
d’e’eCtr’C oxide
be reduced from 2/3” to 1/3” without sacrificing performance.
/;1 T;\ R
XB /I XA U XB 11 XA
DN
~ - -
INTRODUCTION OP

The trend in consumer camcorders is clearly towards mare

compact cameras with increasing resolution and improved low
light-level imaging. The FT-CCD imager presented here was
especially designed for such an application: the required phys- Fig.2.Cross section of image cell along transport direction
ical volume in the camcorder was reduced by using a snlitll
CCD (1/3” image diagonal format), by a low smear operation
without mechanical shutter through fast frame shift and by
A conventional n-channel CCD in a profiled p-well on a n-
the use of on-chip drivers. T h e combination of mosaic color
substrate is used for vertical antiblooming [l]. The CCD pro-
filters with an FT-CCD and a significant reduction of dark
files are optimised such that electronic shutter operation, used
current by surface pinning allow high resolution color imag,es
for variable exposure times, is achieved by setting all image
with low noise even at low illumination levels.
electrodes t o the low clock level, thus flushing the collected
electrons to the n-substrate (called ”charge reset”).
IMAGE PIXEL

The basic image pixel is a four phase cell constructed of

two polysilicon layers, using two short poly-1 (XA) and two FAST FRAME SHIFT
long poly-2 (XB) electrodes per pixel. A perspective view of
Since no mechanical shutter can be used in a compact
the image pixel is given in Fig.].
camcorder, the frame-shift frequency of an FT-CCD has to
be increased to limit smear. This requires a reduction of
the RC time constants in the CCD electrode network. Ca-
pacitances were lowered by significantly reducing the overlap
of the polysilicon electrodes. The resistances of the CCD
(XA) 2A
network were drastically reduced by using vertical aluminum
straps (IN), 1.2 pm wide, over the light-insensitive pt chan-
nel stops (SP). Thus the frame-shift frequency could be in-
creased from 1 to 15 M H z without any loss in performance.
80dB smear suppression is obtained, comparable to 1/3” S-
VHS IL-CCD’s [ 2 , 3 ] . (Smear is defined as the spurious signal
collected during frame shift, from a highlight l/lOth of the
image height.)
Note that with decreasing image diagonals, an FT-CCD can
achieve lower smear values, since the RC time constants are
reduced. In IL-CCD’s, reducing the CCD size tends to in-
crease the smear since the IL-CCD’s become smaller, and
thus more susceptible to direct collection of light-generated
electrons.
Fig.l.Perspective view of image cell

!5.1.1
0-7803-0817-4192 $3.00 0 1992 IEEE JEDM 92-97

Authorized licensed use limited to: Technion Israel School of Technology. Downloaded on December 28, 2009 at 12:48 from IEEE Xplore. Restrictions apply.
 DESIGN OF STORAGE SECTION, SERIAL XA oxide XA
1

REGISTER AND OUTPUT AMPLIFIER 1

T h e storage cell is almost identical to the image pixel.
T h e two-phase readout register was designed using only the \ DP /
same two poly layers as used in the image cell, as shown in
Fig.3. T h e CS mask allows direct contacts from XB to XA
Nsub
by etching part of the oxide above XA.
gate cs Fig.5. Layout of one inverter stage
dielectric contact oxide
driver t y p e CMOS inverters
switching voltage (VDD=lOV) 2.8V
power supply voltage VDD 8 V t o 12V

rise time t r (InF load) 35 11s

DP fall time t f (1nF load) 40 11s
-~ ~ __ ~~
charge reset time (VDR) 10 ps
Nsub number of poly layers 2
-~~- ~.
~~

number of metal layers 2

Fig.3.Cros.s section of two-phase serial register area 1 driver 2.4 1mn2

Also the double source-follower output amplifier was con-

Table 1 .Summary of on-chip driver characteristics
structed with only these poly layers.
MOSAIC COLOR FILTERS O N FT-CCD’S

ON-CHIP DRIVERS Previously reported FT-CCD’s use RGR or (:y-Gr-Ye

To reduce the number of external components required
to operate the CCD, 15 MHz CMOS-drivers for the image
and storage electrodes were included on-chip. They are po-
sitioned above the image- and below the storage section. A
schematic diagram showing the principle of one image driver
is given in Fig.4.
VDH VDR
stripe color filters for color imaging. To obtain S-VHS resolu-
tion, approx. 1200 pixels per line are required when using on
chip stripe filters [l]. With mosaic filters, S-VHS resolxtion
is obtained with only 720 pixels [3].
Color filters were deposited in a mosaic pattern as shown in
Fig.6. Cyan (Cy), yellow (Ye) and magenta (Mg) filters were
evaporated and patterned using a lift-off process. Green fil-
tering is achieved by overlapping cyan and yellow filters. T h e
gaps between the filters lie either above the light-insensitive
metal straps, or above the narrow XA gates. T h e optical sen-
sitivity of these gates is reduced significantly with o u r vertical
n-p-n structure by setting both of them to the low clock volt-
age during integration (i.e. approaching charge-reset condi-
tion), thus limiting the contribution of ”white”, non-filtered
light on the sensor to obtain good color rendition.

VDL IN

Fig.4. Schematic diagram of one image driver

CMOS inverters with increasing transistor width gradually

drive increasing capacitive loads. T h e separate power supply
VDR is used for electronic shuttering: when setting VDR to
GND, the output of the driver is switched to low level, in-
discriminate of the logical input I N . This provides a simple XA
method to implement electronic shutter by charge reset. T h e
layout of one inverter stage is shown in Fig.5.
One extra p-well implant DP2 is required in the CCD process
to obtain the correct threshold voltage for the nMOS transis-
tors. The input signal is standard logic, the supply voltage
can be varied from 8V to 12V. One driver occupies approx. Fig.6. Layout of color filters
2.4 mm2. T h e characteristics are summarised in Table 1.

5.1.2
98-1EDM 92

Authorized licensed use limited to: Technion Israel School of Technology. Downloaded on December 28, 2009 at 12:48 from IEEE Xplore. Restrictions apply.
 REDUCTION OF DARK CURRENT BY Vertical anti-blooming with electronic shutter is not compro-
SURFACE PINNING mised and charge-transfer efficiency is not degraded. How-
ever, charge-storage capacity is reduced from 70 000 electrons
TOimprove the performance a t low light levels, the mal- per pixel to 30 000 in AGP mode. Blue sensitivity is not
jor source of noise, FPN (fixed-pattern noise) from surface- reduced by the shallow layer of holes at the interface, but is
generated dark current had to be reduced. increased since the 2-phase structure allows larger "windows"
A way to completely suppress interface state generation is to (image area's not covered with polysilicon) in the image pixel
invert the surface, i.e. have a layer of holes a t the Si-Si02 (Fig.11).
interface during integration [4]. This was introduced in the
photodiodes of consumer IL-CCD's [5] and in "scientific" full-
0
frame CCD's [6]. DN DP Nsub 1
However, introduction in a consumer FT-CCD of an image
cell with a completely inverted surface is not straightforward
since the function of integration and transport are combined
into the same cell, and the other properties of the pixel (anti-
blooiiiing protection, electronic shutter, efficient transport)
may not be compromised when modifying the pixel struc-
ture for pinned operation. Thus, untill now, only the charge-
pumping technique [7] was used in most FT-CCD's: the image
electrodes are pulsed consecutively to a low voltage to invert
the surface. However, this only yields a partial reduction in
0 2 4 6 8 1 0 1 2
surface dark current: for practical reasons, charge-pumping
is limited to the line blanking periods; and a t higher tem- Depth in SI(prn)
peratures (4OoC), the time constant for the recovery rate of Fig.8. Potential profiles for AGP operation
interface-state generation becomes significantly shorter than under XA (curve 1) and XB (curve 2 )
the line time.
We have achieved a CCD pixel for an FT-CCD that has all 1500
gates pinned (AGP) during the whole integration time with-
out sacrificing other properties such as vertical anti-blooming, N
-

electronic reset and efficient charge transport. Only a small $ 1000

modification to the existing design was required, as shown in -
-
Q

C
Fig.7. Since all gates are set low for pinning, an addition,d
implant DN2 is introduced self-aligned on XA under the XB
gates to keep the charge packets separated. This also allows *
0
500

2-phase operation. T h e resulting potential profiles are shown 0"

in Fig.8.
0
gate CS 7 8 9 10 11 12 13 14
dieleclric contact oxide
Pinning voltage VP (V)

Fig.9. Dark current vs. pinning voltage

Nsub

Fig.7. Cross section of AGP cell along transport direction

Pinning is achieved with the gates 9V below the externallly

applied S P voltage. T h e dark current a t 60°C is reduced from
1000 pA/cm2 without pinning to 50 pA/cm2 in AGP mode.
Dark current vs. pinning voltage V P (offset between exter-
nally applied S P voltage and image electrode voltage) a t 80°C
is shown in Fig.9: in AGP mode, only bulk dark current Gom
the top 2 pm Si is collected. Dark current vs. temperature is
shown in Fig.10. 40 60 80 100 120
Note that the dark current accumulated during frame shift Temperature (OC)
(when the image section is not pinned), and in the storage
section does not contribute to the FPN since it is averaged
Fig.10. Dark current vs. temperature
over 295 lines.

5.1.3

IEDM 92-99
 CCD type Fiame transfer, 113”
Nuniber of lines 588 (2:l interlacel
Number of active pixels/line 720
Pixel size 6.9 p m (H) * 12.6pin ( V )
Clup size 5.7 (H) mni * 10.6 ( V ) niin
Minimum features 0.8pm

Frame shift frequency 15 MHz

Readout frequency 13.5 MHz
Smear suppression 80 dB
Maximum charge-capacity
conventional 70 000 electroils
400 500 600 700 800 AGP 30 000 electroils
Dark current (6OOC)
Wavelength (nm)
conventional 1000 pA/cm2
AGP 5 0 pA/an2

Fig.11. Quantum efficiency vs. wavelength Image and storage clock swing 1ov
for conventional and AGP versions Serial clock swing 5v
Color filters Cy-Gr-YeMg inosaic
TECHNOLOGY Minimum exposure time 1/4000 s
Outamp sensitivity 1 2 pV/electron
Minimum dimensions in sensor fabrication are 0.8 p m . Outamp noise (5 MHz B W ) 15 electroils RMS
A conventional vertical n-p-n structure to achieve blooming
protection is used. As already mentioned, only two layers of Table 2. 1/3” FT CCD specification and performance
polysilicon (0.3 pm, 25 O / o ) are needed. A first aluminum
layer (0.5 pm, 0.05 O / o ) is used for the vertical straps. T h e
second layer (1.0 pm, 0.025 O/O) is used for all other inter- ACKNOWLEDGEMENTS
connections and for the light screen over the storage area.
The ”pinning” version only needs one additional self-aligned T h e authors would like to thank their colleagues in the
implant DN2. T h e sensor d a t a are summarised in Table 2. CCD group a t the Philips Research Laboratories for their
Fig.12 shows a conventional 4-phase device with on-chip ini- valuable contributions. Especially the assistance of M . Steke-
age and storage drivers. lenburg with the on-chip drivers is acknowledged.

m a g e drivers -- I REFERENCES

[l]. J. Bosiers et al., A 2/3” 1188(H) * 484(V) frame-transfer

CCD for ESP and Movie, 1982 Intl. Electron Dev. Conf.,
image section + IEDM’88 Digest pp.70-73.
[Z]. H. Akimoto a t al., ” A 1/3-in 410 000-pixel CCD im-
age sensor with feedback field-plate amplifier,” IEEE J . Solid
State Circuits, , vo1.38 no.12 pp.1907-1914 (1991).
[3]. C. Mizouchi et al., ”1/3-inch 410 000 pixel IT-CXD im-
storage section -+
age sensor, Proc. In tl. Television Engineering Conference
1992 (ITEC’92), pp. 453-454.
[4]. N.S.Saks, ” A technique for suppressing dark current gen-
I
erated by interface states in buried channel CCD imagers”,
storage drivers -+
IEEE Electron Dev. Lett., vol.1 no.7, 1980
[5]. N. Teranishi et al., ” N o image lag photodiode structure
Fig.12. Chip photo in the interline CCD image sensor”, 1982 Jntl. Electron Dev.
Conf., IEDM’82 Digest pp.324-327.
CONCLUSIONS [6]. J. Janesick, T. Elliot, G. Fraschetti, S. Collins, ”Charge-
coupled device pinning technologies”, SPIE Conf on Optical
A 1/3” FT-CXD image sensor with 15 MHz frame shift, Sensors and Electronic Photography, Los Angeles, CA, 1989,
on chip drivers and significantly reduced dark current through Proc. SPIE vol. 1071-15.
surface pinning was presented. S-VHS compatible color imag- [7]. B. Burke and S. Ciajar, ”Dynamic Suppression of interface-
ing is achieved with 720 pixels/line by using mosaic color fil- state dark current in buried-channel CCD’s”, JEEE Trans.
ters. Optimisation of the pixel design in pinned mode is being Electr. Dev., vo1.38 no.2 pp.285-290 (1991).
carried out to increase the charge storage capacity.

5.1.4
100-IEDM 92

Authorized licensed use limited to: Technion Israel School of Technology. Downloaded on December 28, 2009 at 12:48 from IEEE Xplore. Restrictions apply.