STA505

40V 3.5A QUAD POWER HALF BRIDGE

s

MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200m RdsON COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION

MULTIPOWER BCD TECHNOLOGY

s s s s

PowerSO36 ORDERING NUMBER: STA505

DESCRIPTION STA505 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability. The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency AUDIO APPLICATION CIRCUIT
VCC1A IN1A IN1A +3.3V IBIAS CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 REGULATORS 7 VCC2A C32 1F OUT2A OUT2A 6 GND2A PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 C30 1F OUT1A OUT1A 14 GND1A C52 330pF +VCC C55 1000F

(DDX) amplifier capable to deliver 50 + 50W @ THD = 10% at Vcc 30V output power on 8 load and 80W @ THD = 10% at Vcc 36V on 8 load in single BTL configuration. The input pins have threshold proportional to Ibias pin voltage.

L18 22H C20 100nF R98 6 C99 100nF C23 470nF C101 100nF

12

VCC1B C31 1F OUT1B OUT1B GND1B R63 20 R100 6 C21 100nF L19 22H

11 10

TH_WAR IN1B

L113 22H C110 100nF C109 330pF R103 6 R104 20

VCC2B C33 1F OUT2B OUT2B

R102 6 C111 100nF

3 2

C107 100nF C108 470nF C106 100nF

IN2B

IN2B GNDSUB

32 M14

L112 22H

GND2B
D00AU1148B

December 2002

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STA505
PIN FUNCTION
N 1 35 ; 36 15 12 7 4 14 13 6 5 16 ; 17 10 ; 11 8;9 2;3 29 30 31 32 21 ; 22 33 ; 34 25 26 27 24 28 19 23 18 20 Pin GND-SUB Vcc Sign Vcc1A Vcc1B Vcc2A Vcc2B GND1A GND1B GND2A GND2B OUT1A OUT1B OUT2A OUT2B IN1A IN1B IN2A IN2B Vdd Vss PWRDN TRI-STATE FAULT CONFIG TH-WAR GND-clean IBIAS NC GND-Reg Substrate ground Signal Positive supply Positive supply Positive supply Positive supply Positive supply Negative Supply Negative Supply Negative Supply Negative Supply Output half bridge 1A Output half bridge 1B Output half bridge 2A Output half bridge 2B Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5V Regulator referred to ground 5V Regulator referred to +Vcc Stand-by pin Hi-Z pin Fault pin advisor Configuration pin Thermal warning advisor Logical ground High logical state setting voltage Not connected Ground for regulator Vdd Description

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STA505
FUNCTIONAL PIN STATUS
PIN NAME FAULT FAULT * TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR* CONFIG CONFIG** Logical value 0 1 0 1 0 1 0 1 0 1 IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C Normal operation Normal Operation OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)

* : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. **: To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)

PIN CONNECTION

VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG IBIAS VDD VDD GND-Reg GND-Clean

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.

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STA505

ABSOLUTE MAXIMUM RATINGS

Symbol VCE Vmax Top Tstg, Tj Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins 23 to 32 Operating Temperature Range Storage and Junction Temperature Value 40 5.5 0 to 70 -40 to 150 Unit V V C C

ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 30V; T = 25C unless otherwise specified)
Symbol Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON Matching Power Nchannel RdsON Matching Low current Dead Time (static) Test conditions Id=1A;T=25C Vcc=35v;T=25C Id=1A; T=25C Id=1A; T=25C see test circuit no.1; T=25C; see fig. 1 95 95 10 20 50 100 100 25 25 10 36 Ibias/2 +300mV Ibias/2 -300mV Pin voltage=Ibias Pin voltage = 0.3V Ibias = 3.3V Ibias = 3.3V Ibias = 3.3V 0.8 1.7 1 1 35 Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns ns V V V A A A V V

High current Dead Time (dinamic) L=22H; C = 470nF; Rl = 8 Id=3.5A; T=25C; see fig. 3 Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage Low level input voltage Hi level Input current Low level input current Hi level PWRDN pin input current Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Resistive load; Vcc=30V;T=25C Resistive load; Vcc=30V;T=25C Resistive load; as fig.1;T=25C Resistive load; as fig. 1;T=25C

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STA505
ELECTRICAL CHARACTERISTCS (continued)
Symbol Parameter Supply current from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate Supply current from Vcc in operation (both channel switching) Isc (short circuit current limit) (note 2) Test conditions PWRDN = 0 Min. Typ. Max. 3 Unit mA

Vpin = 3.3V Vcc=30V; Tri-state=0; T=25C Vcc=30V; Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; Vcc = 30V;T = 25C 3.5

1 22 80

mA mA mA

6 7

A V

Undervoltage protection threshold T = 25C Output minimum pulse width No Load 70

150

ns

Notes: 1. The following table explains the VL, VH variation with Ibias

Ibias 2.7 3.3 5

VLmin 0.7 0.8 0.85

VHmax 1.5 1.7 1.85

Unit V V V

Note 2: If used in single BTL configuration, the device may be not short circuit protected

LOGIC TRUTH TABLE (see fig. 2)

TRI-STATE 0 1 1 1 1 INxA x 0 0 1 1 INxB x 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used

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STA505
Figure 1. Test Circuit.

Figure 2.
+VCC

Q1 INxA OUTxA

Q2 OUTxB INxB

Q3

Q4

GND

D00AU1134

Figure 3.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B

DTout(A) M58 Q1 OUTxA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTxB M64

DTin(A) INxA

DTin(B) INxB

Iout=3.5A M57 Q3

Iout=3.5A Q4 M63

C71 470nF

Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure

D00AU1162

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STA505
Figure 4. Typical Single BTL Configuration to obtain 80W @ THD 10%, R L = 8, VCC = 36V (note 1)
IBIAS 100nF

+3.3V

23

18 17 16 11 10

N.C. 22H OUT1A OUT1A OUT1B OUT1B OUT2A 22 1/2W 6.2 1/2W 6.2 1/2W

GND-Clean GND-Reg

19 20

100nF FILM 100nF X7R 470nF FILM 100nF X7R 100nF FILM 22H

10K

100nF X7R

VDD VDD CONFIG

21 22 24 28 25 27 26

9 8

OUT2A OUT2B

330pF

TH_WAR nPWRDN 10K

TH_WAR PWRDN FAULT TRI-STATE 100nF IN1A IN1B IN2A IN2B VSS VSS 100nF X7R 100nF X7R Add. VCCSIGN VCCSIGN GNDSUB

3 2

OUT2B

15

VCC1A 1F X7R

+36V 2200F 63V

29 30 31 32 33 34

12

VCC1B VCC2A

IN1A

+36V 1F X7R

IN1B

4 14

VCC2B GND1A GND1B

35

13 GND2A

36 1

6 GND2B 5
D01AU1274

Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board".

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STA505

DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s

MIN. 3.25 0.8

mm TYP.

MAX. 3.5 3.3 1 0.075 0.38 0.32 16 9.8

MIN. 0.128 0.031

inch TYP.

MAX. 0.138 0.13 0.039 0.003 0.015 0.012 0.630 0.38

OUTLINE AND MECHANICAL DATA

0.2 0 0.22 0.23 15.8 9.4 1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 0 15.9 0.61 1.1 1.1 0.031 10 (max) 8 (max) 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114 0 0.008 0.009 0.622 0.37

0.008

0.039 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.003 0.625 0.043 0.043

PowerSO36 (SLUG UP)

(1) D and E1 do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006) (2) No intrusion allowed inwards the leads.

7183931

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STA505

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