ALL ABOUT DIGITAL

PRODUCTS.
BY

Ramki .
INTRODUCTION:
Two popular technologies are widely used to produce Ics namely TTL (Transistor-Transistor Logic) & CMOS ( Complementary Metal Oxide Semiconductor).Cmos has

now became the most opted for new circuits as it can pack more circuitry into a given chip area. The majority of the computers circuitry is comprised of the digital logic. This circuitry makes the logical decisions which results in YES / NO or True/False. Simple digital circuits or the logic blocks can be combined together to form a very complex logic functions. Examples of the basic logic circuits are Inverters (Not), AND, OR, NAND, NOR GATES & FLIP FLOPS. Digital products have only 3 states namely logic 0, logic 1 & z-state. In this book let us concentrate more on how do we test & characterize these digital products.

VARIOUS TESTS PERFORMED :

The various tested that are performed in the digital logic products are as follows:

1. Continuity tests. 2. Functional tests 3. Vil tests 4. Vih tests 5. Iccqc tests 6. Iccqt test 7. Vol Tests/Ronl tests 8. Voh tests /Ronh tests 9. Iil tests 10. Iih tests 11. Iozl tests 12. Iozh tests 13. Tplh tests 14. Tphl tests 15. Tpzl test 16. Tpzh tests 17. Setup & Hold tests. In case of the Lcxh products we will have some tests like: 18. Bus hold leakage tests. 19. Bus hold sustaining current test. 20. Power off leakage tests.

OPEN SHORT TEST:

The open/short test verifies that the contact is being made to all the signal pins & that no signal pin is shorted to another signal or power/ground pins.

Test Methodology:(DC method) Ground all the device pins including the power & ground pins. Connect the PMU to a single device pin. Force the current which will forward bias one of the protection diodes. Force the current in the range of -100 to -200UA. Measure the drop .Typical value measures 0.65V. If the value measures less than 0.2V the device is failed in short test. If the device measures greater than 1.5v the device is failed in open test. If it measures between 0.2 1.5 V the device passes the open/short test. Both Power pin & the ground pin can also be subjected to this test, but as their structure is entirely different from that of the signal pin, test the power pin for the good devices & accordingly set their limits. Although the above DC static method in performing this test is quite convincing test methodology, but still as the cost of every device depends on test time. In order to reduce the test time this test is performed based on the Functional vectors. Test Methodology:(Functional method)

 Define all the signal pins as inputs and force Vil (zero volts).The 0 in the vector file instructs the tester to perform this function on each pin. Define the first signal pin as an output to be tested, turn off the tester drive on that pin, and compare the output for pass/fail. The Z character instructs the tester to perform this function on the first pin to be tested. Turn the driver back on for the pin tested in the last cycle & repeat the step 2 for the next pin tested. Continue until all the signal pins are tested. Sample vector Pattern for open/short test: 00000 -> Ground all the pins z0000 -> Tested for the pin 1 0z000 -> Tested for the pin 2 00z00 -> Tested for the pin 3 000z0 -> Tested for the pin 4 0000z -> Tested for the pin 5

FAIL-OPEN (>1.5V) PASS REGION(0.2-1.5V) FAIL-SHORT (<0.2V)

FUNCTIONAL TEST:

The functional test verifies whether the device correctly performs the intended logical functions. To accomplish this test vectors or truth tables are created. The ability of the truth table to detect the faults is called the fault coverage. The heart of the functional test comprises of the Test vectors combined with the test timings. The majority of the test resources are utilized while performing this test. Before performing this test the exact values for the following items must be carefully examined: 1. DUT power levels. 2. Input levels. 3. Output levels. 4. Output current loading. 5. Cycle time used for test. 6. Clocks/setups/holds/controls. 7. Wave shapes of the input signals. 8. When outputs will be sampled within cycle? 9. Start/Stop points within a vector file. The test vector file represents input & output logic states needed to test the DUT. The test program contains the information needed to control the test hardware in a manner that will create all the necessary voltages, waveforms & timings. As the functional test executes, the test system supplies the input data to the DUT & monitors the DUT outputs on a cycle by cycle, pin by pin basis. If any output pin fails to meet the expected logic state, voltage or timing, the result of the functional test is a failure.

Refer to the Appendix (1) for the various levels used both by the sending & the receiving drivers. Test Methodology: Define the required parameters mentioned already. Note all the input, output & timing parameters are set to their worse case conditions & the functional sequence is executed. Apply Vcc Max (Maximum tolerance of supply voltage). Perform Vil test keeping the parameter Vil as stringent & Vih as relaxed. Perform Vih test keeping the parameter Vih as stringent & vil as relaxed. Monitor the output signals during test. Fails test if any output level is different from expected. Repeat the above sequences by applying Vcc Min.
COMPARATOR LOGIC FOR THE NORMAL OUTPUT LEVELS PASS REGION (VOH > 1.6V) -LOGIC 1 FAIL REGION (1.4V < VOL/VOH< 1.6V)

PASS REGION (VOL <1.4V) -LOGIC 0

DC TESTS:
Most of the dc parameters are verified by forcing the current & setting a voltage limit or forcing voltage & setting a current limit. When a test is performed by forcing the current & measuring the voltage, the voltage is produced by the resistance of the silicon. It is Ohms law which is used to calculate the tested resistance value for each dc parameter. GROSS ICC TEST: The IDD represents the current which flows drain to drain in CMOS circuit. When testing TTL this is called as ICC. ICC represents the current which flows collector to collector in the TTL circuit. The gross ICC is the measurement of the current flow into the VDD pin. This test is often installed in the wafer probe test program and it may also be included in the Production test program. This is mainly used for correct preconditioning. The purpose of this test is to detect the high power supply currents upon initial power up. The test requirements for performing this test will not be found in the device specifications. Test requires simple preconditioning pattern & doesnt require precise preconditioning.
SAMPLE DATALOG OF GROSS IDD/ICC CURRENT USING THE DPS PIN FORCE/RNG MEAS/RNG MIN MAX RESULT

DPS1

5.25V/10V

8.7MA/50MA

-1MA

+45MA

PASS

Test Methodology: Use DPS OR PMU to apply Vcc (max). Set Pass/fail limits. Set all inputs low/high or execute reset sequence. Stop Pattern. Wait 1 to 5 ms (Set Pmu delay). Measure current flowing into the supply pins. Fails ICC if measured current is outside of the limits.

ICC STATIC CURRENT TEST: Static indicates that the DUT is not active during the test. The static ICC test insures that the DUT will not consume more current than the value stated in the device specification, when the DUT is preconditioned to its lowest current consumption logic state. This measurement is extremely important for the battery operated devices. It is also a very good way to identify the processing problems with CMOS devices. The ICC static test measures the total current flow into the Vcc pin. It is performed by executing the test vector pattern that preconditions the device to a known state, typically the state that draws the least amount of Vcc current. The device is then held in a static condition & the amount of current flowing into the Vcc pins is measured. The measured current is then compared to the ICC static test specification. The following parameters influence the test results & therefore must be specified in the device specification: VIL, VIH, VCC, and Vector Sequence & Output loading. Note if the expected ICC current is very small, additional delay time (settling time) may be required before making the current measurement. External by-pass capacitors on the test hardware can affect the measured results. In some cases it may even becomes to use a relay to disconnect the by-pass capacitor to make an accurate measurement.

SAMPLE DATALOG OF STATIC IDD/ICC CURRENT USING PMU PIN FORCE/RNG VCC1 5.25V/10V MEAS/RNG 19.20NA/25UA MIN MAX +1UA RESULT PASS

Test Methodology: Use DPS or PMU to apply Vcc (max). Execute the preconditioning pattern Stop pattern. Wait 1 to 5 ms (Set Pmu delay). Measure the current flowing into the VCC Pins. Fails this test if measured current is greater than ICC spec. The various factors that affect the CMOS IDD currents are: input levels, input pull up & pull down resistors, Vcc levels, Vector sequences, Output current loading & Output capacitor loading.
PMU TEST LIMITS:

FAIL (MEASURES > ICC SPEC)

PASS (MEASURES < ICC SPEC)

When a failure occurs remove the device from the test socket & return the test. The static IDD test should pass with an open socket. If it fails, the current is being consumed by something other than the DUT. So eliminate the sections of the test hardware until the source of the problem is found.

ICC DYNAMIC CURRENT TEST: Dynamic indicates that the DUT is active (being clocked or with its internal devices changing logic states) during the test. The dynamic ICC test insures that the DUT will not consume more current than the value stated in the device specification while the Dut is actively performing its functions. Dynamic ICC is the operating ICC of the device. The dynamic ICC test measures the total current flow into the VCC pins, normally at the maximum operating frequency of the DUT. The resultant current measured is then compared to the ICC dynamic test specification. The following parameters influence the test results & therefore must be specified in the device specification: VIL, VIH, VCC, Vector Sequence, test frequency & Output loading. When measuring the dynamic ICC currents the delay time of the PMU may need to be adjusted some experimenting may be required. The dynamic ICC Test should produce consistent results when the test is repeated.

SAMPLE DATALOG OF DYNAMIC IDD/ICC CURRENT USING DPS PIN FORCE/RNG VCC1 5.25V/10V MEAS/RNG 12.20MA/25MA MIN MAX 18UA RESULT PASS

Test Methodology: Use DPS or PMU to apply Vcc (max). Execute the preconditioning pattern Wait 1 to 5 ms (Set Pmu delay). Measure the current flowing into the VCC Pins. Fails this tests if measured current is greater than Icc spec. Stop Pattern.

VOL /IOL TEST:

VOL represents the maximum voltage produced by an output, when the output is in the low (L) state. IOL test represents the current sinking capabilities of an output when the output is in low state. The VOL / IOL test measures the resistance of an output pin when the output is in logic 0 state. This test insures that the resistance of the output meets the design parameters & guarantees that the output will provide the specified IOL current without exceeding the Vol voltage. In other words, the device output pins must sink at least a specified minimum amount of current & stay in the correct logic state. These VOL/IOL parameters may be verified either statically or dynamically. To perform a static test, the device is preconditioned to set the outputs to logic 0 states. The DC measurement system (PMU) is then connected to the pin under test, the IOL current is forced & the resultant voltage is measured & compared to the VOL specification. If the voltage measured is greater than the VOL limit the test fails. This process is repeated for each pin until all the pins have been verified in the low state.
SAMPLE DATALOG OF DYNAMIC VOL/IOL TEST USING PMU PIN PIN1 FORCE/RNG MEAS/RNG 64.0mA/20mA 130MV/RNG2 MIN MAX 400mV RESULT PASS

PIN2 PIN2 PIN2 PIN2

64.0mA/20mA 64.0mA/20mA 64.0mA/20mA 64.0mA/20mA

430MV/RNG2 130MV/RNG2 120MV/RNG2 530MV/RNG2

400mV 400mV 400mV 400mV

FAIL PASS PASS FAIL

Test Methodology: Apply the voltage Vcc (min). Precondition the output to logic 0. Using PMU, force the IOL current per specification. Wait 1 to 5 ms. Measure the resultant voltage. Fails the VOL test if the measured voltage is greater than the spec limit. PMU TEST LIMITS:

FAILS(VOLTAGE MEASURED > SPEC LIMIT) PASS(VOLTAGE MEASURED < SPEC LIMIT)

Note: 1.Applying the voltage of Vcc (min) is the worst case condition. 2. IOL is the positive current.

In case some of the pins might get failed marginally, in such instances try to insert a device in a DUT and check for

the value measured. If it measures well within the range the docking of the test handler might be the cause of the problem. If the device even gets failed in the DUT dont just assume its failure. Try to do the characterization in the Bench before proceeding further. In case of the resistor option devices lower limit fixation is a must in order to seggregate those from the non-resistor option devices.

VOH/IOH TEST:
Voh test represents the minimum voltage (V) produced by the output when the output is in the high state. IOH represents the current sourcing capabilities of an output when the output is in the high state. The VOH/IOH test measures the resistance of an output pin when the output is in the logic 1 state. This test insures that the resistance of the output meets the design parameters & guarantees that the output will provide the specified IOH current while maintaining the proper VOH TEST. These parameters may be verified either statically or dynamically. To perform the static test, the device is preconditioned to set the outputs into the logic 1 state. The DC measurement unit (PMU) is connected to the pin under test, the IOH current is forced & the resultant voltage is measured & compared to the VOH specification. If the measured voltage is less than the VOH limit, the test fails. This process is repeated until all pins have been verified in the high output state. This test may require running more than one preconditioning sequences to set all the outputs to logic 1.

SAMPLE DATALOG OF DYNAMIC VOH/IOH TEST USING PMU PIN PIN1 PIN2 PIN3 PIN4 PIN5 FORCE/RNG MEAS/RNG -15.0mA/20mA 3.250V/RNG2 -15.0mA/20mA 2.200V/RNG2 -15.0mA/20mA 3.300V/RNG2 -15.0mA/20mA 3.250V/RNG2 -15.0mA/20mA 2.100V/RNG2 MIN 2.400V 2.400V 2.400V 2.400V 2.400V MAX RESULT PASS FAIL PASS PASS FAIL

Test Methodology: Apply the voltage Vcc (min). Precondition the output to logic 1. Using PMU, force the IOH current per specification. Wait 1 to 5 ms. Measure the resultant voltage. Fails the VOH test if the measured voltage is less than the spec limit. PMU TEST LIMITS:

PASS(VOLTAGE MEASURED > SPEC LIMIT) FAILS(VOLTAGE MEASURED < SPEC LIMIT)

Note: 1.Applying the voltage of Vcc (min) is the worst case condition. 2. IOH is the negative current.

3. A voltage clamp must be set.

INPUT CURRENT TESTS (IIL/IIH TEST):

IIL is the current in an input when it is forced low. IIH is the current in an input when it is forced high. The IIL test measures the resistance from an input pin to VCC.The IIH test measures the resistance from an input pins to ground. This test insures that the resistance of the input meets the design parameter that the input will not draw more than the specified IIL/IIH current. It is also the best way to identify the processing problems in CMOS devices. There are several methods to perform the IIL/IIH input current test as follows: 1. Serial/Static Test Method 2. Parallel Test Method 3. Ganged Test Method 1.Serial /Static Test Method:

To perform the IIL test, VCC (max) is applied and all the input pins are preconditioned to logic 1 using the functional pin drivers (VIH). The DC measurement system (PMU) then forces each input low & the resulting current is measured & compared to the IIL current limit as per the test spec. This process is repeated on each pin until all the inputs have been tested. Similarly for the IIH test VCC (max) is applied and all the input pins are preconditioned to logic 0 using the functional pin drivers (VIL).Then the resulting current is measured on each individual pins. Test Methodology(IIL TEST): Apply the voltage Vcc (max). Precondition all the inputs to logic 1 with the pin drivers. Using PMU, force the individual pins to OV. Wait 1 to 5 mSec. Measure the resultant current. Fails IIL if measured current is less than the spec limit (+/- 700NA). Test Methodology(IIH TEST): Apply the voltage Vcc (max). Precondition all the inputs to logic 0 with the pin drivers.

 Using PMU, force the individual pins to VCC (max). Wait 1 to 5 mSec. Measure the resultant current. Fails IIH if measured current is less than the spec limit (+/- 700NA). ADVANTAGE: This serial test has the ability to measure the individual current flow of each pin, and also to test for pin to pin leakage. Since the pin under test receives a different voltage from all other pins ,any leakage path between the inputs will be found. DISADVANTAGE: The disadvantage of this test is the test time required to measure each pin individually. 1.Parallel Test Method: Some test systems have the capability to perform the parallel leakage measurements. It means that all the measurements are made simultaneously, but on an individual basis. This is performed by using the PMU per pin circuitry located on the pin electronics card. All inputs are forced to the logic 1 & the current flow of each pin is measured in parallel (Simultaneously).All inputs are then forced to a logic 0 & the current flow of each pin is again measured in parallel.

Test Methodology(IIL TEST): Apply the voltage Vcc (max). Precondition all the inputs to logic 1 with the pin drivers. Using PMU per pin, force each pin to OV. Wait 1 to 5 mSec. Measure the resultant current. Fails IIL if measured current is less than the spec limit (+/- 700NA).

Test Methodology(IIH TEST): Apply the voltage Vcc (max). Precondition all the inputs to logic 0 with the pin drivers. Using PMU per pin, force each pin to VCC (max). Wait 1 to 5 mSec. Measure the resultant current. Fails IIH if measured current is less than the spec limit (+/- 700NA). ADVANTAGE:

This Parallel method has the ability to perform these tests quickly & yet the individual current flow of each pin is measured. DISADVANTAGE: Pin to Pin leakage between the inputs is more difficult to detect because all inputs are held at the same voltage level when the current measurements are made. This Method requires the test system to have per pin PMU architecture. Note: In Sentry, STS - This test cannot be performed as they dont have the per pin architecture. But in Mct,Ando we can perform this test.

3.Ganged Test Method: Some test systems have the ability to perform the leakage measurements. Ganged measurement means the measurements is made by connecting a single PMU to all the inputs at one time & measuring the total current flow. All the inputs are forced to logic 1 & the total current flow is measured. All the inputs are then forced to logic 0 & the total current flow is measured. The results of the current measurements are compared to the limits set in the test program & a pass/fail decision is made. The current limit of this test is fixed the same as that of the individual pin as per the design each individual pin measures zero current & hence the sum of

the current flow is also zero. If in case, this test fails the program should be written in such a way that it performs the serial test. This Ganged test must not be performed for The resistive inputs because the sum of the leakage current for all the pins will be greater than the spec limit for an individual pin. Test Methodology (IIL TEST): Apply the voltage Vcc (max). Precondition all the inputs to logic 1 with the pin drivers. Using PMU, force all the pins to 0V. Wait 1 to 5 mSec. Measure the resultant current. Fails IIL if measured current is less than the spec limit (+/- 700NA). If fails retest using serial method.

Test Methodology(IIH TEST): Apply the voltage Vcc (max). Precondition all the inputs to logic 0 with the pin drivers. Using PMU, force all inputs to VCC (max). Wait 1 to 5 mSec. Measure the resultant current. Fails IIH if measured current is less than the spec limit (+/- 700NA).

If fails perform the serial test.

ADVANTAGE: This Gang method has the ability to perform these tests quickly & doesnt require the per pin Pmu circuitry, DISADVANTAGE: This test cannot measure the current flow thro the individual pins. Also, if in case this test fails serial test has to be performed. Note: In Sentry, STS, and Ando - This test can be performed.

SAMPLE DATALOG OF SERIAL IIH TEST (MAX)[SAY 5.5V]: PIN PIN1 PIN2 PIN3 PIN4 PIN5 FORCE/RNG 5.50V/RNG2 5.50V/RNG2 5.50V/RNG2 5.50V/RNG2 5.50V/RNG2 MEAS/RNG 0A /1UA 4UA /1UA 0A /1UA 0A /1UA 2UA /1UA

USING PMU @ VCC MAX 700NA 700NA 700NA 700NA 700NA RESULT PASS FAIL PASS PASS FAIL

MIN -700.0NA -700.0NA -700.0NA -700.0NA -700.0NA

SAMPLE DATALOG OF SERIAL IIH TEST USING PMU @ VCC (MAX) [SAY 5.5V]: PIN PIN1 PIN2 PIN3 PIN4 PIN5 FORCE/RNG 0V/RNG2 0V/RNG2 0V/RNG2 0V/RNG2 0V/RNG2 MEAS/RNG 0A /1UA 4UA /1UA 0A /1UA 0A /1UA 2UA /1UA MIN -700.0NA -700.0NA -700.0NA -700.0NA -700.0NA MAX 700NA 700NA 700NA 700NA 700NA RESULT PASS FAIL PASS PASS FAIL

PMU TEST LIMITS: FAILS(IIL/IIH> 700NA) PASS(-700NA<IIL/IIH<700NA) FAILS(IIL/IIH< -700NA)

OUTPUT IMPEDANCE CURRENT TESTS (IOZ TEST):

IOZL is the current from the output when the output is in the high impedance state and a low voltage is applied to the output. IOZH is the current from the output when the output is in the high impedance state & a high voltage is applied to the output. The Iozh high impedance leakage tests are made to insure that bi-directional & high impedance outputs are capable of achieving a high impedance or offstate.The

IOZL test measures the resistance from the output pin to VDD when the output is in the high impedance state. This test insures that the resistance of the output, when it is turned off, meets the design parameters & guarantees that the output will not draw more than the specified IOZL/IOZH current. To perform the IOZ test, Vcc is applied & a pattern is executed which preconditions the device pins to their high impedance state. The DC measurement system (PMU) forces both high & low voltage onto each pin (one at a time) & the resulting current is measured. The measured current is then compared to the IOZ spec limit in the test specification. This process is repeated on each pin individually until all the high Z-pins have been tested. This test can also be performed by the previously explained 3 methods: 1. Serial/static method 2. Parallel method 3. Ganged method Test Methodology: limit. Apply the voltage Vcc (max). Precondition all the outputs to tri state. Using PMU, force 0V. Wait 1 to 5 mSec. Measure the resultant current. Fails IOZ if it measures above the spec Repeat with PMU forcing VDD (max).

 Fails limit.

IOZ if it measures above the spec

SAMPLE DATALOG OF SERIAL IOZ TEST USING PMU @ VCC (MAX) [SAY 5.5V]: PIN PIN1 PIN1 PIN2 PIN2 PIN3 PIN3 FORCE/RNG 5.50V/RNG2 0.00V/RNG2 5.50V/RNG2 0.00V/RNG2 5.50V/RNG2 0.00V/RNG2 MEAS/RNG 0A /1UA 4UA /1UA 0A /1UA 0A /1UA 2UA /1UA 2UA /1UA MIN -700.0NA -700.0NA -700.0NA -700.0NA -700.0NA -700.0NA MAX 700NA 700NA 700NA 700NA 700NA 700NA RESULT PASS FAIL PASS PASS FAIL FAIL

PMU TEST LIMITS: FAILS(IOZ> 700NA) PASS(-700NA<IOZ<700NA) FAILS(IOZ< -700NA)

INPUT CLAMP TEST:

This represents the voltage measured on the input when a negative current is forced from the input. This test verifies the integrity of the input clamp diode between the emitter of the input transistor & the ground. This test is performed in TTL circuits.

Test Methodology: Test only applies to the TTL type devices. Apply Vcc (min). Using PMU, force 18mA (to inputs only). Wait 1 to 5 mSec. Measure the resultant current. Fails if it measures less than 1.5v.

PMU TEST LIMITS: PASS (MEASURES < - 1.5V) FAIL (MEASURES > -1.5V)

OUTPUT SHORT CIRCUIT CURRENT TEST:

This represents the current produced by the output when a shorted condition is applied to the output. The IOS test measures the resistance of an output is in the logic 1 state & 0 v is applied to the outputs. This test insures that the resistance of the output meets the design

parameters when subjected to the worse case loading conditions & guarantees that an output when shorted is capable of sourcing a predefined amount of current. The general rule to avoid hot switching is to have both sides of the relay at the same voltage before opening or closing of the relays. Test Methodology: Apply Vcc (max). Precondition output to logic 1. Using PMU, force 0V. Wait 1 to 5 mSec. Measure the resultant current. Fails if it measures outside the spec limit.

SAMPLE DATALOG OF SERIAL IOS TEST USING PMU: PIN PIN1 PIN2 PIN3 PIN4 FORCE/RNG 0.00V/RNG2 0.00V/RNG2 0.00V/RNG2 0.00V/RNG2 MEAS/RNG -53.2MA /100MA -23.2MA /100MA -43.2MA /100MA -63.2MA /100MA MIN -85.0MA -85.0MA -85.0MA -85.0MA MAX -35.0MA -35.0MA -35.0MA -35.0MA RESULT PASS FAIL PASS PASS

BUS HOLD LEAKAGE TEST:

This test is the same input leakage test for the bus hold inputs in which as there is input resistor (Terminator) this will draw more current hence only Serial method of testing is used with the limits +/- 8ua.

POWER OFF LEAKAGE TEST:

This is the test that is performed in ideal condition. In this test we force the voltage at VCC as 0V which means both the Vcc & Vee are at 0V, the current flowing at this condition with the input voltage of 4.5-5.5 V is measured. This test is performed mostly in Lvc, Alvc, Vcx devices.

Test Methodology: Apply the voltage 0v. Using PMU, force the individual pins to 4.55v. Wait 1 to 5 mSec. Measure the resultant current. Fails Ioff if measured current is less than the spec limit (+/- 700NA).

AC TESTS:

The purpose of the AC testing is to guarantee that the device meets all of its timing specifications. Ac testing is performed by setting up the appropriate timing values & signal formats as defined in the Ac specification. Before we proceed to the test methodology to conduct Ac tests in the digital devices, the terminology of the Following tests should be understood: 1. Setup time test. 2. Hold time test. 3. Propagation delay test. 4. Clock width test. 5. Maximum frequency test. 6. Output enable test. 7. Output disable test.

1.SETUP TIME :

Setup time is the minimum amount of time that the data must be present before a reference signal reaches a certain voltage point. Features: The purpose of this parameter is to guarantee that the input can be read (or latched ) within a minimum amount of time before a reference signal occurs. Performed only for the input pins. Setup time can be a negative number Setup time = (reference signal result of the binary search). 2.HOLD TIME : Hold time is the minimum amount of time that the data must be present after a reference signal reaches a certain voltage point. Features: The purpose of this parameter is to guarantee that the input can be read (or latched) within a minimum amount of time after a reference signal occurs. Performed only for the input pins. Hold time can be a negative number Hold time = (result of the binary search reference signal). 4. PROPAGATION DELAY :

It is the amount of time between the transition of one signal & the resulting transition of another signal, measured at a specific voltage (Usually at 1.5v). Most of these measurements are made from an input signal to the output signal.

Features: The purpose of this parameter is to guarantee that the output signal can occur within a specified time after the occurrence of a reference signal. Performed only on the output pins. Can only be a positive number. 5. MINIMUM CLOCK WIDTHS : The minimum amount of time which the clock can remain in the logic 0 state is Minimum clock low time. The minimum amount of time which the clock can remain in the logic 1 is Minimum clock high time.

Features: The purpose of this parameter is to guarantee that the minimum operational values for clock low & clock high timings.

 The test results can only be a positive number.

6. MAXIMUM FREQUENCY : The maximum operating frequency is usually the inverse of the sum of the minimum clock low & clock high times. When performing any test that requires the movement or the adjustments of a clock edge make certain that all timing relationships to the clock edges are properly maintained. Features: The purpose of this parameter is to guarantee that the maximum device operating frequency. The test results can only be a positive number. 7. OUTPUT ENABLE TIME : Output enable time is the time it takes an output to switch from a high impedance state to driving valid logic levels. The time is measured from a control signal to a switching output. This test requires that the outputs be connected to a load with a reference voltage set at an intermediate level.

Features: The purpose of this parameter is to gurantee that the high impedance output can drive valid output levels within a specified amount of time from occurrence of a reference signal. The test results can only be a positive number. 8. OUTPUT DISABLE TIME : Output disable time is the time it takes an output to switch from driving valid logic levels to a high impedance state, as measured from a control signal. The time is measured from a control signal to a switching output. This test requires that the outputs be connected to a load with a reference voltage set at an intermediate levels. The output causes the bus to be pulled to the intermediate level once the output drivers turn off.

Features: The purpose of this parameter is to gurantee that the high impedance output can drive valid output levels within a specified amount of time from occurrence of a reference signal. The test results can only be a positive number.

P.S: High impedance state means a state which has the voltage greater than vol & less than voh . 9. SIGNAL FORMAT : The signal formatting allows us to guarantee that all the AC parameters are tested to the specification.Signal formats when combined with the vector data,edge placements & input levels, define the wave shape of the input signals to the DUT. Various Signal Formats Used: NRZ : Non return to zero represents the actual data stored in the vector memory & contains no edge timing. NRZ data changes only at the beginning of each cycle. DNRZ : Delayed Non return to zero represents the data stored in the vector memory, but the point within the cycle where the data makes a transition is defined to be a value other than the start of the cycle. DNRZ will change after a predefined delay period only if the vector data has changed between the current cycle & the previous cycle. RZ : Return to zero provides a positive pulse when vector data is logic 1 & no pulse when the vector data is logic 0. This format can provide a positive clock when all the vector data for the pin is logic 1. RO : Return to one provides a negative pulse when the vector data is logic 0 & no pulse when the vector data is

logic 1. This format can provide a negative clock when all the vector data for the pin is logic 0. SBC : Surround by compliment can provide 3 edge transitions per cycle. This signal format creates a complex signal based on the vector data. This format is the only format that will guarantee both setup & hold time in a single execution of test vectors. This is also called as XOR. Refer to the timing diagram for various formats in the fig. 10. DEVELOPING THE INPUT SIGNAL TIMINGS : Once the cycle time has been determined ,the placement of the clock & the control signals within the cycle can be defined. There are generally 2 types of input signals control signals & data signals. Control signals determine the point in time when data signals will be read into the internal logic of the device. Data signals provide data or instructions to the device. Determine the active edges of the clock or the control signals and the amount of setup & hold time required on the data signals.This information will help define the edge placement(timing) of each input signal within the test cycle. Next determine the signal format required for each input signal. Clock signals are usually RZ(positive pulse) or RO(negative pulse) formats. Data signals & /OE are usually in NRZ format. Data signals that have the setup 7 hold time parameters requires SBC format.

Input signals are created by combining data from several areas within the test system. The waveform at the test head is the result of the test vector,edge placement timing,format definition & VIL/H values as shown in the figure.

11. DEVELOPING THE OUPUT SIGNAL TIMINGS Output signal transitions are often controlled by a clock or control signal edge. Review the device timing diagram & determines the active edge of the clock or control signals which cause the output signals to change. Determine the amount of the propagation delay time needed before the output reaches a valid logic level. This point within the cycle is where the output strobe should be placed for the particular signal. The output strobe can be a point in time or a window in time depending on the test system hardware capabilities. When the output strobe occurs the output signal for the DUT is sampled. The signal must be equal to or greater than the VOH voltage if the test vector defines the expected output as logic 1. The signal must be equal to or less than the VOL if the test vector defines the expected output as logic 0.

It is best to define the test timing so that the outputs transitions are tested within the same test cycle. This allows the tpd to be measured accurately. Make sure that certain outputs have sufficient time to propagate out before the end of the test cycle. Also, the strobing plays a major role as some testers may have limitations on how close an output strobe can be placed to the beginning or end of the T0 test cycle boundary. Refer to the fig. on output signal testing.

12. OUTPUT LOADING FOR AC TESTS : A device specification may indicate that a current load must be placed on the output of the device when performing the AC timing sets. These loads are often resistor / diode / capacitance networks which will simulate loading conditions of the circuitry which will be connected to the device in its final application. Refer to the figure for the TTL output load for ac testing . As a starting point Vcc is set to 5.0v & nothing is connected at point A. Under these conditions point B will be approximately 2.1V (0.7v dropped across each diode) and point A will also be at 2.1V. The voltage seen across RL is 2.9V (Vcc 2.1), therefore 1.45mA of current will flow thro RL & 3 diodes to ground. Next, a device output driving logic 0 (0.4v) is connected to A. This will forward biases diode D4, pulling point B to 1.1V (0.4v PLUS one diode drop). There is now 3.9V

across RL & the current flow thro RL into the device output is 1.95mA loading the device output when driving a logic 0. When the device output drives a logic 1(2.4v) D4 becomes reverse biased & eliminates the current loading effect. For this eg. The AC load provides a current load only for a logic 0; when the device drives a logic 1 the load is essentially removed.