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BEE 3133 Digital System Design

1.

COMPANYS BACKGROUND PROFILE


Tiny Digital Designers is an institute-wide and company organization which aims to

advance understanding of emerging tiny technologies, to serve researchers from throughout Tiny DD through events and activities, and to build links between interested science, engineering, and business communities at and beyond the Institute. Tiny DD was established to provide a great combination of research, education and productivity for active and rapid electronic designs services through a mixed team of local and foreign professionals with the mission of delivering unparallel service and support to both Malaysian and International markets. Through the schedule of events, we are specifically focused on advancing Tiny DDs Triad of Activities Research, Education, and Community, as well as the promotion of entrepreneurship and the innovation of new scientific and commercial ideas.

BEE 3133 Digital System Design

COMPANY DIRECTORS
2. COMPANYS ORGANISATION CHART
Project Manager WADHAH Secretary LU YEE Head Engineer ABDISAMAD Engineer AL-FAROOQ Head Designer CHOON JIAT Designer AMIRA

ADDRESS : Plot PT 2471, Nilai Industrial Estate, 71800 Nilai, Negeri Sembilan, Malaysia PHONE FAX E-MAIL : 016-9999999 : 06-6669999 : tinydd@tinydd.org.my

WEBSITE : www.TinyDigitalDesignes.org

BEE 3133 Digital System Design

3. MOORE FINITE STATE MACHINE (SEQUENCE DETECTOR) 010 i) STATE DIAGRAM


3 bits, 4 states

STATE TABLE Present State w=0 A B C D B B D B Next State w=1 A C A C 0 0 0 1 Output, Z

BEE 3133 Digital System Design

ii)

STATE ASSIGNMENT
Present State w=0 Y2 A B C D 0 0 1 1 Y1 0 1 0 1 Y2 0 0 1 0 Y1 1 1 1 1 Y2 0 1 0 1 Next State w=1 Y1 0 0 0 0 0 0 0 1 Output, Z

iii)

K-MAP AND EQUATIONS


Input wo 0 0 0 0 1 1 1 1 y2 0 0 1 1 0 0 1 1 y1 0 1 0 1 0 1 0 1 Y2 0 0 0 1 1 0 0 1 Output Y1 1 0 1 0 1 0 1 0 Z 0 0 0 0 0 0 1 1

BEE 3133 Digital System Design

w y2 y1 y2 y1 y2 y1 y2 y1 0 0 0 1

w 0 1 1 0 Y2= y2 y1 w + y1 w

w y2 y1 y2 y1 y2 y1 y2 y1 1 1 1 1

w 0 0 0 0 Y1= w

w y2 y1 y2 y1 y2 y1 y2 y1 0 0 1 0

w 0 0 1 0 Z= y2 y1

BEE 3133 Digital System Design

iv)

CIRCUIT

Part by part circuits:

For:

 

For :

= W

For :

Z=

BEE 3133 Digital System Design

v)

Total Cost

Full Circuit:

CLK RESET

Total cost = number of gates + number of inputs

vi)

= 4 + 10 Transistor Level / CMOS Circuit = 14 cost

vii) Transistor Level / CMOS Circuit

BEE 3133 Digital System Design

BEE 3133 Digital System Design

BEE 3133 Digital System Design

viii) Euler Path

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BEE 3133 Digital System Design

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BEE 3133 Digital System Design

ix)
y2 = wy1 +
2

Stick Diagram
y2
1

=  =( +


1)

(w +

+ y1)

Vdd

Vdd

y1

Vss

Vss

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BEE 3133 Digital System Design y1 = 1 = =w

Vdd

Vdd

y1

y1

y1

Vss

Vss

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BEE 3133 Digital System Design z = y2y1 = = 2 + 1

Vdd

Vdd

Vss

Vss

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BEE 3133 Digital System Design

vii) VHDL Code


library ieee; use ieee.std_logic_1164.all; entity moore_010 is port( clock,resetn,w:in std_logic;--input define z:out std_logic);--output define end moore_010; --end entity architecture behaviour of moore_010 is type state_type is (A,B,C,D);-- defining the four states of Moores FSM signal y_present,y_next:state_type; -- defining present and next states begin process (w,y_present) begin --Behavior of y:CASE statement case y_present is --State machine statement:WHEN clause and IF-ELSE when A=> if w='0' then y_next<=B; else y_next<=A; end if; when B=> if w='0' then y_next<=B; else y_next<=C; end if; when C=> if w='0' then y_next<=A; else y_next<=D; end if; when D=> if w='1' then y_next<=C; else y_next<=B;
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BEE 3133 Digital System Design end if; end case; end process; process(clock,resetn) begin if resetn='0' then y_present<=A; elsif(clock'event and clock='1')then y_present<=y_next; end if; end process; z<='1' when y_present=D else'0'; end behaviour;

RTL-viewer

a)

Functional Simulation

Functional simulation is used to verify the syntax and functionality of the design. And it approximates the behavior of the hardware design by assuming that all output change at the same time.

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BEE 3133 Digital System Design

b)

Timing Simulation

Timing simulation is used to verify the operation of the circuit. Timing simulation predicts the exact behavior of a hardware design. It is important to verify the operation of the circuit after the worse-case or error is placed and routed delays are calculated.

c) Analysis
Simulating the circuit using the obtained VHDL code verifies the correctness of the design. In this part of the assignment, we were asked to do a design of a Moore machine FSM 010 detector by using VHDL code in Quartus II. As it appears from the functional simulation that the output generates 1 when it encounters a sequence of 010. This approach can be followed by using VHDL by first creating a VHDL entity for a moore_010. Secondly, we declare this code using library ieee and STD_LOGIC type code (std_logic_1164). This will identify the type (BIT, BOOLEAN) and time definition (ns,ps).The std_logic_1164.all will define types and function to use in writing code. And in here we use the standard logic form in the input and output. Lastly, we can say that by using designing software like quartus 2; it will enable designer to do their job more easily, where they can design a logic gates in an easier way and they didnt have to design a real logic circuit for testing purposes.

4. Conclusion
To draw a conclusion, Digital Design for Finite State Machines is widely studied and manipulated to serve the need for present and future technologies. The foundation for a good start on design for state machines can be accomplished by understanding the initials and next sates. A finite state machine must have an initial state which provides a starting point, and a current state which remembers the product of the last state transition. Received input events act as triggers, which cause an evaluation of some kind of the rules that govern the transitions from
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BEE 3133 Digital System Design the current state to other states. The best way to visualize a FSM is to think of it as a flow chart or a directed graph of states, though as will be shown; there are more accurate abstract modeling techniques that can be used. For this project, we implemented Moores to detect 010. Moore machines add outputs to each state. Thus, each state is associated with an output. When you transition into the state, the output corresponding to the state is produced. After drawing all possible paths for each state, the modeled map is ready to be filled in the assignment table. The next stage is to K-map the possible equations that will derive the output. Total cost of the design was computed to see the feasibility of the design. The circuit was then tested in Quaruts II, to determine the timing and functional analysis. The VHDL code that showed the results of the equations obtained and had explained many points of the design efficiency. In completion of the project, the system was drawn into a LAYOUT EDITOR using L-EDIT software from Tanner Research. The layout was tested and the design was extracted to generate a circuit "netlist", which allows you to simulate the circuit using SPICE. The good design is the one that cover all possibilities and solve major problems.

5. Reference
i. ii. iii. iv. v. vi. http://www.ece.uprm.edu/~borges/Chp8.pdf http://web.mit.edu/tinytech/ Fundamentals of Digital Logic with VHDL (Brown,Vranesic-2005) Lecture Notes Wikipedia.org www.logomaker.com //// for company logo

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