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INTEGRATED CIRCUITS

DATA SHEET

TDA8366 I2C-bus controlled PAL/NTSC TV processor


Objective specication File under Integrated Circuits, IC02 January 1995

Philips Semiconductors

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


FEATURES Multistandard vision IF circuit (positive and negative modulation) Video identification circuit in the IF circuit which is independent of the synchronization for stable On Screen Display (OSD) under no-signal conditions Source selection with 2 Colour Video Blanking Synchronization (CVBS) inputs and a Y/C (or extra CVBS) input Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP) processor Integrated chrominance trap and bandpass filters (automatically calibrated) Integrated luminance delay line Asymmetrical peaking in the luminance channel with a (defeatable) noise coring function PAL/NTSC colour decoder with automatic search system Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications RGB control circuit with black-current stabilization and white point adjustment; to obtain a good grey scale tracking the black-current ratio of the 3 guns depends on the white point adjustment Linear RGB inputs and fast blanking Horizontal synchronization with two control loops and alignment-free horizontal oscillator Vertical count-down circuit Geometry correction by means of modulation of the vertical and EW drive I2C-bus control of various functions Low dissipation (850 mW) Small amount of peripheral components compared with competition ICs Only one adjustment (vision IF demodulator) Y, U and V inputs and outputs. GENERAL DESCRIPTION

TDA8366

The TDA8366 is an I2C-bus controlled PAL/NTSC TV processor. The circuit has been designed for use with the baseband chrominance delay line TDA4665 and for DC-coupled vertical and East-West (EW) output stages. The device can process both CVBS and Y/C input signals and has a linear RGB-input with fast blanking. The peaking circuit generates asymmetrical overshoots (the amplitude of the black overshoots is approximately 2 times higher as the one of the white overshoots) and contains a (defeatable) coring function. The RGB control circuit contains a black-current stabilizer circuit with internal clamp capacitors. The white point of the picture tube is adjusted via the I2C-bus. The deflection control circuit provides a drive pulse for the horizontal output stage, a differential sawtooth current for the vertical output stage and an East-West drive current for the East-West output stage.These signals can be manipulated for geometry correction of the picture. The supply voltage for the IC is 8 V. The IC is available in an SDIP package with 52 pins and in a QFP package with 64 pins (see Chapter Ordering information). The pin numbers indicated in this document are referenced to the SDIP52; SOT247-1 package; unless otherwise indicated.

January 1995

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8366 TDA8366H Note SDIP52 QFP64(1) DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) plastic quad at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm

TDA8366

VERSION SOT247-1 SOT319-2

1. When using IR reflow soldering it is recommended that the Drypack instructions in the Quality Reference Handbook (order number 9398 510 63011) are followed. QUICK REFERENCE DATA SYMBOL Supply VP IP Input voltages V46,47(rms) V15(p-p) V9(p-p) V8(p-p) V21,22,23(p-p) Output signals Vo(p-p) I52 V36(p-p) V13(p-p) V28(p-p) V27(p-p) V26 V19,18,17(p-p) I38 I44,45 I43 demodulated CVBS output (peak-to-peak value) tuner AGC output current range TXT output voltage (peak-to-peak value) PIP output voltage (peak-to-peak value) (RY) output voltage (peak-to-peak value) (BY) output voltage (peak-to-peak value) Y output voltage RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current EW drive output current 0 10 1 0.5 2.5 1.0 1.0 525 675 450 2.0 5 V mA V V mV mV mV V mA mA mA video IF amplier sensitivity (RMS value) external CVBS input (peak-to-peak value) S-VHS luminance input voltage (peak-to-peak value) S-VHS chroma input voltage (burst amplitude) (peak-to-peak value) RGB inputs (peak-to-peak value) 70 1.0 1.0 0.3 0.7 V V V V V supply voltage supply current 8.0 100 V mA PARAMETER MIN. TYP. MAX. UNIT

January 1995

handbook, full pagewidth

January 1995
VP2 ( 8 V) V P1 ( 8 V) 10 AGCOUT (TUNER) DEC AGC 47 46 52 51 AGC FOR IF AND TUNER POL IF AMPLIFIER AND DEMODULATOR POL 1 IFDEM1 AFC AND SAMPLE AND HOLD CONTROL DACs 17 x 6 bits 2 x 4 bits TOP 35 SCL 5
2

BLOCK DIAGRAM

Philips Semiconductors

I2C-bus controlled PAL/NTSC TV processor

PH1LF

DEC DIG DEC BG PH2LF

FBI SCO HOUT

SDA 6 41 VCO AND CONTROL 7 3 ref 40 39 37

38 EW GEOMETRY 43 EWD

I C-BUS TRANSCEIVER

2nd LOOP AND HORIZONTAL OUTPUT

48 SYNC SEPARATOR AND 1st LOOP HORIZONTAL/ VERTICAL DIVIDER 44 VERTICAL GEOMETRY 45 49 50

EHTO VDR (pos) VDR (neg) VSC I ref BLKIN

IFIN2 IFIN1

IFDEM2 2

VIDEO AMPLIFIER MUTE

TDA8366

VERTICAL SYNC SEPARATOR ref FILTER TUNING DELAY AND PEAKING SAT HUE PAL/NTSC DECODER 14 31 34 DET RYO BYO 4.4 MHz 3.6 MHz RYI 33 32 28

WHITE POINT

BLACK CURRENT STABILIZER BRI CONTR

16

20 19 18 17

BCLIN RO GO BO

4
AFC IDENT VIDEO MUTE SW TRAP BANDPASS VIDEO IDENTIFICATION RGB MATRIX AND OUTPUT SW S-VHS - SWITCH 8 9 13 36 DEC FT PIPO CHROMA CVBS/Y SEC ref XTAL2 XTAL1 CVBS/TXT CVBS - SWITCH 12 42 IFVO 4 11 CVBS INT CVBS EXT SOUND TRAP 15 G-Y MATRIX AND SAT CONTROL 27 30 29 BYI LUMIN 26 25 RGB INPUT AND SWITCH 21 22 23 24 RI GI BI RGBIN GND1 GND2

MLA745 - 1

TDA4661

LUMOUT

Objective specication

TDA8366

Fig.1 Block diagram (SDIP52; SOT247-1).

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


PINNING PIN SYMBOL SDIP52 IFDEM1 IFDEM2 DECDIG IFVO SCL SDA DECBG CHROMA CVBS/Y VP1 CVBSINT GND1 PIPO DECFT CVBSEXT BLKIN BO GO RO BCLIN RI GI BI RGBIN LUMIN LUMOUT BYO RYO BYI RYI SECref XTAL1 XTAL2 DET VP2 CVBS/TXT SCO HOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 QFP64 11 12 13 14 16 17 18 20 21 22 29 25 27 28 24 30 31 32 33 35 37 38 39 40 42 43 44 45 46 47 48 49 50 52 54 55 56 57 IF demodulator tuned circuit 1 IF demodulator tuned circuit 2 decoupling digital supply IF video output serial clock input serial data input/output bandgap decoupling chrominance input (S-VHS) external CVBS/Y input main supply voltage 1 (+8 V) internal CVBS input ground 1 picture-in-picture output decoupling lter tuning external CVBS input black-current input blue output green output red output beam current limiter input red input for insertion green input for insertion blue input for insertion RGB insertion input luminance input luminance output (BY) signal output (RY) signal output (BY) signal input (RY) signal input SECAM reference output 3.58 MHz crystal connection 4.43/3.58 MHz crystal connection loop lter phase detector horizontal oscillator supply voltage (+8 V) CVBS/TXT output sandcastle output horizontal output DESCRIPTION

TDA8366

January 1995

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


PIN SYMBOL SDIP52 FBI PH2LF PH1LF GND2 EWD VDR(pos) VDR(neg) IFIN1 IFIN2 EHTO VSC Iref DECAGC AGCOUT n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. VP3 GND3 GND4 39 40 41 42 43 44 45 46 47 48 49 50 51 52 QFP64 58 59 60 26 63 64 1 2 3 4 5 6 7 8 9 10 15 19 34 36 41 51 53 23 61 62 yback input phase-2 lter phase-1 lter ground 2 east-west drive output vertical drive 1 positive output vertical drive 2 negative output IF input 1 IF input 2 EHT/overvoltage protection input vertical sawtooth capacitor reference current input AGC decoupling capacitor tuner AGC output not connected not connected not connected not connected not connected not connected not connected not connected not connected supply voltage 3 (+8 V) ground 3 ground 4 DESCRIPTION

TDA8366

The pin numbers mentioned in the rest of this document are referenced to the SDIP52 (SOT247-1) package.

January 1995

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

handbook, halfpage

IFDEM1 IFDEM2 DEC DIG IFVO SCL SDA DEC BG CHROMA CVBS/Y

1 2 3 4 5 6 7 8 9

52 51 50 49 48 47 46 45 44 43 42 41 40 TDA8366 39 38 37 36 35 34 33 32 31 30 29 28 27
MLA737 - 1

AGCOUT DEC AGC I ref VSC EHTO IFIN2 IFIN1 VDR (neg) VDR(pos) EWD GND2 PH1LF PH2LF FBI HOUT SCO CVBS/TXT VP2 DET XTAL2 XTAL1 SEC ref RYI BYI RYO BYO

V P1 10 CVBS INT GND1 PIPO DEC FT CVBS EXT BLKIN BO GO RO BCLIN RI GI BI RGBIN LUMIN LUMOUT 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Fig.2 Pin configuration (SDIP52).

January 1995

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

55 CVBS/TXT

64 VDR(pos)

60 PH1LF

59 PH2LF

57 HOUT

62 GND4

61 GND3

63 EWD

56 SCO

VDR (neg) IFIN1 IFIN2 EHTO VSC I ref DECAGC AGCOUT n.c.

53 n.c.

58 FBI

handbook, full pagewidth

52 DET 51 n.c. 50 XTAL2 49 XTAL1 48 SEC ref 47 RYI 46 BYI 45 RYO 44 BYO 43 LUMOUT 42 LUMIN 41 n.c. 40 RGBIN 39 BI 38 GI 37 RI 36 n.c. 35 BCLIN 34 n.c. 33 RO GO 32
MLC756

1 2 3 4 5 6 7 8 9 TDA8366H

n.c. 10 IFDEM1 11 IFDEM2 12 DEC DIG 13 IFVO 14 n.c. 15 SCL 16 SDA 17 DEC BG 18 n.c. 19 CHROMA 20 CVBS/Y 21 V P1 22 VP3 23 CVBS EXT 24

GND1 25

GND2 26

PIPO 27

DEC FT 28

CVBS INT 29

BLKIN 30

54 VP2

Fig.3 Pin configuration (QFP64).

January 1995

BO 31

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


FUNCTIONAL DESCRIPTION Vision IF amplier The IF-amplifier contains 3 AC-coupled control stages with a total gain control range which is in excess of 66 dB. The sensitivity of the circuit is comparable with that of modern IF-ICs. The reference carrier for the video demodulator is obtained by means of passive regeneration of the picture carrier. The external reference tuned circuit is the only remaining adjustment of the IC. The polarity of the demodulator can be switched via the I2C-bus in such a way that the circuit is suitable for both positive and negative modulated signals. The AFC-circuit is driven with the same reference signal as the video demodulator. To avoid that the video content disturbs the AFC operation a sample-and-hold circuit is applied for signals with negative modulation. The capacitor for this function is internal. The AFC information is supplied to the tuning system via the I2C-bus. The AGC-detector operates on top-sync or top white-level depending on the polarity of the demodulator. The demodulation polarity is switched via the I2C-bus. The AGC detector time-constant capacitor is connected externally (this mainly because of the flexibility of the application). The time-constant of the AGC system during positive modulation is rather long to avoid visible variations of the signal amplitude. To obtain an acceptable speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period. When during 3 frame periods no action is detected the speed of the system is increased. The circuit contains a video identification circuit which is independent of the synchronization circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. The identification output is supplied to the tuning system via the I2C-bus. The information of this identification circuit can also be used to switch the phase-1 (1) loop to a low gain when no signal is received so that a stable OSD display is obtained. The coupling of the video identification circuit with the 1 loop can be switched on and off via the I2C-bus. Synchronization circuit

TDA8366

The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is only used to detect whether the line oscillator is synchronized and not for transmitter identification. The first Phase-Locked Loop (PLL) has a very high-statical steepness so that the phase of the picture is independent of the line frequency. The line oscillator is running at twice the line frequency. The oscillator capacitor is internal. Because of the spreads of internal components an automatic adjustment circuit has been added to the IC. It compares the oscillator frequency with that of the crystal oscillator in the colour decoder. To protect the horizontal output transistor the horizontal drive is switched-off when a power-on-reset is detected. The frequency of the oscillator is calibrated again when all subaddress bytes have been sent. When the oscillator has the right frequency the calibration stops and the horizontal drive is switched-on again via the soft start procedure (standby bit in normal mode). When the IC is switched-on the same procedure is followed. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. During the start-up procedure the duty cycle of the horizontal output pulse increases from 0 to 50% in approximately 100 lines. The vertical sawtooth generator drives the vertical output and EW correction drive circuits. The geometry processing circuits provide control of horizontal shift, EW width, EW parabola/width ratio, EW corner/parabola ratio, trapezium correction, vertical shift, vertical slope, vertical amplitude, and the S-correction. All these controls can be set via the I2C-bus. The geometry processor has a differential current

January 1995

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


output for the vertical drive signal and a single-ended output for the EW drive. Both the vertical drive and the EW drive outputs can be modulated for EHT compensation. The EHT compensation pin is also used for overvoltage protection. The geometry processor also offers the possibilities for vertical compression (for display of 16 : 9 pictures on a 4 : 3 screen) and vertical expansion (for display of 4 : 3 pictures on a 16 : 9 screen with full picture width, or for display of letter-box transmissions on a 4 : 3 screen with full picture height). For the expand mode it is possible to shift the picture vertically (only one fixed position). Also the de-interlace of the vertical output can be set via the I2C-bus. To avoid damage of the picture tube when the vertical deflection fails the guard output current of the TDA8350 can be supplied to the sandcastle output. When a failure is detected the RGB-outputs are blanked and a bit is set (NDF) in the status byte of the I2C-bus. When no vertical deflection output stage is connected this guard circuit will also blank the output signals. This can be overruled by means of the EVG bit of subaddress 0A (see Table 1). Integrated video lters The circuit contains a chrominance bandpass and trap circuit. The chrominance trap filter in the luminance path is designed for a symmetrical step response behaviour. The filters are realized by means of gyrator circuits and they are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realized by means of gyrator circuits. It is possible to connect a Colour Transient Improvement (CTI) or Picture Signal Improvement (PSI) IC to the TDA8366. Therefore the luminance signal which has passed the filter and delay line circuit is externally available. The output signal of the transient improvement circuit must be supplied to the luminance input circuit. When the CTI function is not required the two pins must be AC-coupled. Video switches

TDA8366

The circuit has two CVBS inputs and an Super-Video Home System (S-VHS) input. The input can be chosen by the I2C-bus. The input selector also has a position in which CVBSEXT is processed, unless there is a signal on the S-VHS input. When the input selector is in this position it switches to the S-VHS input if the S-VHS detector detects sync pulses on the S-VHS luminance input. The S-VHS detector output can be read by the I2C-bus. When the S-VHS option is not used the luminance input can be used as a second input for external CVBS signals. The choice is made via the CVS-bit (see Table 1). The video switch circuit has two outputs which can be programmed in a different way. The input signal for the decoder is also available on the TXT output. Therefore this signal can be used to drive the teletext decoder and the SECAM add-on decoder. The signal on the PIP output can be chosen independent of the TXT output. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again. Colour decoder The colour decoder contains an alignment-free crystal oscillator, a killer circuit and the colour difference demodulators. The 90 phase shift for the reference signal is made internally. The demodulation angle and gain ratio for the colour difference signals for PAL and NTSC are adapted to the standard. The colour decoder is very flexible. Together with the SECAM decoder TDA8395 an automatic multistandard decoder can be designed. Which standard the IC can decode depends on the external crystals. If a 4.4 MHz and a 3.5 MHz crystal are used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be decoded. If two 3.5 MHz crystals are used PAL N and M can be decoded. If one crystal is connected only PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The crystal frequency of the decoder is used to tune the line oscillator. Therefore the value of the crystal frequency must be given to the IC via the I2C-bus.

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


RGB output circuit and black-current stabilization The colour-difference signals are matrixed with the luminance signal to obtain the RGB-signals. For the RGB-inputs linear amplifiers have been chosen so that the circuit is suited for signals coming from the SCART connector. The contrast and brightness control operate on internal and external signals. The output signal has an amplitude of approximately 2 V black-to-white at nominal input signals and nominal settings of the controls. The black current stabilization is realized by means of a feedback from the video output amplifiers to the RGB control circuit. The black current of the 3 guns of the picture tube is internally measured and stabilized. The black level control is active during 4 lines at the end of the vertical blanking. During the first line the leakage current is measured and the following 3 lines the 3 guns are adjusted to the required level. The maximum acceptable leakage current is 100 A. The nominal value of the black current is 10 A. The ratio of the currents for the various guns automatically tracks with the white point adjustment so that the back-ground colour is the same as the adjusted white point. The input impedance of the black-current measuring pin is 15 k. Therefore the beam current during scan will cause the input voltage to exceed the supply voltage. The internal protection will start conducting so that the excessive current is bypassed. When the TV receiver is switched-on the black current stabilization circuit is not active, the RGB outputs are blanked and beam current limiting input pin is short-circuited. Only during the measuring lines will the outputs supply a voltage of 5 V to the video output stage so that it can be detected if the picture tube is warming up. These pulses are switched-on after a waiting time of approximately 0.5 s. This ensures that the vertical deflection is activated so that the measuring pulses are not

TDA8366
visible on the screen. As soon as the current supplied to the measuring input exceeds a value of 190 A the stabilization circuit is activated. After a waiting time of approximately 0.8 s the blanking and the beam current limiting input pin are released. The remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. I2C-BUS SPECIFICATION

handbook, halfpage

A6 1

A5 0

A4 0

A3 0

A2 1

A1 0

A0 1

R/W 1/0
MLA743

X = dont care.

Fig.4 Slave address (8A).

Valid subaddresses: 00 to 13; subaddress FE is reserved for test purposes. Auto-increment mode is available for subaddresses. Start-up procedure Read the status bytes until POR = 0 and send all subaddress bytes. The horizontal output signal is switched-on when the oscillator is calibrated. It is possible to have the horizontal output signal available before calibration. Then the SFM bit must be set to logic 0. Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, the procedure mentioned above must be carried out to restart the IC. When this procedure is not followed the horizontal frequency may be incorrect after power-up or after a power dip.

January 1995

11

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


Inputs Table 1 Input status bits; note 1 FUNCTION Source select Decoder mode Hue Horizontal shift (HS) EW width (EW) EW parabola/width (PW) EW corner parabola (CP) EW trapezium (TC) Vertical slope (VS) Vertical amplitude (VA) S-correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC take-over Note 1. X = dont care. Table 2 Output status bits; note 1 FUNCTION Output status bytes SUBADDRESS (HEX) 00 01 Note 1. X = dont care. DATA BYTE D7 POR NDF D6 FSI IN1 D5 STS X D4 SL IFI D3 XPR AFA D2 CD2 AFB SUBADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 DATA BYTE D7 INA X X X X X X NCIN VID HCO SBL EXP SFM MAT YD3 RBL IE1 AFW MOD D6 INB X X X X X X X LBM EVG PRD CL CVS PHL YD2 COR X IFS VSW D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 YD1 A5 A5 A5 A5 D4 IND STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 YD0 A4 A4 A4 A4 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2

TDA8366

D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1

D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0

FORF FORS

D1 CD1 X

D0 CD0 X

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


INPUT CONTROL BITS Table 3 INA 0 0 1 1 Table 4 INC 0 0 1 1 Table 5 FOA 0 0 1 Note 1. X = dont care. Table 6 XA 0 0 1 1 Crystal indication XB 0 1 0 1 two 3.6 MHz one 3.6 MHz (pin 32) one 4.4 MHz (pin 33) 3.6 MHz (pin 32) and 4.4 MHz (pin 33) Table 11 Colour decoder mode CM2 0 0 0 0 1 1 1 1 CM1 0 0 1 1 0 0 1 1 CM0 0 1 0 1 0 1 0 1 CRYSTAL Source select 1 INB 0 1 0 1 DECODER AND TXT CVBSINT CVBSEXT S-VHS S-VHS (CVBSEXT) Table 7 FORF 0 0 1 1 Note PIP CVBSINT CVBSEXT S-VHS S-VHS (CVBSEXT) Table 8 DL 0 1 Table 9 STB 0 1 standby normal interlace de-interlace Standby MODE Interlace STATUS Forced eld frequency FORS 0 1 0 1

TDA8366

FIELD FREQUENCY auto (60 Hz when line not synchronized) 60 Hz; note 1 50 Hz; note 1 auto (50 Hz when line not synchronized)

Source select 2 IND 0 1 0 1

1. When the forced mode is selected the divider will only switch to that position when the horizontal oscillator is not synchronized.

Phase 1 (1) time constant FOB(1) 0 1 X normal slow fast MODE

Table 10 Synchronization mode POC 0 1 active not active MODE

DECODER MODE not forced, own intelligence forced NTSC 3.6 MHz forced PAL 4.4 MHz forced SECAM forced NTSC 4.4 MHz forced PAL 3.6 MHz (pin 32) forced PAL 3.6 MHz (pin 33) no function

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


Table 12 Vertical divider mode NCIN 0 1 VERTICAL DIVIDER MODE normal operation switched to search window

TDA8366
Table 20 Horizontal frequency during switch-on SFM 0 1 maximum nominal START-UP FREQUENCY

Table 13 Video ident mode VID 0 1 not active VIDEO IDENT MODE 1 loop switched on and off

Table 21 Condition Y/C input CVS 0 1 Y-INPUT MODE switched to Y/C mode switched to CVBS mode

Table 14 Long blanking mode LBM 0 1 BLANKING MODE adapted to standard (50 or 60 Hz) xed in accordance with 50 Hz standard

Table 22 PAL/NTSC matrix MAT 0 1 PAL MATRIX adapted to standard

Table 15 EHT tracking mode HCO 0 1 TRACKING MODE EHT tracking only on vertical EHT tracking on vertical and EW

Table 23 Colour crystal PLL PHL 0 1 PLL closed oscillator free-running STATE

Table 16 Enable vertical guard (RGB blanking) EVG 0 1 active VERTICAL GUARD MODE not active

Table 24 Y-delay adjustment; note 1 YD0 to YD3 YD3 YD2 YD1 YD0 Note 1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 160 ns. This is only valid for a CVBS signal without group delay distortions. Table 25 RGB blanking RBL 0 not active active 1 RGB BLANKING YD3 160 ns + YD2 80 ns + YD1 40 ns + YD0 40 ns Y-DELAY

Table 17 Service blanking SBL 0 1 off on SERVICE BLANKING MODE

Table 18 Overvoltage input mode PRD 0 1 OVERVOLTAGE MODE detection mode protection mode

Table 19 Vertical deection mode EXP 0 0 1 1 January 1995 CL 0 1 0 1 VERTICAL DEFLECTION MODE normal compress expand expand and lift 14

Table 26 Noise coring (peaking) COR 0 1 off on NOISE CORING

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


Table 27 Enable fast blanking IE1 0 1 not active active FAST BLANKING Table 35 Phase 1 (1) lock indication SL 0 1 not locked locked INDICATION

TDA8366

Table 28 AFC window AFW 0 1 normal enlarged AFC WINDOW

Table 36 X-ray protection XPR 0 1 OVERVOLTAGE no overvoltage detected overvoltage detected

Table 29 IF sensitivity IFS 0 1 normal reduced IF SENSITIVITY

Table 37 Colour decoder mode CD2 0 0 0 0 1 1 1 1 CD1 0 0 1 1 0 0 1 1 CD0 0 1 0 1 0 1 0 1 STANDARD no colour standard identied NTSC 3.6 MHz PAL 4.4 MHz SECAM NTSC 4.4 MHz PAL 3.6 MHz (pin 32) PAL 3.6 MHz (pin 33) spare

Table 30 Modulation standard MOD 0 1 negative positive MODULATION

Table 31 Video mute VSW 0 1 normal operation IF-video signal switched off STATE Table 38 Output vertical guard NDF 0 1 OUTPUT CONTROL BITS Table 32 Power-on-reset POR 0 1 normal power-down MODE Table 39 Indication RGB insertion IN1 0 1 RGB INSERTION no (pin 24 LOW) yes (pin 24 HIGH) OK failure VERTICAL OUTPUT STAGE

Table 33 Field frequency indication FSI 0 1 50 Hz 60 Hz FREQUENCY

Table 40 Output video identication IFI 0 1 VIDEO SIGNAL no video signal identied video signal identied

Table 34 S-VHS status STS 0 1 no signal signal S-VHS INPUT

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


Table 41 AFC output AFA 0 0 1 1 AFB 0 1 0 1 CONDITION outside window; too low outside window; too high in window; below reference in window; above reference

TDA8366

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Tstg Tamb Tsol Tj Ves PARAMETER supply voltage storage temperature operating ambient temperature soldering temperature operating junction temperature electrostatic handling MM; all pins; notes 1 and 3 Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 k; C = 100 pF. 3. Machine Model (MM): R = 0 ; C = 200 pF. THERMAL CHARACTERISTICS SYMBOL Rth j-a SDIP52 QFP64 QUALITY SPECIFICATION In accordance with SNW-FQ-611E. The number of the quality specification can be found in the Quality Reference Handbook. The handbook can be ordered using the code 9398 510 63011. Latch-up Itrigger 100 mA or 1.5VDD(max) Itrigger 100 mA or 0.5VDD(max). PARAMETER thermal resistance from junction to ambient in free air 40 50 K/W K/W VALUE UNIT for 5 s CONDITIONS 25 0 HBM; all pins; notes 1 and 2 2000 200 MIN. MAX. 9.0 +150 70 260 150 +2000 +200 V C C C C V V UNIT

Following pins do not meet the above specification: Pin 7: 90 mA Pin 17: 90 mA Pin 18: 90 mA Pin 19: 90 mA Pin 24: 90 mA Pin 34: 60 mA Pin 49: 90 mA Pin 50: 90 mA.

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


CHARACTERISTICS VP = 8 V; Tamb = 25 C; unless otherwise specied. SYMBOL Supplies MAIN SUPPLY (PIN 10) VP1 IP1 Ptot VP2 IP2 IF circuit VISION IF AMPLIFIER INPUTS (PINS 46 AND 47) Vi(rms) input sensitivity (RMS value) note 1 fi = 38.90 MHz fi = 45.75 MHz fi = 58.75 MHz RI CI Gcr Vi max(rms) input resistance (differential) input capacitance (differential) gain control range maximum input signal (RMS value) note 2 note 2 64 100 70 70 70 2 3 150 supply voltage supply current total power dissipation 7.2 7.2 8.0 100 850 PARAMETER CONDITIONS MIN. TYP.

TDA8366

MAX.

UNIT

8.8 8.8

V mA W

HORIZONTAL OSCILLATOR SUPPLY (PIN 35) supply voltage supply current 8.0 6 V mA

100 100 100

V V V k pF dB mV

VIDEO AMPLIFIER OUTPUT (PIN 4); note 3 Vo V4 V4 V4 zero signal output level top sync level white level difference in amplitude between negative and positive modulation video output impedance internal bias current of NPN emitter follower output transistor maximum source current bandwidth of demodulated output signal differential gain differential phase video non-linearity white spot threshold level white spot insertion level at 3 dB note 5 notes 5 and 6 note 7 negative modulation; note 4 positive modulation; note 4 negative modulation positive modulation 1.9 4.7 2.0 2.0 4.5 0 2.1 15 V V V V %

Zo Ibias Isource(max) B Gdiff diff NLvid Vth Vins

1.0 6

50 9 2 5.0 3.3

5 5 5 5

mA mA MHz % deg % V V

January 1995

17

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS notes 6 and 8 Vo = 0.92 or 1.1 MHz Vo = 2.66 or 3.3 MHz yellow S/N signal-to-noise ratio Vo = 0.92 or 1.1 MHz Vo = 2.66 or 3.3 MHz notes 6 and 9 Vi = 10 mV end of control range V4 V4 residual carrier signal residual 2nd harmonic of carrier signal note 6 note 6 52 52 60 61 5.5 2.5 60 60 56 60 66 66 62 66 MIN. TYP.

TDA8366

MAX.

UNIT

VIDEO AMPLIFIER OUTPUT (CONTINUED) Nclamp Nins mod noise inverter clamping level noise inverter insertion level (identical to black level) intermodulation blue 1.4 2.6 V V

dB dB dB dB dB dB mV mV

IF AND TUNER AGC; note 10

timing of IF-AGC with a 2.2 F capacitor (pin 51)


modulated video interference tinc response time to an IF input signal amplitude increase of 52 dB response to an IF input signal amplitude decrease of 52 dB allowed leakage current of the AGC capacitor 30% AM for 1 mV to 100 mV; 0 to 200 Hz (system B/G) positive and negative modulation negative modulation positive modulation negative modulation positive modulation 2 10 % ms

tdec IL

40

50 100 0.4 80

10 200

ms ms A nA

Tuner take-over adjustment (via


V51min(rms) V51max(rms)

I2C-bus)
0.8 mV mV

minimum starting level for tuner take-over (RMS value) maximum starting level for tuner take-over (RMS value)

Tuner control output (pin 52)


V52max V52(sat) I52max IL Vi maximum tuner AGC output voltage output saturation voltage maximum tuner AGC output swing leakage current RF AGC input signal variation for complete tuner control maximum tuner gain; note 2 minimum tuner gain; I47 = 2 mA 5 0.5 2 VP + 1 300 1 4 V mV mA A dB

January 1995

18

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS 65 195 note 6 MIN. TYP.

TDA8366

MAX. 100 300 50

UNIT

AFC OUTPUT (VIA I2C-BUS); note 11 RES Wsen WsenL fos td AFC resolution window sensitivity window sensitivity in large window mode AFC offset 2 80 240 bits kHz kHz kHz

VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS) delay time of identication after the AGC has stabilized on a new transmitter 10 ms

CVBS and S-VHS input switch INTERNAL AND EXTERNAL CVBS INPUTS (PINS 11 AND 15) V11(p-p) I11 SSCVBS CVBS input voltage (peak-to-peak value) CVBS input current suppression of non-selected CVBS input signal notes 6 and 13 note 12 50 1.0 4 1.4 V A dB

S-VHS INPUT (PINS 8 AND 9) V9(p-p) I9(p-p) V8 I8 Vo(p-p) Zo VTS luminance input voltage (peak-to-peak value) luminance input current chrominance input voltage (burst amplitude) chrominance input current note 14 1.0 4 0.3 4 1.4 0.45 250 V A V A V V

TXT AND PIP OUTPUT SIGNALS (PINS 36 AND 13) output signal amplitude (peak-to-peak value) output impedance top sync level 1.0 2.5

January 1995

19

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS MIN. TYP.

TDA8366

MAX.

UNIT

RGB inputs, colour difference inputs, luminance inputs and outputs RGB INPUTS (PINS 21, 22 AND 23) V21,22,23(p-p) input signal amplitude for an output signal of 2 V (black-to-white) (peak-to-peak value) input signal amplitude before clipping occurs (peak-to-peak value) difference between black level of internal and external signals at the outputs input currents delay difference for the three channels no clamping; note 2 note 6 note 15 0.7 0.8 V

V21,22,23(p-p)

note 6

1.0

Vo

20

mV

I21,22,23 td

0.5 20

A ns

FAST BLANKING (PIN 24) Vi V24(max) td td input voltage maximum input pulse delay time from RGB in to RGB out delay difference between insertion to RGB out and RGB in to RGB out input current suppression of internal RGB signals suppression of external RGB signals input voltage to blank the RGB outputs to facilitate On Screen Display signals being applied to the outputs notes 6 and 12; insertion; fi = 0 to 5 MHz notes 6 and 12; no insertion; fi = 0 to 5 MHz no data insertion data insertion insertion data insertion; note 6 data insertion; note 6 0.9 100 50 0.4 3.0 V V V ns ns

I24 SSint SSext VI

55 55 4

0.2

mA dB dB V

COLOUR DIFFERENCE INPUT SIGNALS (PINS 29 AND 30) V30(p-p) V29(p-p) I29,30 input signal amplitude (RY) (peak-to-peak value) input signal amplitude (BY) (peak-to-peak value) input current for both inputs note 2 note 2 note 2 1.05 1.35 0.1 1.0 V V A

January 1995

20

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS during burst key pulse no clamp MIN. TYP.

TDA8366

MAX.

UNIT

LUMINANCE INPUTS AND OUTPUTS (PINS 25 AND 26) V26(p-p) VTS Zo V25(p-p) Iclamp Ii output signal amplitude (peak-to-peak value) top sync level output impedance input signal amplitude (peak-to-peak value) clamp current input current top sync-white 0.45 2.5 250 0.45 200 0.63 0.5 V V V A A

Chrominance lters CHROMINANCE TRAP CIRCUIT ftrap QF SR trap frequency trap quality factor colour subcarrier rejection note 16 20 fosc 2 fosc 3 dB MHz

CHROMINANCE BANDPASS CIRCUIT fc QBP centre frequency bandpass quality factor MHz

Delay line and peaking circuit Y DELAY LINE td td1 B delay time tuning range delay time bandwidth of internal delay line note 6 8 steps note 6 160 5 note 2 positive negative peaking control curve CORING STAGE S GW coring range wave gain negative half wave gain ------------------------------------------------------------positive half wave gain 15 1.8 IRE 16 steps 480 3 160 20 36 see Fig.5 +160 ns ns MHz

PEAKING CONTROL; note 17 fc(p) tW OS peaking centre frequency width of preshoot or overshoot overshoot MHz ns % %

Horizontal synchronization circuits SYNC VIDEO INPUT (PINS 9, 11 AND 15) V9,11,15 SLHS SLVS sync pulse amplitude slicing level for horizontal sync slicing level for vertical sync note 2 note 18 50 300 50 30 mV % %

January 1995

21

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS VP = 8.0 V 10%; note 6 Tamb = 0 to 70 C; note 6 MIN. TYP.

TDA8366

MAX. 2 0.5 80 75

UNIT

HORIZONTAL OSCILLATOR ffr ffr f/VP f(max) fosc(max) free running frequency spread on free running frequency frequency variation with respect to the supply voltage frequency variation with temperature maximum frequency deviation at the start of the horizontal output 15625 0.2 Hz % % Hz %

FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 41); note 19 fHR fCR S/N holding range PLL catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point note 6 0.6 0.9 0.9 20 1.2 kHz kHz dB

HYS i/o tcr

11

dB s/s s

SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 40) control sensitivity control range from start of horizontal output to yback at nominal shift position horizontal shift range control sensitivity for dynamic compensation HORIZONTAL OUTPUT (PIN 38); note 20 VOL IO(max) VO(max) VHSW V2(SW) V39(max) Zi LOW level output voltage maximum allowed output current maximum allowed output voltage duty factor note 6 IO = 10 mA 10 note 2 note 2 50 0.3 VP V mA V % 63 steps 150 12

tshift

5.3

s s/V

FLYBACK PULSE INPUT (PIN 39) switching level for horizontal blanking switching level for phase-2 loop maximum input voltage input impedance 0.4 4.0 8.0 10 V V V M

January 1995

22

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS MIN. TYP.

TDA8366

MAX.

UNIT

SANDCASTLE PULSE OUTPUT (PIN 37) V37 tW output voltage pulse width during burst key during blanking burst key pulse vertical blanking (50 Hz) vertical blanking (60 Hz) Vclamp I37(min) I37(max) td clamp level for vertical guard detection minimum input current to activate guard detection maximum allowable input current delay of start of burst key to start of sync 4.8 1.8 3.3 2.5 5.3 2.0 3.5 25 21 2.7 5.4 5.8 2.2 3.7 0.5 V V s lines lines V mA mA s

SOFT START; note 21 df tss duty factor control range soft start time 0 100 50 % lines

Vertical synchronization and geometry correction VERTICAL OSCILLATOR; note 22 ffr flock free running frequency locking range divider value not locked locking range VERTICAL RAMP GENERATOR (PIN 49) V49(p-p) Idis Icharge VS sawtooth amplitude (peak-to-peak value) discharge current charge current set by external resistor vertical slope note 23 control range (63 steps) compress mode expand mode I49 V49L charge current increase LOW level of ramp f = 60 Hz normal or expand mode compress mode VERTICAL DRIVE OUTPUTS (PINS 44 AND 45) Idiff(p-p) ICM Vo January 1995 differential output current (peak-to-peak value) common mode current output voltage range 23 VA = 1FH 0 1 400 4.0 mA A V VS = 1FH; C = 100 nF; R = 39 k 14 3.5 1 19 75 133 20 2.07 2.55 +14 V mA A % % % % V V 45 488 50/60 625/525 64.5 722 Hz Hz lines lines/ frame

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL V48 SMR vert EW Ieq V48 DE-INTERLACE rst eld delay EW WIDTH CR Ieq Vo Io CR Ieq CR Ieq CR Ieq CR Ieqdiff(p-p) control range equivalent output current EW output voltage range EW output current range 63 steps 100 0 1.0 0 0.5H PARAMETER CONDITIONS MIN. 7.5 7.5 3.9 TYP.

TDA8366

MAX.

UNIT

EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 48) input voltage scan modulation range vertical sensitivity EW sensitivity EW equivalent output current overvoltage detection level when switched-on 1.2 6 +120 2.8 +6 120 80 400 8.0 900 % A V A % A % A % A % % A V % %/V %/V A V

EW PARABOLA/WIDTH control range equivalent output current 63 steps EW = 3FH 0 0 44 210 4 80 63 steps; SC = 00H 63 steps; SC = 3FH equivalent differential vertical drive output current (peak-to-peak value) SC = 00H 80 86 800 24 480

EW CORNER/PARABOLA control range equivalent output current 63 steps PW = 3FH; EW = 3FH 0 0

EW TRAPEZIUM control range equivalent output current 63 steps +4 +80

VERTICAL AMPLITUDE control range 120 112 1200

VERTICAL SHIFT CR Ieqdiff(p-p) control range equivalent differential vertical drive output current (peak-to-peak value) 63 steps 4 40 +4 +40 % A

S-CORRECTION CR control range 63 steps 0 25 %

January 1995

24

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS MIN. TYP.

TDA8366

MAX.

UNIT

Colour demodulation part CHROMINANCE AMPLIFIER ACCcr V ACC control range change in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF strong signal conditions; S/N 40 dB; note 6 noisy input signals; note 6 ACL CIRCUIT chrominance burst ratio at which the ACL starts to operate REFERENCE PART 2.3 2.7 note 24 26 2 dB dB

THRon HYSoff

23

26 +3 +1

29

dB dB dB

Phase-locked loop; note 25


fCR catching range phase shift for a 400 Hz deviation of the oscillator frequency note 6 300 500 2 Hz deg

Oscillator
TCosc fosc Ri Ci HUE CONTROL HUEcr HUE HUE/T hue control range hue variation for 10% VP hue variation with temperature 63 steps; see Fig.6 note 6 Tamb = 0 to 70 C; note 6 35 40 0 0 deg deg deg temperature coefcient of the oscillator frequency oscillator frequency deviation with respect to the supply input resistance input capacitance note 6 note 6; VP = 8 V 10% pin 32; f = 3.58 MHz; note 2 pin 33; f = 4.43 MHz; note 2 pins 32 and 33; note 2 2.0 1.5 1.0 2.5 250 10 Hz/K Hz k k pF

January 1995

25

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS 1.60 MIN. TYP.

TDA8366

MAX. 1.96

UNIT

DEMODULATORS (PINS 27 AND 28) V28(p-p) V27(p-p) G (RY) output signal amplitude (peak-to-peak value) (BY) output signal amplitude (peak-to-peak value) gain between both demodulators G(BY) and G(RY) spread of signal amplitude ratio PAL/NTSC output impedance (RY)/(BY) output bandwidth of demodulators residual carrier output (peak-to-peak value) note 6 note 6 3 dB; note 27 f = fosc; (RY) output f = fosc; (BY) output f = 2fosc; (RY) output f = 2fosc; (BY) output V28(p-p) Vo/T Vo/VP e H/2 ripple at (RY) output (peak-to-peak value) change of output signal amplitude with temperature change of output signal amplitude with supply voltage phase error in the demodulated signals note 6 note 6 0.1 note 26 note 26 0.525 0.675 1.78 V V

V Zo B V27,28(p-p)

500 650

+1 5 5 5 5 25 0.1 5

dB kHz mV mV mV mV mV %/K dB deg

COLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT

PAL or (SECAM mode with TDA8395); (RY) and (BY) not affected
(GY)/(RY) ratio of demodulated signals (GY)/(BY) ratio of demodulated signals 0.51 10% 0.19 25% (BY) 1.39(RY) 0.07(BY) 0.46(RY) 0.15(BY)

NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)
(BY) (RY) (GY) (BY) signal (RY) signal (GY) signal

January 1995

26

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS 0.2 PAL/NTSC identied no PAL/NTSC identied; SECAM (by TDA8395) identied I31 required current to stop PAL/NTSC identication circuit during SECAM MIN. TYP.

TDA8366

MAX. 0.3

UNIT

REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 31) fref V31(p-p) Vo reference frequency output signal amplitude (peak-to-peak value) output level 4.43 0.25 1.5 5.0 MHz V V V

150

Control part SATURATION CONTROL; note 15 SATcr CONcr saturation control range 63 steps; see Fig.7 52 20 0.5 dB

CONTRAST CONTROL; note 15 contrast control range 63 steps dB dB tracking between the three see Fig.8 channels over a control range of 10 dB BRIGHTNESS CONTROL BRIcr V17,18,19(p-p) brightness control range 63 steps; see Fig.9 tbf 0.7 2.0 tbf V

RGB AMPLIFIERS (PINS 17, 18 AND 19) output signal amplitude (peak-to-peak value) at nominal luminance input signal, nominal contrast and white-point adjustment; note 15 at maximum white point setting VBWmax(p-p) maximum signal amplitude (black-to-white) output signal amplitude for the red channel (peak-to-peak value) blanking level at the RGB outputs internal bias current of NPN emitter follower output transistor available output current output impedance note 28 at maximum white point setting V

3.0 2.6 3.6 2.1

tbf

V V V V

VRED(p-p)

at nominal settings for tbf contrast and saturation control and no luminance signal to the input (RY, PAL) 0.7

Vblank Ibias Io Zo

0.8 1.5 5 150

0.9

V mA mA

January 1995

27

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS MIN. TYP.

TDA8366

MAX. 1

UNIT

RGB AMPLIFIERS (CONTINUED) CRbl control range of the black-current stabilization nominal brightness and white-point adjustment (with respect to the measuring pulse); Vblk = 2.5 V note 6 V

Vbl Vo bl/T bl

black level shift with picture content output voltage of the 4-L pulse after switch-on variation of black level with temperature relative variation in black level between the three channels during variations of supply voltage (10%) saturation (50 dB) contrast (20 dB) brightness (0.5 V) temperature (range 40 C)

4.2 1.0

20

mV V mV/K

note 6 note 6

nominal controls nominal contrast nominal saturation nominal controls RGB input; note 29 CVBS input; note 29 at fosc at 2fosc plus higher harmonics in RGB outputs RGB input; at 3 dB CVBS input; at 3 dB; fosc = 3.58 MHz CVBS input; at 3 dB; fosc = 4.43 MHz S-VHS input; at 3 dB

60 50 8 5 40 40

2.8 3.5 20H 50 50

tbf tbf tbf tbf tbf 15 15 60 60

mV mV mV mV mV dB dB mV mV MHz MHz MHz MHz

S/N Vres(p-p)

signal-to-noise ratio of the output signals residual voltage at the RGB outputs (peak-to-peak value) bandwidth of output signals

WHITE-POINT ADJUSTMENT I2C-bus setting for nominal gain Ginc(max) Gdec(max) Ibias Ileak Iscan(max) maximum increase of the gain maximum decrease of the gain HEX code HEX code 3FH HEX code 00H % % A A mA

BLACK-CURRENT STABILIZATION (PIN 16); note 30 bias current for the picture tube cathode acceptable leakage current maximum current during scan 10 100 0.3

January 1995

28

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SYMBOL PARAMETER CONDITIONS MIN. TYP.

TDA8366

MAX.

UNIT

BEAM CURRENT LIMITING (PIN 20); note 28 VCR VdiffCR VBR VdiffBR Vbias Ich(int) Idisch Notes 1. On set AGC. 2. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 3. Measured at 10 mV (RMS) top sync input signal. 4. So called projected zero point, i.e. with switched demodulator. 5. Measured in accordance with the test line given in Fig.10. For the differential phase test the peak white setting is reduced to 87%. a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 7. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.11. 8. The test set-up and input conditions are given in Fig.12. The figures are measured with an input signal of 10 mV RMS. 9. Measured with a source impedance of 75 , where: V O (black-to-white) S/N = 20 log -------------------------------------------------------V m ( rms ) ( B = 5 MHz ) 10. To obtain a good noise immunity of the AGC circuit the AGC detector is gated during the sync pulse. This gating is switched-off during the vertical retrace to avoid disturbances of the signal amplitude due to phase errors of the incoming video signal which are caused by the head-switching of VCRs. contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction internal bias voltage internal charge current discharge current due to peak-white limiting 4 2 3 2 4.5 40 200 V V V V V A A

January 1995

29

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

11. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is obtained with a Q-factor of 60. The AFC off-set is tested with a double sideband input signal and with the reference tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator). The tuning information is supplied to the tuning system via the I2C-bus. Two bits have been reserved for this function. The first bit indicates whether the tuning is within the given window. The second bit indicates the direction of the tuning. Bit indications: a) AFA = 1; tuning inside window. b) AFA = 0; tuning outside window. c) AFB = 1; tuning too high. d) AFB = 0; tuning too low. To improve the speed of search tuning systems the AFC window can be increased to about 240 kHz. The width of the window can be set by means of the AFW bit in subaddress 03. 12. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 13. This parameter is measured at nominal settings of the various controls. 14. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1). 15. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum 10 dB. In the nominal brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses. 16. The 3 dB bandwidth of the circuit can be calculated by means of the following equation: 1 f 3 dB = f osc 1 ------- 2Q 17. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 18. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). 19. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a noise detector and the time constant is switched to slow when too much noise is present in the signal. In the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatically or overruled by the I2C-bus. The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first loop can be defeated via the I2C-bus. When the horizontal PLL is set to the slow mode (via I2C-bus bits FOA and FOB) or during weak signal conditions in the automatic mode the phase detector is gated to obtain a good noise immunity. The width of the gating pulse is 5.7 s. The output current of the phase detector in the various conditions are shown in Table 42. 20. During the start-up period of the oscillator the duty factor of the output pulse rises gradually from 0% to 50% (time approximately 100 lines). 21. The start-up frequency depends on the SFM bit in the I2C-bus protocol. When SFM = 0 the frequency starts at a high (non calibrated) value. When SFM = 1 the output signal will only be available after calibration.

January 1995

30

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

22. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation: a) Search mode large window. This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode narrow window. This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz). When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress 08. 23. Conditions: frequency is 50 Hz; normal mode; VS = 1F. 24. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and 20 dB. 25. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than 1 dB with respect to the fundamental frequency for a damping resistance of 1 k, oscillation at the fundamental frequency is guaranteed. The spurious response of the 3.58 MHz crystal must be lower than 1 dB with respect to the fundamental frequency for a damping resistance of 1.5 k. The catching and detuning range are measured for nominal crystal parameters. These are: a) Load resonance frequency f0 = 4.433619 or 3.579545 MHz; CL = 20 pF. b) Motional capacitance C1 = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal). c) Parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal). The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. Philips Components has developed a special crystal which is tuned to the correct frequency in an application without series capacitance (code number 9922 520 0038X; see Table 43). This has the advantage that the tuning (catching) range is increased with approximately 50% without negative effects on spurious responses. When the catching range of 300 Hz is considered too low this special crystal is a suitable alternative. The free-running frequency of the oscillator can be checked by opening the colour PLL via the I2C-bus. In that condition the colour killer is not active so that the frequency off-set is visible on the screen. When two crystals are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator switching continuously between the two frequencies.

January 1995

31

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

26. The (RY) and (BY) signals are demodulated with a phase difference of the reference carrier of 90 and a gain ratio ( B Y) -------------------- = 1.78. The matrixing to the required signals is achieved in the control part. ( R Y) 27. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz. 28. At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input. 29. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 30. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a result the black-current of each gun is adapted to the white point setting so that the back-ground colour will follow the white point adjustment. Table 42 Output current of the phase detector in the various conditions I2C-BUS COMMANDS VID 0 POC 0 0 0 0 0 0 1 FOA 0 0 0 0 1 FOB 0 0 1 1 IC CONDITIONS IDENT yes yes yes yes yes no COIN yes no yes no NOISE yes SCAN 30 180 30 180 180 6 -1 CURRENT/MODE V-RETR 30 270 30 270 270 6 GATING yes no yes no no no MODE auto auto slow slow fast OSD off

Table 43 Code numbers for special crystals SYSTEM PAL-N NTSC-M PAL-M PAL-B/G FREQUENCY (MHz) 3.582056 3.579545 3.575611 4.433619 CODE NUMBER 9922 520 00381 9922 520 00382 9922 520 00383 9922 520 00384

January 1995

32

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

MLA738 - 1

MLA739 - 1

50 (%) 30 (deg)

50

30

10

10

10

10

30

30

50

F 10 DAC (HEX)

50

10

20

30 40 DAC (HEX)

Overshoot in direction black.

Fig.5 Peaking control curve.

Fig.6 Hue control curve.

MLA741 - 1 MLA740 - 1

250 (%) 225 200 175 150 125 100 75 50 25 0 0 10 20 30 40 DAC (HEX)

100 (%) 90 80 70 60 50 40 30 20 10 0 10 20 30 40 DAC (HEX)

Fig.7 Saturation control curve.

Fig.8 Contrast control curve.

January 1995

33

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

MLA742 - 1

0.7 (V)
MBC212

0.35 16 %

100% 92%

0.35

30% for negative modulation 100% = 10% rest carrier

0.7 0 0 10 20 30 40 DAC (HEX)

Relative variation with respect to the measuring pulse.

Fig.9 Brightness control curve.

Fig.10 Video output signal.

handbook, full pagewidth

MBC211

100% 86% 72% 58% 44% 30% 10 12 22 26 32 36 40 44 48 52 56 60 64 s

Fig.11 Test signal waveform.

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

handbook, full pagewidth

3.2 dB 10 dB 13.2 dB 30 dB 13.2 dB 30 dB

SC CC BLUE

PC

SC CC YELLOW

PC
MBC213

PC

SC

ATTENUATOR

TEST CIRCUIT

SPECTRUM ANALYZER

CC

gain setting adjusted for blue


MBC210

Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier. All amplitudes with respect to top sync level. V O at 3.58 or 4.4 MHz Value at 0.92 or 1.1 MHz = 20 log ----------------------------------------------------------- + 3.6 dB V O at 0.92 or 1.1 MHz V O at 3.58 or 4.4 MHz Value at 2.66 or 3.3 MHz = 20 log ----------------------------------------------------------V O at 2.66 or 3.3 MHz

Fig.12 Test set-up intermodulation.

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Philips Semiconductors

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I2C-bus controlled PAL/NTSC TV processor


TEST AND APPLICATION INFORMATION

TDA8366

handbook, full pagewidth

QSS IF

BAND PASS STEREO AND CONTROL BAND PASS

L R SCL SDA

from tuner

SAW FILTER 2

SOUND TRAP 11 47 and 46 4

CVBS/Y CVBS EXT CHROMA 15 9 8 5 6

RI GI BI

RGBIN

21 22 23 24 19 18 17 RO GO BO BLKIN BCLIN EWD VDR (pos) VDR (neg) HOUT FBI

IFDEM2 2

16 20

TDA8366
1 IFDEM1

43 44 45 38 39

33 4.4 MHz 3.6 MHz

32

36

31 RYO

28 27 BYO

30 RYI

29 BYI

37 SCO to text decoder

CVBS/ SEC ref TXT

TDA8395

TDA4661

MLA746 - 1

Fig.13 Application diagram.

East-West output stage In order to obtain correct tracking of the vertical and horizontal EHT-correction, the EW output stage should be dimensioned as illustrated in Fig.14. Resistor REW determines the gain of the EW output stage. Resistor Rc determines the reference current for both the vertical sawtooth generator and the geometry processor.

The preferred value of Rc is 39 k which results in a reference current of 100 A (Vref = 3.9 V). The value of REW must be: V scan R EW = R c ---------------------18 V ref Example: With Vref = 3.9 V; Rc = 39 k and Vscan = 120 V then REW = 68 k.

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

handbook, full pagewidth

VDD

HORIZONTAL DEFLECTION STAGE R ew

V scan

TDA8366
43 EWD EW output stage DIODE MODULATOR V EW

50 Rc 39 k (2%) I ref V ref

49 C saw 100 nF (5%)

MLA744 - 1

Fig.14 East-West output stage.

VA = 0, 31H and 63H; VSH = 31H; SC = 0.

VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.

Fig.15 Control range of vertical amplitude.

Fig.16 Control range of vertical slope.

January 1995

37

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

VSH = 0, 31H and 63H; VA = 31H; SC = 0.

SC = 0, 31H and 63H; VA = 31H; VHS = 31H.

Fig.17 Control range of vertical shift.

Fig.18 Control range of S-correction.

EW = 0, 31H and 63H; PW = 31H; CP = 31H.

PW = 0, 31H and 63H; EW = 31H; CP = 31H.

Fig.19 Control range of EW width.

Fig.20 Control range of EW parabola/width ratio.

January 1995

38

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

CP = 0, 31H and 63H; EW = 31H; PW = 63H.

TC = 0, 31H and 63H; EW = 31H; PW = 31H.

Fig.21 Control range of EW corner/parabola ratio.

Fig.22 Control range of EW trapezium correction.

January 1995

39

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


Adjustment of geometry control parameters The deflection processor of the TDA8366 offers nine control parameters for picture alignment: Vertical picture alignment S-correction vertical amplitude vertical slope vertical shift Horizontal picture alignment horizontal shift EW width EW parabola/width EW corner/parabola EW trapezium correction. It is important to notice that the TDA8366 is designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and therefore not available). For a particular combination of picture tube type, vertical output stage and EW output stage it is determined which are the required values for the settings of S-correction, EW parabola/width ratio and EW corner/parabola ratio. These parameters can be preset via the I2C-bus, and do not need any additional adjustment. The rest of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV-set adjustments. The vertical shift control is meant for compensation of off-sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in first order approximation proportional to the value of the off-set, and to the square of the S-correction needed. The necessity to use the vertical shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the S-correction, and on the demands upon vertical linearity.

TDA8366
For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SBL bit HIGH. In this mode the RGB-outputs are blanked during the second half of the picture. There are 2 different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed. The top of the picture is placed by adjustment of the vertical amplitude, and the bottom by adjustment of the vertical slope. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrical with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the right setting and should not be changed. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1F). Then the top of the picture is placed by adjustment of the vertical amplitude and the bottom by adjustment of the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjustment of the EW width and the horizontal shift. Finally (if necessary) the left- and right-hand sides of the picture are aligned in parallel by adjusting the EW trapezium control. After adjustment of the picture for normal vertical deflection as described, no additional adjustment is necessary for the compress and expand mode. If required a small correction of the picture height can be made by adjusting the vertical slope. This will not effect the linearity.

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


PACKAGE OUTLINES

TDA8366

handbook, full pagewidth

seating plane

47.92 47.02 4.57 5.08 max max

15.80 15.24

3.2 2.8

0.51 min 1.73 max 1.778 (25x) 0.53 max 0.18 M 0.32 max 15.24 1.3 max 17.15 15.90
MSA267

52

27

14.1 13.7

26

Dimensions in mm.

Fig.23 Plastic shrink dual in-line package; 52 leads (600 mil) SDIP52; SOT247-1.

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor

TDA8366

handbook, full pagewidth

seating plane

0.10 S 18.2 17.6

B 52 51

64 1 pin 1 index

1.2 (4x) 0.8 1.0

0.20 M B 0.50 0.35 19 20 0.50 0.35 14.1 13.9 32 1.2 (4x) 0.8 33 0.20 M A

20.1 24.2 19.9 23.6

1.0

2.90 2.65

1.4 1.2 0.25 0.05 0.25 0.14 3.2 2.7

1.0 0.6 detail X

0 to 7 o
MSA327

Dimensions in mm.

Fig.24 Plastic quad at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm. January 1995 42

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic quad at-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C.

TDA8366
A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


DEFINITIONS Data sheet status Objective specication Preliminary specication Product specication Limiting values

TDA8366

This data sheet contains target or goal specications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains nal product specications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specication. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

January 1995

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Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


NOTES

TDA8366

January 1995

45

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


NOTES

TDA8366

January 1995

46

Philips Semiconductors

Objective specication

I2C-bus controlled PAL/NTSC TV processor


NOTES

TDA8366

January 1995

47

Philips Semiconductors a worldwide company


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For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD36 Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands


533061/1500/01/pp48 Document order number: Date of release: January 1995 9397 745 80011

Philips Semiconductors