100331 Low Power Triple D Flip-Flop

July 1992

100331 Low Power Triple D Flip-Flop

General Description
The 100331 contains three D-type edge-triggered master slave flip-flops with true and complement outputs a Common Clock (CPC) and Master Set (MS) and Master Reset (MR) inputs Each flip-flop has individual Clock (CPn) Direct Set (SDn) and Direct Clear (CDn) inputs Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH The Master Set Master Reset and individual CDn and SDn inputs override the Clock inputs All inputs have 50 kX pull-down resistors

Features
Y Y Y Y

Y Y

35% power reduction of the 100131 2000V ESD protection Pin function compatible with 100131 Voltage compensated operating range e b4 2V to b 5 7V Available to industrial grade temperature range Available to MIL-STD-883

Logic Symbol
Pin Names CP0 CP2 CPC D0 D2 CD0 CD2 SDn MR MS Q0-Q2 Q0 Q2
TL F 10262 1

Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs

Connection Diagrams
24-Pin DIP SOIC 28-Pin PCC 24-Pin Quad Cerpak

TL F 10262 3

TL F 102622

TL F 10262 4

C1995 National Semiconductor Corporation

TL F 10262

RRD-B30M105 Printed in U S A

Logic Diagram

TL F 10262 5

Truth Tables (Each Flip-Flop)

Synchronous Operation Inputs Dn L H L H X X X CPn L L L L L H X CPC L L L L L X H MS SDn L L L L L L L MR CDn L L L L L L L Outputs Qn(t a 1) L H L H Qn(t) Qn(t) Qn(t) Dn X X X CPn X X X Asynchronous Operation Inputs CPC X X X MS SDn H L H MR CDn L H H Outputs Qn(t a 1) H L U

H e HIGH Voltage Level L e LOW Voltage Level X e Dont Care U e Undefined t e Time before CP Positive Transition t a 1 e Time after CP Positive Transition L e LOW to HIGH Transition

Absolute Maximum Ratings

Above which the useful life may be impaired (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Pin Potential to Ground Pin (VEE) Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2)
a 175 C a 150 C b 7 0V to a 0 5V

Recommended Operating Conditions

Case Temperature (TC) Commercial Industrial Military Supply Voltage (VEE) 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C
b 5 7V to b 4 2V

VEE to a 0 5V
b 50 mA
s 2000V

Note 1 Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 ESD testing conforms to MIL-STD-883 Method 3015

Commercial Version DC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND TC e 0 C to a 85 C (Note 3) Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current
b 122 b 1165 b 1830

Min
b 1025 b 1830 b 1035

Typ
b 955 b 1705

Max
b 870 b 1620

Units mV mV mV

Conditions VIN e VIH (Max) or VIL (Min) VIN e VIH (Min) or VIL (Max) Loading with 50X to b2 0V Loading with 50X to b2 0V

b 1610 b 870 b 1475

mV mV mV mA

Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN e VIL (Min) VIN e VIH (Max) Inputs Open

05 240
b 65

mA mA

Note 3 The specified limits represent the worst case value for the parameter Since these values normally occur at the temperature extremes additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions

Commercial Version (Continued) DIP AC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND (Continued) Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Transition Time 20% to 80% 80% to 20% Setup Time Dn CDn SDn (Release Time) MS MR (Release Time) Hold Time Dn Pulse Width HIGH CPn CPC CDn SDn MR MS Propagation Delay MS MR to Output Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn SDn to Output TC e 0 C Min 375 0 75 0 75 0 70 0 70 1 10 1 10 0 35 0 40 1 30 2 30 05 2 00 2 00 2 00 1 70 2 00 2 60 2 80 1 30 Max TC e a 25 C Min 375 0 75 0 75 0 70 0 70 1 10 1 10 0 35 0 40 1 30 2 30 05 2 00 2 00 2 00 1 70 2 00 2 60 2 80 1 30 Max TC e a 85 C Min 375 0 75 0 75 0 70 0 70 1 10 1 10 0 35 0 40 1 30 2 30 07 2 00 2 00 2 00 1 80 ns 2 00 2 60 ns 2 80 1 30 ns CPn CPC e H CPn CPC e H CPn CPC e L Max Units MHz ns Conditions

Figures 2 and 3 Figures 1 and 3

ns CPn CPC e L

Figures 1 and 4

Figures 1 3 and 4 Figure 5

ns

Figure 4
ns ns

tH tpw(H)

Figure 5 Figures 3 and 4

SOIC PCC and Cerpak AC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay MS MR to Output Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn SDn to Output TC e 0 C Min 400 0 75 0 75 0 70 0 80 1 10 1 10 1 80 1 80 1 50 1 80 2 40 2 60 Max TC e a 25 C Min 400 0 75 0 75 0 70 0 70 1 10 1 10 1 80 1 80 1 50 1 80 2 40 2 60 Max TC e a 85 C Min 400 0 75 0 75 0 70 0 70 1 10 1 10 1 80 1 80 1 60 ns 1 80 2 40 ns 2 60 CPn CPC e H CPn CPC e H CPn CPC e L Max Units MHz ns Conditions

Figures 2 and 3 Figures 1 and 3

ns CPn CPC e L

Figures 1 and 4

Commercial Version (Continued) SOIC PCC and Cerpak AC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND (Continued) Symbol tTLH tTHL tS Parameter Transition Time 20% to 80% 80% to 20% Setup Time Dn CDn SDn (Release Time) MS MR (Release Time) Hold Time Dn Pulse Width HIGH CPn CPC CDn SDn MR MS Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn SDn to Output TC e 0 C Min 0 35 0 30 1 20 2 20 05 2 00 0 75 0 70 0 70 0 80 Propagation Delay MS MR to Output 1 10 1 20 Maximum Skew Common Edge Output-to-Output Variation Common Clock to Output Path Maximum Skew Common Edge Output-to-Output Variation CPn to Output Path Maximum Skew Common Edge Output-to-Output Variation Common Clock to Output Path Maximum Skew Common Edge Output-to-Output Variation CPn to Output Path Maximum Skew Opposite Edge Output-to-Output Variation Common Clock to Output Path Maximum Skew Opposite Edge Output-to-Output Variation CPn to Output Path Maximum Skew Pin (Signal) Transition Variation Common Clock to Output Path Maximum Skew Pin (Signal) Transition Variation CPn to Output Path 1 40 1 40 1 50 1 70 2 00 2 10 100 Max 1 10 TC e a 25 C Min 0 35 0 30 1 20 2 20 05 2 00 0 75 0 75 0 70 0 80 1 10 1 20 1 40 1 40 1 50 1 70 2 00 2 10 100 Max 1 10 TC e a 85 C Min 0 35 0 30 1 20 2 20 07 2 00 0 80 0 80 0 80 0 80 1 20 1 30 1 50 1 50 1 60 ns 1 80 2 10 ns 2 20 100 ps Max 1 10 Units ns Conditions

Figures 1 3 and 4 Figure 5

ns

Figure 4
ns ns ns ns

tH tpw(H)

Figure 5 Figures 3 and 4

tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tOSHL

Figures 1 and 3 PCC Only

CPn CPC e L PCC Only CPn CPC e H PCC Only CPn CPC e L PCC Only CPn CPC e H PCC Only PCC Only (Note 1) PCC Only (Note 1) PCC Only (Note 1) PCC Only (Note 1) PCC Only (Note 1) PCC Only (Note 1) PCC Only (Note 1) PCC Only (Note 1)

Figures 1 and 4

tOSHL

235

235

235

ps

tOSLH

120

120

120

ps

tOSLH

275

275

275

ps

tOST

125

125

125

ps

tOST

265

265

265

ps

tps

90

90

90

ps

tps

90

90

90

ps

Note 1 Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both HL and LH (tOST) Parameters tOST and tps guaranteed by design

Industrial Version PCC DC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND TC e b40 C to a 85 C (Note) Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current
b 122 b 1170 b 1830

TC e b40 C Min
b 1085 b 1830 b 1095 b 1565 b 870 b 1480

TC e 0 C to a 85 C Min
b 1025 b 1830 b 1035 b 1610 b 1165 b 1830 b 870

Units mV mV mV mV mV mV mA

Conditions VIN e VIH (Max) or VIL (Min) VIN e VIH (Min) or VIL (Max) Loading with 50X to b2 0V Loading with 50X to b2 0V

Max
b 870 b 1575

Max
b 870 b 1620

Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN e VIL (Min) VIN e VIH (Max) Inputs Open

1475

05 300
b 60

05 240
b 122 b 65

mA mA

Note The specified limits represent the worst case value for the parameter Since these values normally occur at the temperature extremes additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions

PCC AC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Transition Time 20% to 80% 80% to 20% Setup Time Dn CDn SDn (Release Time) MS MR (Release Time) Hold Time Dn Pulse Width HIGH CPn CPC CDn SDn MR MS Propagation Delay MS MR to Output Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn SDn to Output TC e b40 C Min 375 0 75 0 70 0 60 0 70 1 10 1 10 0 20 1 80 1 80 1 50 1 80 2 40 2 60 1 40 Max TC e a 25 C Min 400 0 75 0 75 0 70 0 70 1 10 1 10 0 35 1 80 1 80 1 50 1 80 2 40 2 60 1 10 Max TC e a 85 C Min 400 0 75 0 75 0 70 0 70 1 10 1 10 0 35 1 80 1 80 1 60 ns 1 80 2 40 ns 2 60 1 10 ns CPn CPC e H CPn CPC e H CPn CPC e L Max MHz ns Units Conditions

Figures 2 and 3

Figures 1 and 3
ns CPn CPC e L

Figures 1 and 4

Figures 1 3 and 4 Figure 5

1 00 1 50 2 50 07 2 00

0 30 1 20 2 20 05 2 00

0 30 1 20 2 20 07 2 00

ns

Figure 4
ns ns

tH tpw(H)

Figure 5 Figures 3 and 4

Military Version DC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND TC e b55 C to a 125 C Symbol VOH Parameter Output HIGH Voltage Min
b 1025 b 1085

Max
b 870 b 870 b 1620 b 1555

Units mV mV mV mV mV mV

TC 0 C to a 125 C
b 55 C

Conditions

Notes

VOL

Output LOW Voltage

b 1830 b 1830

0 C to a 125 C
b 55 C

VIN e VIH (Max) or VIL (Min)

Loading with 50X to b2 0V

1 2 3

VOHC

Output HIGH Voltage

b 1035 b 1085

0 C to
a 125 C b 55 C

VOLC

Output LOW Voltage

b 1610 b 1555

mV mV mV mV mA

0 C to a 125 C
b 55 C b 55 C to a 125 C b 55 C to a 125 C b 55 C to a 125 C

VIN e VIH (Min) or VIL (Max)

Loading with 50X to b2 0V

1 2 3

VIH VIL IIL IIH

Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current

b 1165 b 1830

b 870 b 1475

Guaranteed HIGH Signal for all Inputs Guaranteed LOW Signal for all Inputs VEE e b4 2V VIN e VIL (Min) VEE e b5 7V VIN e VIH (Max) Inputs Open

1 2 3 4 1 2 3 4 1 2 3

0 50 240 340

mA mA mA

0 C to
a 125 C b 55 C b 55 C to a 125 C

1 2 3

IEE

Power Supply Current

b 130

b 50

1 2 3

Note 1 F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C) then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up This provides cold start specs which can be considered a worst case condition at cold temperatures Note 2 Screen tested 100% on each device at b 55 C a 25 C and a 125 C Subgroups 1 2 3 7 and 8 Note 3 Sampled tested (Method 5005 Table I) on each manufactured lot at b 55 C a 25 C and a 125 C Subgroups A1 2 3 7 and 8 Note 4 Guaranteed by applying specified input condition and testing VOH VOL

Military Version (Continued) AC Electrical Characteristics

VEE e b4 2V to b5 7V VCC e VCCA e GND Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL ts Transition Time 20% to 80% 80% to 20% Setup Time Dn CDn SDn (Release Time) MS MR (Release Time) Hold Time Dn Pulse Width HIGH CPn CPC CDn SDn MR MS Propagation Delay MS MR to Output Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn SDn to Output TC e b55 C Min 400 0 50 0 50 0 50 0 50 0 70 0 70 0 20 2 20 2 20 2 20 2 40 2 70 2 90 1 40 Max TC e a 25 C Min 400 0 60 0 60 0 60 0 60 0 80 0 80 0 20 2 00 2 00 2 00 2 10 2 60 2 80 1 40 Max TC e a 125 C Min 400 0 50 0 50 0 50 0 50 0 80 0 80 0 20 2 40 2 40 2 40 ns 2 50 2 90 ns 3 10 1 40 ns CPn CPC e H CPn CPC e H CPn CPC e L Max MHz Figures 2 and 3 ns 4 Units Conditions Notes

Figures 1 and 3
ns CPn CPC e L

Figures 1 2 3 1 and 4

Figures 1 3 and 4 Figure 5

1 00 1 50 2 50 1 50 2 00

0 80 1 30 2 30 1 30 2 00

0 90 1 60 2 50 1 60 2 00

ns

Figure 4
ns ns

th tpw(H)

Figure 5 Figures 3 and 4

Note 1 F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C) then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up This provides cold start specs which can be considered a worst case condition at cold temperatures Note 2 Screen tested 100% on each device at a 25 C Temperature only Subgroup A9 Note 3 Sample tested (Method 5005 Table I) on each Mfg lot at a 25 C Subgroup A9 and at a 125 C and b 55 C Temp Subgroups A10 and A11 Note 4 Not tested at a 25 C a 125 C and b 55 C Temperature (design characterization data)

Test Circuits

TL F 10262 6

FIGURE 1 AC Test Circuit

TL F 10262 7

FIGURE 2 Toggle Frequency Test Circuit

Notes VCC VCCA e a 2V VEE e b 2 5V L1 and L2 e Equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0 1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Fixture and stray capacitance s 3 pF

Switching Waveforms

TL F 10262 8

FIGURE 3 Propagation Delay (Clock) and Transition Times

TL F 10262 9

FIGURE 4 Propagation Delay (Resets)

TL F 10262 10

FIGURE 5 Data Setup and Hold Time

Note ts is the minimum time before the transition of the clock that information must be present at the data input Note th is the minimum time after the transition of the clock that information must remain unchanged at the data input

10

Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 100331 D C QB Device Type (Basic) Package Code D e Ceramic DIP F e Quad Cerpak Q e Plastic Leaded Chip Carrier (PCC) P e Plastic DIP S e Small Outline (SOIC) Special Variation QB e Military grade device with environmental and burn-in processing Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC Only) M e Military (b55 C to a 125 C)

11

Physical Dimensions inches (millimeters)

24-Lead Ceramic Dual-In-Line Package (0 400 Wide) (D) NS Package Number J24E

24-Lead Molded Package (0 300 Wide) (S) NS Package Number M24B

12

Physical Dimensions inches (millimeters) (Continued)

24-Lead Plastic Dual-In-Line Package (P) NS Package Number N24E

28-Lead Plastic Chip Carrier (Q) NS Package Number V28A

13

100331 Low Power Triple D Flip-Flop

Physical Dimensions inches (millimeters) (Continued)

Lit

114912

24-Lead Quad Cerpak (F) NS Package Number W24B

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