2: Transistors, Fabrication, Layout

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2: Transistors, Fabrication, Layout

J. A. Abraham
60 Department
of Electrical and Computer Engineering The University of Texas at Austin EE 382M, VLSI I Fall 2010
August 30, 2010
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ECE Department, University of Texas at Austin
Lecture 2: Transistors, Fabrication, Layout
J. A. Abraham, August 30, 2010
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Conductivity in Silicon Lattice

Look at the behavior of crystalline silicon mmtemperatures close to 60 K, electrons in outermost shell 40 80 100 At 0 tightly bound (insulator) At higher temps., (300 K), some electrons have thermal energy to break covalent bonds
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The Elements (Periodic Table)

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Build Systems with Information on Electrical Characteristics of Building Blocks (Transistors)

40 60 80 100 Thismm course will not cover semiconductor physics Learn this from other courses in the department 120
We will design VLSI circuits knowing the electrical behavior of the transistors
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Dopants
Used to selectively change the conductivity of silicon Silicon is a semiconductor mm 40 60 80 100 Pure silicon has no free carriers and conducts poorly Adding dopants impurities to pure silicon increases the conductivity
40 Group V: extra electron (n-type) 120
Group III: missing electron, called hole (p-type)

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p-n Junctions
Diodes mm 40 60 80 100 120 A junction between p-type and n-type semiconductor forms a diode Current ows only in one direction
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nMOS Transistor
Four-Terminal device: gate, source, drain, body mm oxide 40 60 80 Gate body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor, even 40 though gate material changed to polysilicon Latest gate material in Intel 45 nm process is back to metal
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nMOS Transistor Operation

Body (bulk) is commonly tied to Ground (0 V)
mm When the gate is 40 a low voltage at 60 P-type body is at low voltage 80 100 120
Source-body and drain-body diodes are OFF No current ows, transistor is OFF
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When the gate is at a high voltage Positive charge on gate of MOS 60 capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now 80 electrons can ow through n-type silicon from source through channel to drain, transistor is ON
ECE Department, University of Texas at Austin Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 30, 2010 7 / 42
pMOS Transistor
Similar to nMOS transistor, but doping and voltages reversed
mm tied to 40 Body high voltage60 (VDD) 80 100 120
Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior 40
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CMOS Fabrication
Silicon technology CMOS transistors are fabricated on silicon wafer 100 mm 40 60 80 Lithography process similar to printing press On each step, dierent materials are deposited or etched Easiest to understand by viewing both top and cross-section 40 of wafer in a simplied manufacturing process Example inverter cross-section Typically use p-type substrate for nMOS transistors
60 Requires n-well for body of pMOS transistors
A GND Y VDD SiO2 n+ diffusion
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n+
n+ p substrate
p+ n well
p+
p+ diffusion polysilicon metal1
nMOS transistor
pMOS transistor
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Well and Substrate Taps

Substrate contacts are critical to correct operation of CMOS Substrate must be tied to GND, n-well to VDD 100 mm 40 60 80 (reverse-biased diodes isolate regions) Metal to lightly-doped semiconductor forms poor connection called Schottky Diode use heavily doped well and substrate contacts/taps 40
A GND Y VDD
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p+ n+ n+ p substrate substrate tap p+ n well p+ n+
well tap
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Inverter Masks
Transistors and wires are dened by masks mm Cross-sections shown above taken along dashed line 40 60 80 100
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Examples of Fabrication Steps

Start mm with blank wafer 40
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Build inverter from the bottom up First step is to form the n-well
40 Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built Implant or diuse n dopants into exposed wafer Strip o SiO2 60
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Oxidation and Photoresist

Grow SiO2 on top of Si wafer mm 1200 C with H60 or O2 in 80 900 oxidation furnace 40 100 2O
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Spin-on photoresist Photoresist is a light-sensitive organic polymer which softens 60 where exposed to light (positive resist)
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Lithography
Use light to transfer a pattern to the wafer Expose photoresist through n-well mask (using UV light mm 40 60 80 100 example 193 nm wavelength)
Immersion lithography used in some nanoscale processes 120
Strip o exposed photoresist

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Interesting physics problem How can we print a 45 nm feature using light with a 80 wavelength of 193 nm? Signicant distortion of the image!
Trend in Integrated Circuit Feature Sizes

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Features Smaller than Wavelength of Light Used

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Optical Proximity Correction (OPC)

What you see is NOT what you get
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Etch and Strip Photoresist

Etch oxide with Hydrouoric acid (HF) Only oxide where60 resist has been exposed 100 mm attacks 40 80
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Strip remaining photoresist using mixture of acids (piranha etch) Necessary so resist does not melt in the next step
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n-Well
Formed using ion implant (used to be diusion)
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Bombard wafer with As ions, which only enter exposed Si

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(With diusion, wafer is placed in a furnace with As gas) Remaining oxide is then stripped o using HF, and it is back to the bare wafer, but with an n-well
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Subsequent steps repeat the above process

Polysilicon
Very thin layer of gate oxide is grown on wafer mm oxide thickness is <60 (few atomic layers) 40 80 100 Gate 20A One of the most critical steps in fabrication process Polysilicon deposited on top of gate oxide Grown using Chemical vapor deposition (CVD) Wafer placed in furnace with Silane (SiH) gas Small crystals (polysilicon) formed on wafer Heavily doped to be a good conductor 60
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Polysilicon Patterning
Use same lithography processing to pattern polysilicon Reactive Ion 40 (RIE) process Etch mm 60
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Charge buildup on un-etched polysilicon can lead to antenna eects and damage gate oxide
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Self-aligned process 80 Polysilicon blocks dopants where the channel should be formed
N+ Diusion
nMOS transistors are formed Oxide mm is patterned to form the n+ regions 40 60 80
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N+ diusion forms nMOS source, drain, and n-well contact
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N+ Diusion, Contd
Ion implantation used to dope silicon n+ mm regions are formed 60 40
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Oxide is stripped o to complete patterning step
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P+ Diusion
mm 40 60 80 A similar set of steps is used to form the p+ diusion 100 regions for 120 the pMOS transistor source and drain as well as the substrate contact 40
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Contacts
mm Points where the 40 level of 60 rst metal contacts the transistors 80 100 Used to wire the devices together 120
Wafer is covered with thick eld oxide Oxide is etched where the contact cuts are needed
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Metalization
Used to interconnect internal nodes mm 40 60 Aluminum was the traditional metal 80 Aluminum is sputtered over the entire wafer Patterned to remove excess metal, leaving the wires
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Switch to Copper for high performance processes
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Layout
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Describes actual layers and geometry on the silicon substrate to implement a function Need to dene transistors, interconnection
40 Transistor widths (for performance) Spacing, interconnect widths, to reduce defects, satisfy power requirements Contacts (between poly or active and metal), and vias (between metal layers) Wells and their contacts (to power or ground)
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Layout of lower-level cells constrained by higher-level requirements: oorplanning

design iteration 80
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Layout, Contd
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Chips are specied with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) 40 Feature size f = distance between source and drain
Set by minimum width of polysilicon (= minimum drawn gate length)
Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f /2
e.g., = 0.3m in 0.6m process 80 60
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CMOS Inverter Layout

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Note: the N- and P- well are 80 100 120 not shown in the layout
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Other CMOS Layouts

Using wide transistors
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Using even wider transistors

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Buer with Two Inverters

Side by side
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Stacked
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Improving Layout Eciency

Flip a cell so that power (or ground) can be shared with another cell
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Stick Diagram and Simplied Layout of NAND Gate

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Stick diagrams identify actual layers (which a schematic does not); both can be annotated 40 with transistor sizes
n- and p-wells are shown
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Simplied Design Rules

Based on (popular in academia) Discussed in the textbook mm 40
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Rules based on can theoretically be migrated to a dierent technology (by changing the value of ); in practise, all the rules do not scale in the same way, and industry typically does not use rules 40
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Inverter Layout
Dimensions of pMOS and nMOS transistors
mm Dimensions specied as Width/Length ( W ) 40 60 80 L 100 120 Minimum size, 4/2, sometimes called unit-size transistor (pMOS transistors are typically designed to be about twice the width of nMOS transistors, because of the mobilities of holes and electrons) 40
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The MOSIS Scalable CMOS Rules

mm 40 60 100 MOSIS is a prototyping and small-volume 80 production service for VLSI circuit development MOSIS keeps costs down by combining many designs on a single die (multi-project chips) 40 Similar facilities exist in Europe (Europractice, CMP), Taiwan, etc. 120
-based rules Designs using these rules are fabricated by a variety of 60 companies Support for submicron digital CMOS, analog (buried poly layer for capacitor), micromachines, etc. http://www.mosis.com//Technical/Designrules/scmos/
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Nangate 45nm Open Cell Library

Used in the laboratory exercises mm is an open-source, standard-cell library 40 60 80 This
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To aid university research programs and other organizations in developing design ows, designing circuits and exercising new algorithms 40 Link to the wiki on the lab pages
Example: poly rules (note: summarized here)

Rule 1 2 3 4 5 6 Value 60 nm 50 140 nm 55 nm 70 nm 50 80 nm 75 nm Description Minimum width Minimum spacing Min. extension Min. enclosure Min. spacing Min. spacing
Lecture 2: Transistors, Fabrication, Layout J. A. Abraham, August 30, 2010 37 / 42
Example of Other Nangate 45nm Rules

mm Active Rules Rule 1 2 3 4 Contact Rule 1 2 3 4 5 6 7 Value 90 nm 80 nm 40 Rules Value 65 nm 60 75 nm 5 nm 5 nm 80 35 nm 90 nm 40 60 Description Minimum width Minimum spacing Min. well-active active inside 80 100 120
Description Minimum width Minimum spacing contact inside Min. active around Min. poly around Min. spacing with gate Min. spacing with poly
Trend Towards Reducing Number of Rules

Improve manufacturability Less mm exibility for designers 40 60
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Intel reduced the number of poly layout rules for logic layout in 45nm by 37% compared with the 65 nm process Highly regular layout greatly reduces lithographic distortions
40 Limit rules, thereby limiting the number of allowed structures and shape relationships Move towards 1-dimensional shapes and Gridded Design Rules (GDR)
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Example layout from Tela Innovations
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Regular Layout
Lithography simulations mm 60 80 Lithographic 40 distortions reduced signicantly with100 shapes 120 1-D and GDR Scan D Flip-Flop, 45nm process Source: Tela Innovations, Inc., ISPD 2009
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2D Conventional Layout
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1D GDR Layout
Copper and the Damascene Process

Source: UMC
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Layers of Damascene Copper (Intel)

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Copper Damascene Interconnect (Intel)

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Advanced Metalization
IBM Technology (in Rabaey, Digital Integrated Circuits, 2nd ed.) mm 40 60 First commercial Copper process 120 80 100 (0.12)
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2: Transistors, Fabrication, Layout

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Conductivity in Silicon Lattice

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

The Elements (Periodic Table)

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Build Systems with Information on Electrical Characteristics of Building Blocks (Transistors)

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Group III: missing electron, called hole (p-type)

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

nMOS Transistor Operation

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

p+ diffusion polysilicon metal1

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Well and Substrate Taps

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Examples of Fabrication Steps

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Oxidation and Photoresist

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Strip o exposed photoresist

Trend in Integrated Circuit Feature Sizes

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Features Smaller than Wavelength of Light Used

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout

J. A. Abraham, August 30, 2010

Optical Proximity Correction (OPC)

ECE Department, University of Texas at Austin

Lecture 2: Transistors, Fabrication, Layout