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Code No: 54203/MT

NR
M.Tech. – II Semester Regular Examinations, September, 2008

CPLD & FPGA ARCHITECTURE & APPLICATIONS


(Embedded Systems)

Time: 3hours Max. Marks:60

Answer any FIVE questions


All questions carry equal marks
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1.a) Compare PALs, PLDs and PGAs in all respects.


b) Give the architectures of PLAs and ROMs and discuss about the
advantages and disadvantages of both types of devices.

2.a) Describe the architectural features of cypros FLASH 370 devices


and mention the salient features of the device technology.
b) Discuss about the features of AMDs’ CPLD devices.

3.a) Give the design flow using FPGAs. What are the various large
blockers of FPGAs? Explain.
b) Draw the architecture of xi linx XC 4000 series FPGA and explain
about the salient features.

4.a) Explain about state transition tables and state assignments for
FPGAs.
b) What is the alternative realization for state machine chart?

5.a) Explain about state machine designs centred around shift


registers.
b) Explain about one – hot design method.

6. Give the salient features and explain about the mentor graphics
EDA tool FPGA advantage.

7. Give the design flow for parallel Adder cells and counters using
mentor graphics EDA toll?

8. Write notes on any Two


(a) AT or T – ORCA
(b) Linked state machines
(c) Metastability and synchronization.

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