HIGH-SPEED PHOTODETECTORS AND RECEIVERS FOR LONG-HAUL COMMUNICATION SYSTEMS

A Dissertation

Submitted to the Graduate School of the University of Notre Dame in Partial Fulllment of the Requirements for the Degree of

Doctor of Philosophy

by

Rajkumar Sankaralingam, M.S.

Patrick J. Fay, Director

Graduate Program in Electrical Engineering Notre Dame, Indiana October 2005

HIGH-SPEED PHOTODETECTORS AND RECEIVERS FOR LONG-HAUL COMMUNICATION SYSTEMS

Abstract by Rajkumar Sankaralingam For long-haul ber-optic communication systems, the development of ecient high-speed photodiodes and transistors compatible with each other is essential for monolithic integration. This dissertation details the design, fabrication, and characterization of InP-based photodiodes and HEMTs suitable for operating in the low-loss low-dispersion window of the optical bers used in telecommunication systems. High-speed photodiodes with bandwidths as high 60 GHz and a responsivity of 0.3 A/W have been achieved using a dual-depletion design. To achieve better bandwidth-eciency products, a novel drift-enhanced dual-absorption design was developed and demonstrated. Diodes fabricated with this design achieved bandwidths of 30 GHz with a responsivity of 0.82 A/W. Numerical and analytical analyses have been performed to understand the bandwidth limitations of these photodiodes to optimize their performance. Ultrafast HEMTs with cuto frequencies over 200 GHz have been demonstrated using a 0.1 m T-gate process. Non-linear models suitable for use in circuit simulators were developed to accurately describe the performance of both the photodiodes and the HEMTs. Using these models, a single-ended four-stage transimpedance amplier has been designed exhibiting a gain of 4.5 k with a 50 GHz bandwidth. A novel dierential

Rajkumar Sankaralingam transimpedance amplier utilizing the unique design of dual-absorption photodiodes was proposed and demonstrated. This design is shown to achieve improved responsivity-bandwidth product compared to conventional designs.

CONTENTS

FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv viii ix 1 8 12 15 16 18 19 23 23 28 29 30 32 35 40 47 51 64 72 75 76 84

ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . CHAPTER 1: INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . CHAPTER 2: PHOTODETECTORS . . . . . . . . . . . 2.1 Conventional PIN photodetectors . . . . . . . . . 2.1.1 Fabrication and process ow . . . . . . . . 2.1.2 Experimental setup . . . . . . . . . . . . . 2.1.3 Experimental results . . . . . . . . . . . . 2.2 Drift-enhanced PIN photodetectors . . . . . . . . 2.2.1 Fabrication and process Flow . . . . . . . 2.2.2 Experimental results . . . . . . . . . . . . 2.3 Drift-enhanced dual-absorption PIN photodiodes . 2.3.1 Material structure . . . . . . . . . . . . . . 2.3.2 Fabrication and process Flow . . . . . . . 2.3.3 Experimental results . . . . . . . . . . . . 2.4 Device modeling . . . . . . . . . . . . . . . . . . . 2.5 Device simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 3: HIGH ELECTRON MOBILITY TRANSISTORS . . . . . . 3.1 Material structure, fabrication, and results . . . . . . . . . . . . . 3.2 Device modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHAPTER 4: PHOTORECEIVERS . . . 4.1 Transimpedance amplier design 4.1.1 Single-ended design . . . . 4.1.2 Dierential design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ii

CHAPTER 5: SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

91 91 92 93

iii

FIGURES

1.1 1.2 1.3 2.1 2.2

Optical absorption coecients for various photodetector materials [43, 47]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic diagram of stacked layer integration of PIN-HEMT structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic diagram of shared layer integration of PIN-HBT structure. Simple equivalent circuit of a PIN photodetector. . . . . . . . . . Bandwidth of a conventional PIN diode (junction area 248 m2 corresponding to 10 m optical window diameter) as a function of its absorption layer thickness. . . . . . . . . . . . . . . . . . . . . Material structure and band diagram of conventional PIN. . . . . Schematic cross-section of a PIN photodiode. . . . . . . . . . . . . Experimental setup used to measure the bandwidth and responsivity of photodetectors. . . . . . . . . . . . . . . . . . . . . . . . . . Area dependence of dark current. . . . . . . . . . . . . . . . . . . Normalized responsivity curve used to calculate bandwidth. . . . . Schematic of drift-enhanced PIN structure. . . . . . . . . . . . . . InGaAs electron (solid) and hole (dashed) drift velocities as a function of electric eld [53]. . . . . . . . . . . . . . . . . . . . . . . .

4 5 6 11

13 14 16 17 18 19 20 20

2.3 2.4 2.5 2.6 2.7 2.8 2.9

2.10 Material structure of drift-enhanced PINs used in this work (a) AA5000, (b) AA7000 with absorption layer thickness of 5000 and A respectively (c) TA5000 with a absorption layer thickness 7000 A of 5000 and InAlAs transparent anode layer. . . . . . . . . . . A 2.11 Band diagram of transparent anode TA5000. . . . . . . . . . . . . 2.12 Area dependence of dark current in fabricated devices. . . . . . . 2.13 DC photoresponse of transparent anode PIN (TA5000). . . . . . . 2.14 Bias dependence of device capacitance for TA5000. . . . . . . . . 2.15 Normalized responsivity curve of TA5000. . . . . . . . . . . . . . iv

22 22 24 24 25 26

2.16 Inverse area dependence of bandwidth. . . . . . . . . . . . . . . . 2.17 Bias dependence of bandwidth in AA7000. . . . . . . . . . . . . . 2.18 Dual absorption PINIP photodiode structure. . . . . . . . . . . . 2.19 Material structures: (a) Control design (b) Drift enhanced design. 2.20 Schematic cross-section of a dual-absorption photodiode. . . . . . 2.21 (a) Schematic representation of crystallographic mesa etch prole with respect to wafer ats (b) SEM image of mesa prole along [011] (b) along [011]. . . . . . . . . . . . . . . . . . . . . . . . . . 2.22 DC photoresponse of a typical drift-enhanced device showing responsivity of 0.82 A/W. . . . . . . . . . . . . . . . . . . . . . . . 2.23 Device capacitance as a function of area. . . . . . . . . . . . . . . 2.24 Frequency response of 6 m optical diameter devices showing the advantage of drift-layers in improving 3-dB bandwidth. . . . . . . 2.25 Measured bandwidth of drift-enhanced and control structures as a function of area; drift-enhanced structure exhibits improved bandwidths over control structure, up to 30% for 6 m optical diameter devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.26 Measured bandwidth of drift-enhanced devices as a function of inverse area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.27 Lumped element equivalent circuit used to describe photodiodes; Rd is the diode shunt resistance, Cj is the junction capacitance due to depletion, Rs is the series resistance of the diode (sum of contact resistance and bulk resistance), Ls is the total series inductance (mainly due to pads), Cp is the pad capacitance, and Cx is the launch capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . 2.28 Measured (dashed) and modeled (solid) s-parameters of TA5000 (10 m optical diameter device). . . . . . . . . . . . . . . . . . . . 2.29 Area dependence of modeled and theoretical junction capacitance in TA5000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.30 Schematic diagram showing the initial carrier distribution as result of impulse optical excitation. . . . . . . . . . . . . . . . . . . . . . 2.31 Electron drift velocities of InGaAs, InAs and GaAs as a function of electric eld. Light shaded area comprises data for In0.53 Ga0.47 As on InP substrates from dierent authors, dark shaded area refers to GaAs bulk values [7]. . . . . . . . . . . . . . . . . . . . . . . . 2.32 Simulated transit-time limited impulse response in TA5000. . . . .

27 28 29 30 31

33 34 34 35

36 36

37 38 38 40

43 43

2.33 Maximum BWE and corresponding total depletion width as a function of absorption layer thickness for drift-enhanced dual-absorption photodiode structure, as extracted from simulation. A peak BWE of 26 GHz is obtained. For W1 1.35 m, a dual-absorption structure without drift layer is optimal (W1 = W ). . . . . . . . . . . . 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Schematic cross-section of a typical InP-based HEMT. . . . . . . Schematic HEMT layer structure with (a) lattice matched channel (b) composite channel. . . . . . . . . . . . . . . . . . . . . . . . . SEM image showing end view of T-gates fabricated. . . . . . . . . Ids vs Vgs charactersitics of lattice matched HEMT with 0.3 m gate length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ids vs Vgs charactersitics of pseudomorphic HEMT with 0.3 m gate length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ids vs Vds charactersitics of pseudomorphic HEMTs with 0.3 m gate length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ft and fmax of 0.3 m gate length lattice matched HEMTs. . . . . ft and fmax of 0.3 m gate length pseudomorphic HEMTs. . . . .

45 49 52 53 55 55

Ids vs Vds charactersitics of lattice matched with 0.3 m gate length. 56 57 58 59 60 61 62 63 63 65 67 67 69 70 71

3.10 Material structure of modied lattice matched HEMT with reduced layer thicknesses and InP etch stop. . . . . . . . . . . . . . . . . . 3.11 SEM image showing end view of 0.1 m T-gates. . . . . . . . . . 3.12 Ids vs Vgs charactersitics of 0.1 m gate length device. . . . . . . . 3.13 Ids vs Vds charactersitics of 0.1 m gate length device. . . . . . . . 3.14 Current gain and Masons Unilateral power gain of 0.1 m gate length device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 EEHEMT circuit schematic [1]. . . . . . . . . . . . . . . . . . . . 3.16 Measured (symbols) and modeled (solid) Ids vs Vgs charactersitics. 3.17 Measured (symbols) and modeled (solid) Ids vs Vds charactersitics. 3.18 Measured (symbols) and modeled (solid) s-parameters for Vgs =0 V and Vds =1.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.19 Measured (symbols) and modeled (solid) s-parameters for Vgs =-0.2 V and Vds =1.3 V (corresponds to peak ft , high gain). . . . . . . . 3.20 Measured (symbols) and modeled (solid) s-parameters for Vgs =-0.5 V and Vds =1.3 V (low noise bias condition). . . . . . . . . . . . .

vi

4.1 4.2 4.3 4.4 4.5 4.6 4.7

Common receiver topologies: (a) low impedance design (b) high impedance design (c) transimpedance design. . . . . . . . . . . . . Simple feedback transimpedance amplier. . . . . . . . . . . . . . Feedback common source amplier with source follower output. . Transimpedance amplier with four amplifying stages. . . . . . . Transimpedance gain assuming open load. . . . . . . . . . . . . . Eye diagram of the output waveform for a 40 Gbps RZ PRBS pattern of length (231 1). . . . . . . . . . . . . . . . . . . . . . . . . (a) Output voltage magnitude of the transimpedance stages for a 1 mW incident optical power - Vo1 corresponds to the common gate stage followed by a source follower (top diode); Vo2 corresponds to a common gate amplier followed by a common source stage (bottom diode) (b) Vo1 and Vo2 showing a 180 broadband phase dierence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dierential transimpedance amplier using a drift-enhanced dualabsorption photodiode at the input. . . . . . . . . . . . . . . . . . Output voltage of the dierential amplier corresponding to 1 mW optical power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

73 76 77 80 81 84

87 88 89

4.8 4.9

4.10 Eye diagram for the dierential transimpedance amplier for a 40 Gbps PRBS pattern of length (231 1); each division corresponds to 50 mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

vii

TABLES

2.1 2.2 2.3 3.1 3.2 4.1

SUMMARY OF EQUIVALENT CIRCUIT PARAMETERS FOR 6 m OPTICAL WINDOW DIAMETER PHOTODIODES. . . . MATERIAL CHARACTERISTICS USED IN SIMULATION. . .

39 42

MEASURED AND MODELED RESULTS FOR 6 m OPTICAL DIAMETER DRIFT-ENHANCED DUAL-ABSORPTION DEVICE. 46 SUMMARY OF FABRICATED LM-HEMT AND P-HEMT RESULTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUMMARY OF DC AND RF RESULTS FOR THE MODIFIED LM-HEMT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STATUS OF HIGH-SPEED TRANSIMPEDANCE AMPLIFIERS. 60 64 85

viii

ACKNOWLEDGMENTS

I am indebted to Prof. Patrick Fay for his patience and guidance over the last ve years. I cannot thank him enough in words. A thesis advisor is lot like a parent for a graduate students intellectual and professional development. My advisor, Prof. Fay, did take his role very seriously. This work would not have been possible without the help of Mike Thomas, Mark Richmond, and Keith Darr. I deeply appreciate their dedication and am thankful for their patience in bearing me in spite of all my complaints!. I am grateful to Prof. Snider and Prof. Jena for helping me out with fruitful discussions whenever I ran into problems. I am thankful to them and Prof. Hall for being in my thesis committee. I am thankful to all my friends who endured me, I cherish their friendships and experiences far above any other aspect of my time at Notre Dame. I especially appreciate my parents and wife for their support and love, without whom I wouldnt have been able to get this far.

ix

CHAPTER 1 INTRODUCTION

A communication system is required to transfer information between two points over a distance. This information transfer is usually achieved by superimposing or modulating the information on to an electromagnetic wave that acts as a carrier for the information signal. In optical communication systems, the electromagnetic carrier is in the optical range of frequencies and the transmission is typically through optical bers. Since optical carrier frequencies are around 100 THz (near infrared), it yields a far greater potential transmission bandwidth than conventional metallic cable systems. Also, optical bers exhibit very low transmission loss compared to copper conductors, facilitating extremely wide repeater spacing (long transmission without intermediate electronics) for implemeting communication links, thus reducing system cost and complexity. Together with the modulation bandwidth capability of optical bers, this has made adoption of beroptics a necessity in the majority of long-haul telecommunication applications. In a typical ber-optic communication system, the intensity of a semiconductor laser is modulated by the input informational signal using an external modulator. This signal is launched onto a ber for transmission. At the other end, a photodetector converts the optical signal back to the message signal, which is then amplied before further processing.

The photodetector is an essential component of any optical ber communication system and is one of the crucial elements which dictates the overall system performance. When considering signal attenuation along the link, the system performance is determined at the detector. Hence, improvements in detector characteristics and performance lead to fewer repeaters and lowers both investment and maintenance costs. A photodetector is essentially a solid-state sensor that converts light energy into electrical energy, manifested usually in the form of photocurrent. Fundamentally, the generation of carriers is controlled by lled valence band states and available conduction band states separated by incident photon energy under the constraint of conservation of momentum. Since photons have negligible momentum (infrared), the conservation of momentum translates to transition of electron from valence band to conduction band with almost the same momentum. To facilitate such generation, conduction band minima should lie directly above valence band maxima in momentum space. Such materials are called direct bandgap materials. Absorption in indirect bandgap materials requires the assistance of a phonon (particle associated with lattice vibrations having a small energy and large momentum compared to photons) so that momentum as well as energy are conserved. Since the indirect absorption process involves a phonon in addition to the electron and photon, the probability of having an interaction take place involving all three particles will be lower than a simple electron-photon interaction in the direct absorption process. As a result, absorption is weaker in indirect bandgap materials necessitating thicker absorption layers which leads to higher transit times and hence lower bandwidths. Silicon and germanium, in spite of being indirect bandgap materials, are used

as detector materials for local area network applications. Silicon detectors are common for wavelengths from 0.4 to 1.0 m, while germanium detectors are used at longer wavelengths up to 1.8 m. For high performance long-haul communication III-V semiconductors are more common. In0.53 Ga0.47 As lattice matched to InP has a cuto wavelength of 1.65 m and is especially useful for telecommunication photodetectors as it includes both the 1.3 and 1.55 m windows, where the optical dispersion and attenuation in standard silica bers are at their respective minima. Also, very high speed optical modulators and lasers have been demonstrated in this wavelength region. In addition to favorable wavelength operation, both heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs) have been demonstrated in the InGaAs/InP material system, thus making it an ideal choice for meeting the demands of monolithically integrated long-haul communication systems. An integrated photoreceiver is made up of two key elements: photodetector and electronic amplier. Monolithically integrated receivers oer the advantage of potentially lower cost, lower parasitics and higher reliability compared to hybrid receivers. Independent of integration scheme, the choice of device technology for photoreceiver design is based on performance criteria like sensitivity, frequency response and noise. There are many dierent types of photodetectors possible with the most appropriate kind of detector being determined by the application. In high bit-rate optical communication systems, metal-semiconductor-metal (MSM), PIN, waveguide photodiodes (WGPDs) and avalanche photodiodes are most widely used. Of these, MSM diodes are the least complex but they have limited quantum eciency for high-speed operation. Avalanche photodiodes oer excellent sensitivity

Photon energy (eV)

5 4 3 2 1 0.9 0.8 0.7

1 108

1 107 Si 1 106 (m-1) 1 105 a-Si:H 1 104

Ge

In0.7Ga0.3As0.64P0.36 In0.53Ga0.47As GaAs InP

1 103
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Wavelength ( m) Absorption coefficient ( ) vs. wavelength ( ) for various semiconductors

Figure 1.1. Optical absorption coecients for various photodetector materials [43, 47].

due to internal gain but are inherently limited when it comes to high bandwidth. PIN diodes have excellent bandwidth with good linearity, noise performance, and sensitivity [5]. Conventional PIN diodes are top-illuminated and are easy to align to optical bers, but they suer from a trade-o between bandwidth and responsivity. WGPDs ease this constraint by side-illumination through a waveguide such that the light path and carrier path are perpendicular to each other. But, such freedom comes at the expense of increased complexity in ber alignment. Both conventional top-illuminated PIN diodes and WGPDs are actively pursued in OEICs for next generation high-speed communication systems [48], [22]. Due to packaging simplicity, we pursue top-illuminated PIN photodiodes in this work. When it comes to transistors, both HBTs and HEMTs have been successfully

integrated with PIN photodetectors [24], [22]. Both InP HBTs and HEMTs have been demonstrated with very high cuto frequencies - 604 GHz for HBTs [21], and 562 GHz for HEMTs [59]. When it comes to noise performance, although HBTs in general exhibit a lower 1/f noise than HEMTs, HEMTs exhibit exceptional highfrequency low-noise performance. Pseudomorphic HEMTs provide further reduced 1/f and generation-recombination noise. The high frequency noise performance of HEMTs is also enhanced by use of submicron gate lengths and low-resistance T-gate proles [28].

Photodiode p PIN layers i n HEMT n barrier channel buffer semiinsulating substrate HEMT layers

Figure 1.2. Schematic diagram of stacked layer integration of PIN-HEMT structure.

Monolithic integration of PINs and HEMTs is best implemented by a stacked layer structure. In general, for all HEMT based ampliers, HEMT layers are grown rst, followed by the detector layers as shown in Fig. 1.2. This is because the performance of the device on top is sometimes degraded due to imperfect insu-

HBT Photodiode p PIN layers i n n emitter p base i collector n subcollector semiinsulating substrate HBT layers

Figure 1.3. Schematic diagram of shared layer integration of PIN-HBT structure.

lating quality of the layers underneath it. In the case of photodetector this shows as dark current and hence increased shot noise. In the case of HEMTs, this shows as degraded parasitics which signicantly aects the power gain cuto frequency [15]. This can impose a signicant penalty while designing wide-band low noise ampliers. Since the dark current induced shot noise of PINs are expected to be insignicant compared to noise sources in the amplier, PIN layers are usually stacked on top of HEMT layers. In HBT based designs, this is less critical, but the conventional choice is to grow HBT layers on top of PIN layers. But stacking HBT and PIN layers makes processing dicult due to non planarity of the resulting structure. Hence, HBTs and PINs often share the base and collector regions as shown in Fig. 1.3 (see e.g. [20],[23]). PIN-HEMT photoreceivers oer exibility in terms of device design, as both transistor and photodetector heterostructures can be optimized independently. Hence, unlike shared layer PIN-HBT photoreceivers, devices can be optimized separately. Therefore, in this work, we focus on PIN-HEMT receivers due to their good cut-o frequencies, low-noise characteristics, as well as the design exibility and processing simplicity. 6

Though 40 Gbps PIN-HEMT receivers have been reported in literature, most of them use waveguide photodiodes and distributed ampliers. To make photoreceivers cost ecient, lumped element ampliers integrated with top-illuminated photodiodes would be more preferable. The goal of this thesis is to demonstrate that 40 Gbps performance can be achieved in such a conguration.

CHAPTER 2 PHOTODETECTORS

A photodetector is a transducer capable of producing an electrical signal in response to an optical signal. Semiconductor photodetectors rely on the absorption of incident photons with energy greater than the semiconductor bandgap energy to generate electron-hole pairs (EHPs). Photodetection broadly involves three processes: (1) absorption of optical energy and generation of carriers, (2) transportation of these photogenerated carriers away from the absorption region, (3) carrier collection and generation of photocurrent [4]. The performance of a photodetector can be characterized by various gures of merit. These include the responsivity of the detector, its bandwidth, and the noise added to the signal by the detector. Responsivity is a measure of light-to-current conversion eciency of the detector. Mathematically, the responsivity of a detector, Iph q = Pinc h , is given as

(2.1)

where q is the elementary charge, h is Plancks constant, is the frequency of incident light, Iph is the photocurrent, Pinc is the incident optical power, and is the external quantum eciency representing the fraction of incident photons leading to Iph . In reverse biased junction photodiodes where the depletion region (high

eld region) constitutes the bulk of the absorption region, can be approximated by

= i (1 R)(1 ed )

(2.2)

where R is the optical reectivity between air and the semiconductor, is the absorption coecient of the intrinsic region, d is the depletion region thickness and i is the internal quantum eciency dened as the ratio of number of EHPs created to the number of absorbed photons. In pure, defect free material, i is almost unity. A high detector responsivity improves the signal-to-noise ratio of the receiver system. It is possible to have gain in photodetectors (as in avalanche photodetectors) due to impact ionization and avalanche multiplication that can lead to very high responsivities. But these mechanisms are usually accompanied by a penalty in bandwidth and noise performance [14]. The bandwidth of a photodetector is dened as the frequency at which the responsivity of the detector has fallen o by 3-dB from its low frequency value. It is limited mainly by carrier transit time, RC time constant, diusion current and carrier piling at heterointerfaces [6]. Carrier transit time is the time taken by photogenerated carriers to travel across the high-eld region. It is usually dominated by hole transit time, as holes typically have a lower drift velocity than electrons in common photodetector materials. The RC time constant is determined by the equivalent circuit parameters of the photodiode. Diode series resistance (due to ohmic contacts and bulk resistances), load impedance, and the junction and parasitic capacitances contribute to the RC time constant. Diusion current becomes important when the photocurrent due to carriers absorbed in the p and n con-

tact regions within about one diusion length of the edge of the depletion region becomes comparable to the current arising from photogenerated carriers within the depletion region. In conventional detector designs, this diusion component is usually much smaller than the drift current and contributes a slow but small tail to the detectors impulse response. For high-speed detectors, diusion current can be eliminated by using a double-heterostructure design that limits absorption to high-eld intrinsic regions. But using a double-heterostructure design can lead to carrier piling at the junctions which again can slow the detector. However, this problem can be overcome by superlattice or compositional grading at the heterointerfaces. According to Kato et. al [26], if carrier transit time and the RC time constant are independent of each other and have Gaussian responses, the bandwidth (f3dB ) can be approximately given by (neglecting diusion and carrier piling) 1
2 f3dB

1 1 + 2 2 ft fRC

(2.3)

where ft is the transit time limited bandwidth and fRC is the RC-limit. For broadband operation, both the factors need to be optimized carefully. To analyze the performance of the photodetector analytically, ft can be approximated by [26] 3.5v 2d

ft where v is dened as

(2.4)

1 1 1 1 = ( 4 + 4) 4 v 2 ve vh

(2.5)

Here, ve and vh are electron and hole saturation velocities. For InGaAs, typical

10

reported values are ve = 6.5 106 cm/s and vh = 4.8 106 cm/s [26].

Rs

I(t)

Cd

Cp

RL

Figure 2.1. Simple equivalent circuit of a PIN photodetector.

A simple equivalent circuit of a PIN photodiode is given in Fig. 2.1 [6]. If the parasitic capacitance (Cp ) and series resistance (Rs ) are negligible, then the RC-limited bandwidth can be given by 1 2RL Cd

fRC =

(2.6)

where RL is the load resistance and Cd is the photodiode junction capacitance. Typically in normally-incident PIN diodes, thicker intrinsic region leads to higher transit time and smaller Cd . Hence we need to tailor the intrinsic layer thickness to optimize bandwidth. For discrete photodetectors, RL is usually assumed to be 50 because most of the RF instruments used for device characterization are designed to have an input impedance of 50 . In photoreceivers, the input impedance of the amplier following the photodetector is often designed to be lower than 50 to improve the circuit bandwidth. Another important characteristic of a photodetector is its noise performance.

11

Shot noise and Johnson noise (thermal noise) are the two dominant sources of noise in high-speed detectors. Since most photodiodes are operated under reverse bias conditions, the dark current is usually quite small. This dark current, which manifests itself as shot noise, contributes to the total system noise and gives random uctuations about the average particle ow of the photocurrent. Here, the uctuations are due to the randomness in thermal generation of carriers. Johnson noise is due to the various resistances in diodes equivalent circuit. Diode shunt resistance and series resistance contribute to the Johnson noise. If the diode is followed by an amplier in a receiver circuit, then the input resistance of the amplier and the ampliers noise gure also contribute to the Johnson noise of the overall photoreceiver. Apart from these noise sources, there is also a contribution from the background radiation in the ambient where the detector is placed. Usually, the contribution of the amplier dominates noise performance in a photoreceiver at telecommunication wavelengths.

2.1 Conventional PIN photodetectors A simple junction photodiode relies on generation of EHPs in the depletion region between p and n regions. To enhance the generation of EHPs and to reduce junction capacitance, an undoped (intrinsic) layer is introduced between p and n regions (a PIN diode). Such an intrinsic region is completely depleted at relatively low reverse bias and hence acts as an extended depletion region. This leads to a direct increase in absorption volume and a reduction in depletion capacitance. So a PIN structure oers both better quantum eciency as well as potentially improved bandwidth compared to PN junction diodes. The intrinsic layer thickness in a PIN diode is a key design parameter that

12

determines the responsivity and bandwidth of the detector. For high responsivity, the intrinsic layer thickness should be as large as possible, but increased thickness leads to an increased carrier transit-time and hence can lower the bandwidth. Thus there is a tradeo between bandwidth and responsivity in PIN diodes. Hence, for assessing performance of a photodetector design, bandwidth-eciency product (BWE) is a convenient metric. Since there is no inherent optical gain in PIN diodes, the maximum quantum eciency is 100% and the maximum BWE that can be obtained is the bandwidth of the diode.

50 40 30 20 10 0

Bandwidth (GHz)

0.2

0.4

0.6

0.8

Absorption layer thickness (m)

Figure 2.2. Bandwidth of a conventional PIN diode (junction area 248 m2 corresponding to 10 m optical window diameter) as a function of its absorption layer thickness.

13

Eqns. 2.2 and 2.3 can be used in designing a PIN layer structure. Assuming a load resistance of 50 and considering only junction capacitance, the bandwidth of a PIN structure can be determined as a function of its absorption layer thickness (Fig. 2.2). Junction capacitance is calculated for a device with 10 m optical window diameter corresponding to a junction layout area of 248 m2 . To achieve bandwidths of 40 GHz with a 10 m optical window diameter device, we need an absorption layer thickness of about 5000 , which corresponds to a maximum A eciency of 29%. The heterostructures used to fabricate PIN photodiodes in this work were grown by metalorganic chemical vapor deposition (MOCVD). The p-type layers were doped with carbon, while n-type layers were doped with silicon. The layer structure used along with its simulated band diagram are given in Fig. 2.3.

Material Structure
1

Anode

Absorption layer

Ec(eV) Ev(eV) Ef(eV)

500 p+ InGaAs (anode) A 5000 i InGaAs (absorption layer) A 2000 n+ InP (cathode) A 200 i InGaAs (etch stop) A SI InP (substrate)

0.5

E-Ef (eV)

-0.5 Cathode -1

-1.5 0 1000 2000 3000 4000 5000 6000 7000 8000

Depth (A)

Figure 2.3. Material structure and band diagram of conventional PIN.

14

Normally, the diode operates under a reverse bias sucient to deplete the intrinsic region completely. The electric eld due to this bias sweeps the photogenerated carriers across the depletion region. Even for moderate reverse bias, the carriers drift across the i-layer at close to their saturation velocities. This governs the transit time of the device which in turn aects the bandwidth. Technically there is also diusion of carriers photogenerated outside the i-layer (i. e. in the anode layer) although the contribution of this eect to the responsivity and bandwidth is small.

2.1.1 Fabrication and process ow Fabrication of the PIN photodetectors evaluated in this thesis involves seven mask layers. Anode contacts were dened by depositing 200/2000 of Ti/Au A through electron beam deposition on the p+ -InGaAs cap layer. Fiducial marks were also laid out along with the anode contacts to facilitate alignment of subsequent layers. The p-InGaAs anode and i-InGaAs absorption layer were then etched using a mixture of citric acid and hydrogen peroxide (20:1 citric acid/H2 O2 ) to expose the n-InP layer underneath. This was followed by mesa isolation of the n-InP cathode and the InGaAs etch stop. InP was etched using a mixture of phosphoric and hydrochloric acid (3:1 H3 P O4 /HCl). Once the devices were isolated, cathode contacts were dened by thermal deposition of 900/150/1200 of A AuGe/Ni/Au. These contacts were then annealed for 30 sec in a rapid thermal processor at 290 C in a nitrogen ambient. Benzocyclobutene (BCB) was then spun on the sample to serve as passivating layer and as a low-k dielectric for the overlay pads. Vias were dened in the BCB by dry etching in RIE using 3.3/30 sccm of SF6 /O2 with a DC bias of 30 V. The bias was optimized to realize sloped

15

side walls that lead to good step coverage for evaporated metal lms. Metal pads were then dened to draw out contacts through the BCB vias to facilitate RF probing. Finally, the BCB was etched o in the annular opening in the anode contact to create an optical window through which photoexcitation is provided as shown in Fig. 2.4.

Figure 2.4. Schematic cross-section of a PIN photodiode.

2.1.2 Experimental setup The DC measurements were made using an Agilent 4155C semiconductor parameter analyzer. A ber probe was used to position an optical ber on top of the device. The alignment was active, i. e., ber alignment was done by maximizing electrical output. The RF measurement setup used to measure the on-wafer frequency response consists of a distributed feedback (DFB) laser source which 16

Laser & Controller

50 GHz Synthesizer

Data Generator

50 GHz MZ Spectrum Analyzer

Optical Attenuator

DUT

Optical Power Meter

Figure 2.5. Experimental setup used to measure the bandwidth and responsivity of photodetectors.

emits light at 1.55 m. This light is modulated by a 50 GHz synthesizer through a Mach-Zehnder modulator. Here, the incoming optical signal is split equally into two branches and by application of a suitable bias, the two branches are separated in phase due to the electro-optic eect in lithium niobate. The signals are then recombined, producing a modulated output which is then fed to a optical attenuator. The light from the attenuator is then sent through a splitter, so as to monitor its optical power, while the other arm goes to the DUT (Device Under Test). The electrical output generated in the DUT in response to the modulated optical input is detected by a 50 GHz spectrum anlayzer. From the AC voltage impressed across the spectrum analyzers input impedance by the photocurrent, we can calculate the variation in responsivity with frequency. Eects of imperfections in the electrical and optical components are removed using a calibration procedure based on a standard reference detector. The measurement setup is almost completely computer controlled by a GPIB driver written in C for this purpose. A schematic diagram of the complete responsivity and bandwidth measurement setup is shown

17

in Fig. 2.5.

2.1.3 Experimental results The fabricated diodes were observed to have dark currents in the nA range for devices of junction area less than 588 m2 . The dark currents were also found to scale linearly with junction areas as shown in Fig. 2.6. The area dependence of the dark currents measured at a reverse bias of 3 V gave a typical dark current density of 1.2 105 A/m2 .

24 m

12E-9

at 3V

Dark Current (A)

Dark Current (A)

1x10-8 10 m

10E-9

14 m 6 m

8E-9 6E-9 4E-9 2E-9

1x10

-9

1x10-10

0E+0

-5

-4

-3

-2

-1

Bias Voltage (V)

(a)

200 400 600 800 1000 1200 Area (m 2)

(b)

Figure 2.6. Area dependence of dark current.

The bandwidth experimentally observed using the setup described was typically around 20 GHz as shown in Fig. 2.7. Responsivity was normalized to the

18

1x10-7

14E-9

low frequency value to show the 3-dB value clearly. The less-than-optimum performance of these diodes is explained by poor contact resistance which led to high series resistance in these devices.

Normalized Responsivity (dB)

5 0 -5 -10 -15 -20 -25 0.01

0.1

10

100

Frequency (GHz)

Figure 2.7. Normalized responsivity curve used to calculate bandwidth.

2.2 Drift-enhanced PIN photodetectors The drift-enhanced PIN structure (also called a dual-depletion PIN structure) preserves the responsivity of conventional PIN while oering the potential for improved bandwidth [12]. The drift-enhanced design has two depletion layers an absorption layer, and a transparent wide bandgap drift layer (Fig. 2.8). The main advantage of this structure is that it reduces junction capacitance due to an increased depletion layer thickness while only modestly impacting the transit time. 19

p anode i absorption layer

I drift layer n cathode

Figure 2.8. Schematic of drift-enhanced PIN structure.

1.8 1.6

Drift Velocity (x107 cm/s)

1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100

Electric Field (kV/cm)

Figure 2.9. InGaAs electron (solid) and hole (dashed) drift velocities as a function of electric eld [53].

Due to lower drift velocity, the transit time of holes across the InGaAs absorption layer is longer than that of electrons for top-illuminated conventional PIN diodes (Fig. 2.9). The inclusion of a transparent i-InP drift layer between the i-InGaAs absorption layer and cathode only increases the transit time of electrons. As a result, the drift layer has negligible eect on the overall transit time limited

20

bandwidth of the photodiode, provided that the thickness of the drift layer is such that the electron transit time is preserved at a value less than or comparable to the hole transit time. Since the responsivity of such a device is the same as a conventional PIN diode due to an identical absorption volume, the dual-depletion oers an improved BWE compared to a conventional PIN design. Using the same saturation velocities used for InGaAs in conventional PIN photodiodes and assuming a electron drift velocity of 1.5 107 cm/s for InP [32], the electron and hole transit times would be comparable for a drift layer thickness of around 2500 when the absorption layer thickness is 5000 . A A Two drift-enhanced designs with drift layer thickness of 2500 were evalA uated. The control design (AA5000) has a conventional (absorbing) anode with a 5000 thick absorption layer, while the other design (TA5000) featured a A transparent p-InAlAs layer in addition to the top p-InGaAs anode. Both the heterostructures were grown by MBE. The structure with the InAlAs contact layer is expected to have a better responsivity because the transparent anode layer allows photogeneration to occur only in the high-eld absorption layer. If the p and i layers are both narrow bandgap material, a portion of the photogenerated carriers in the p-layer recombines before reaching the depletion region without contributing to the total current. Hence making the p-layer transparent enables all of the incoming light to participate in EHP generation and increases responsivity. To study the eect of absorption layer thickness, another heterostructure (AA7000) with 7000 absorption layer thickness, otherwise identical to the A control design (AA5000), was used. A schematic diagram of all three heterostructures are given in Fig. 2.10, and a calculated band diagram for structure TA5000 is shown in Fig. 2.11.

21

 300 p+ InGaAs (anode) A 5000 (AA5000) A i InGaAs (absorption layer) 2500 i InP (drift layer) A 100 n+ InGaAs (etch stop) A 3000 n+ InP (cathode) A 200 i InGaAs (etch stop) A SI InP (substrate) (a)

300 p+ InGaAs (anode) A 7000 (AA7000) A i InGaAs (absorption layer) 2500 i InP (drift layer) A 100 n+ InGaAs (etch stop) A 3000 n+ InP (cathode) A 200 i InGaAs (etch stop) A SI InP (substrate) (b)

300 p+ InGaAs (anode) A A 100 p+ InAlAs (transparent anode) 5000 (TA5000) A i InGaAs (absorption layer) 2500 i InP (drift layer) A 100 n+ InGaAs (etch stop) A 3000 n+ InP (cathode) A 200 i InGaAs (etch stop) A SI InP (substrate) (c)

Figure 2.10. Material structure of drift-enhanced PINs used in this work (a) AA5000, (b) AA7000 with absorption layer thickness of 5000 and 7000 respectively (c) TA5000 with a absorption layer A A thickness of 5000 and InAlAs transparent anode layer. A

1.5 InAlAs 1 InGaAs 0.5

E - E (eV)

0 -0.5 -1 -1.5 -2 0 0.2 0.4 0.6 0.8 1 InGaAs InP InGaAs InP

E E

f c

1.2

Depth (m)
Figure 2.11. Band diagram of transparent anode TA5000.

22

2.2.1 Fabrication and process Flow The fabrication sequence for drift-enhanced PINs is almost identical to that of conventional PIN diodes. The only dierence was to modify the mesa etch process to include H3 PO4 /HCl etchant to etch the drift layer, making use of the InGaAs etch stop to facilitate n-contact placement. Otherwise, photolithography and other processes were the same as in conventional PINs.

2.2.2 Experimental results Typical dark currents were in the nA range for devices with junction areas up to 1136 m2 for all three heterostructures. The dark current behavior was almost linear with area in all devices. Dark current densities assuming linear dependence on junction areas were found to be 1.35 106 A/m2 , 4.84 107 A/m2 , and 1.16 106 A/m2 for AA5000, TA5000, and AA7000 respectively, as shown in Fig. 2.12. The dierence in the current densities are mainly due to processing non-uniformities. Typical responsivities at 1.55 m were 0.27 A/W, 0.3 A/W, and 0.38 A/W for AA5000, TA5000, and AA7000 respectively. The responsivity of the transparent anode structure shows an improvement over the absorbing anode structure as expected. Due to reection at the interface between air and InGaAs, part of the incident optical power is reected back (assuming normal incidence). If we use SiNx for AR coating, we can reduce losses due to reection and improve the responsivity by almost 30%. A typical illuminated measured I-V characteristic of a fabricated photodiode on heterostructure TA5000 is given in Fig. 2.13. For the photoresponse, the input optical power is stepped in 3 dB increments and the corresponding currents

23

5 4.5

Dark Current (nA)

TA5000 AA5000 AA7000

4 3.5 3 2.5 2 1.5 1 200 400 600 800

2

1000

1200

Area (m )
Figure 2.12. Area dependence of dark current in fabricated devices.

10-3 10-4 Popt= 420 W

Current (A)

10-5 10-6 10-7 10-8 10-9 10

-10

Dark Current Popt stepped in 3dB increments 0 2 4 6 8 10 12 14 16

Bias Voltage (V)

Figure 2.13. DC photoresponse of transparent anode PIN (TA5000).

24

are recorded. Equally spaced logarithmic I-V curves in the gure indicate that the electrical output is quite linear with the optical input for over at least two orders of magnitude from 3.3 W to 420 W. Experimentally determined device capacitances using a CV meter were found to saturate with bias at about 2 V, as shown in Fig. 2.14.

400 350 25 m 15 m 10 m 6 m

Capacitance (fF)

300 250 200 150 100 50 0 0 2 4 6

10

Reverse Bias (V)

Figure 2.14. Bias dependence of device capacitance for TA5000.

The RF experimental setup described earlier (Fig. 2.5) was used to measure the frequency response of these devices. Bandwidths greater than 50 GHz were observed for 5000 devices with optical window diameter 10m (corresponds A to junction area 248 m2 ). Extrapolation using least-squares ts of a single-pole transfer function to the measured data suggests a 3 dB bandwidth of around

25

60 GHz for 6 m diameter devices on TA5000 and AA5000, while the 6 m diameter AA7000 devices showed a bandwidth of around 52 GHz. These values correspond to BWEs of 14.2 GHz for TA5000 and 15.6 GHz for AA7000. For devices exhibiting bandwidth over 50 GHz, the bandwidths reported are estimates obtained by extrapolation (Fig. 2.15).

Relative Responsivity (dB)

0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 0.01 0.1 1 10 100

Frequency (GHz)
Figure 2.15. Normalized responsivity curve of TA5000.

Bandwidth decreases with increasing junction area due to the increasing RClimit as shown in Fig. 2.16. The linear region of inverse area dependence clearly shows that bandwidth of large area devices are limited by junction capacitance. As the junction area decreases, bandwidth becomes dominated by the transit time limit and begins to saturate. AA7000s bandwidth dependence on area has

26

a shorter linear region due to increased transit time contribution of the thicker absorption layer.

70

Bandwidth (GHz)

60 50 40 30 20 10 0

AA7000 TA5000

4
-1

6
9 -2

10

Area (x 10 m )
Figure 2.16. Inverse area dependence of bandwidth.

The bandwidth of drift-enhanced diodes has an interesting bias dependence (Fig. 2.17). Small area devices were observed to exhibit pronounced bias dependent peaking around 2 V. In general, at low bias voltages, the intrinsic region is not fully depleted, and the bandwidth is limited by diode capacitance. In small area devices, at higher bias voltages, carrier transit time limits the bandwidth. Carrier transit-time-limited bandwidth decreases as bias is increased partly due to a decrease in drift velocity with electric eld (Fig. 2.9) and partly because of an increased depletion region width in the contact layers [5], which is evident in the

27

6 m and 10 m optical diameter devices. Since the contact layers were heavily doped (> 1019 cm3 ), the contribution due to increased depletion layer thickness is much smaller compared to decrease in transit time through the absorption layer due to the decrease in drift velocity.

60 50 40 30 20 10 0 0 2 4 6 8 10 25 m 15 m 10 m 6 m

Bandwidth (GHz)

Bias Voltage (V)

Figure 2.17. Bias dependence of bandwidth in AA7000.

2.3 Drift-enhanced dual-absorption PIN photodiodes The responsivity of a conventional vertically illuminated PIN diode can be improved without aecting the transit time limit by adding another absorption layer as shown in the PINIP structure in Fig. 2.18 [19]. The increase in responsivity in this case is accompanied by the undesired eect of doubling device capacitance, 28

leading to a more severe RC-limited bandwidth. Since the dual-depletion design eases the RC-limit while preserving responsivity, a judicious combination of the two designs should lead to a better BWE than is possible in conventional vertically illuminated diodes.

p+ InGaAs (anode) i InGaAs (absorption layer) n+ InP (cathode) i InGaAs (absorption layer) p+ InGaAs (anode) SI InP (substrate)

Figure 2.18. Dual absorption PINIP photodiode structure.

2.3.1 Material structure To evaluate the performance of the drift-enhanced dual-absorption design, a layer structure similar to the dual-depletion photodiodes was used. The absorption layer thickness was chosen to be 7000 because we expect these devices to A be strongly RC-limited and thus a larger absorption length and transit time can be used without appreciably sacricing device bandwidth. To study the eectiveness of the drift enhancement layer for increasing bandwidth, a control structure without the i-InP drift layers but otherwise identical was used. The cross-sectional schematic of the heterostructures used in this work is given in Fig. 2.19. Both

29

 p+ InGaAs (anode) 300 A A p+ InAlAs (anode) 100 A i InGaAs (absorption layer) 7000 A n+ InP (cathode) 500 A n+ InGaAs (cathode etch stop) 100 A n+ InP (cathode) 2500 A i InGaAs (absorption layer) 7000 p+ InAlAs (anode) 100 A A p+ InGaAs (anode) 300 p+ InP (anode) 10000 A A i InGaAs (etch stop) 100 SI InP (substrate)

A p+ InGaAs (anode) 300 A p+ InAlAs (anode) 100 i InGaAs (absorption layer) 7000 A A i InP (drift layer) 2500 A n+ InP (cathode) 500 A n+ InGaAs (cathode etch stop) 100 A n+ InP (cathode) 2500 A i InP (drift layer) 2500 A i InGaAs (absorption layer) 7000 p+ InAlAs (anode) 100 A A p+ InGaAs (anode) 300 p+ InP (anode) 10000 A A i InGaAs (etch stop) 100 SI InP (substrate)

(a)

(b)

Figure 2.19. Material structures: (a) Control design (b) Drift enhanced design.

the heterostructures were grown by MBE.

2.3.2 Fabrication and process Flow Fabrication of dual-absorption diodes involves eight mask layers. Schematic cross-section of the photodiode after fabrication is shown in Fig. 2.20. Anode contacts were dened rst by electron beam deposition of 200/2000 of A Ti/Au. After anode contact denition, p-InGaAs, p-InAlAs, i-InGaAs and n-InP were wet etched using citric acid- and phosphoric acid-based etchants as in dualdepletion diodes. Cathode contacts were then dened by thermal deposition of 900/150/1200 of AuGe/Ni/Au, followed by alloying at 290 C in RTP for 30 A

30

Optical window Light Ti/Au AuGe/Ni/Au

p i I n I i p

Ti/Au SiNx

Semiinsulating substrate

Figure 2.20. Schematic cross-section of a dual-absorption photodiode.

sec in nitrogen ambient. TLM pads incorporated along with the cathode contacts were used to test the contact resistivity, and contact resistances of less than 0.1 mm were obtained. This was followed by removing the n-InGaAs etch stop, nInP, i-InGaAs, p-InAlAs, and p-InGaAs layers by wet etch to expose the bottom anode contact. After this mesa etch, all subsequent steps were carried out using an optimized two-layer photoresist process, since the primary device mesa is too tall to be fully covered by a single layer of AZ5214 photoresist. 200/2000 of A Ti/Au was then deposited to dene bottom anode contacts by electron-beam deposition. Mesa isolation of the anode contact layer is then carried out by etching the p-InP and underlying InGaAs etch stop using a combination of wet and dry etches. Dry etching was needed for isolation because the bottom InGaAs etch stop and the InP substrate had unintentional layer intermixing in the samples used that could not be etched away using selective wet chemical etchants. Dry

31

Ti/Au SiNx

etching was done in RIE using CH4 /H2 /Ar with a ow rate of 4/20/10 sccm, 75 mT chamber pressure, and 300 W of RF power. The sidewall damage due to the dry etch process was reduced using a sputtered SiO2 layer to protect the active device areas. Dry etching was followed by a short wet etch to minimize the damage further. After stripping the protective SiO2 layer, 2100 of SiNx A was deposited by PECVD to act as a passivation layer, interlayer dielectric, and as anti reection coating. SiH4 /N H3 /N2 with a ow rate of 60/7.5/1000 sccm, and a chamber pressure of 1300 mT were used at a RF power of 25 W to deposit SiNx . Since SiNx forms a conformal coating, and both citric acid-based InGaAs etch and the H3 P O4 -based InP etch are crystallographic, i. e., the wet etching in certain crystallographic planes occur faster in preference to others, the mesa patterns had to be aligned perpendicular to the [011] crystal direction (primary at) in such a way that sidewalls over which metal lines run have an outward slope. The crystallographic nature of etchants can be clearly seen from Fig. 2.21. Finally RF metal pads were dened by depositing 200/4000 of Ti/Au by electron beam A deposition.

2.3.3 Experimental results DC measurements at 1.55 m of top illuminated drift-enhanced photodiodes exhibit a measured responsivity of 0.59 A/W without AR coating, improving to 0.82 A/W with AR coating. Control devices without the drift layers exhibit identical responsivity, as expected. The photocurrent scales linearly with incident optical power as shown in Fig. 2.22. Capacitance measurements (at 1 MHz) indicate that both control and drift-enhanced structures are fully depleted at 1.2 V and the device capacitance is linear with device area with capacitance per unit

32

Primary flat

[011] [011] Secondary flat

(a)

(b)

(c)

Figure 2.21. (a) Schematic representation of crystallographic mesa etch prole with respect to wafer ats (b) SEM image of mesa prole along [011] (b) along [011].

area of 0.151 fF/m2 and 0.147 fF/m2 for control and drift-enhanced designs respectively, as shown in Fig. 2.23. Fully depleted devices with 6 m diameter optical windows (with total junction area of 374 m2 ) showed capacitances of 71 fF and 91 fF for devices with and without drift layers, respectively (a reduction of 22% due to drift layer). The measured electrical 3-dB bandwidth of a typical 6 m optical diameter device is 30 GHz for the drift-enhanced design, corresponding to a BWE of 19.7

33

10-3 10-4
Popt=336 W

Current (A)

10-5 10-6 10-7 10-8

Popt stepped in 3dB increments

Dark current

10

-9

-1

Bias voltage (V)

Figure 2.22. DC photoresponse of a typical drift-enhanced device showing responsivity of 0.82 A/W.

500

Capacitance (fF)

400 300 200 100 0 0

drift-enhanced control

500

1000 1500 2000 2500 3000

Area (m2)
Figure 2.23. Device capacitance as a function of area.

GHz at 1.55 m (Fig. 2.24), while the control design exhibited bandwidths of 24 GHz for devices of the same area. The bandwidth decreases with increase in 34

junction area due to increased capacitance, as shown in Fig. 2.25. The inverse area dependence of the bandwidths (Fig. 2.26) shows linear dependence when capacitance limited and tends to saturate when the RC-limit becomes comparable to the transit-time limit.

Normalized Responsivity (dB)

1 0 -1 -2 -3 -4 -5 -6 0.01 0.1 1 10 100 Control Drift-enhanced

Frequency (GHz)
Figure 2.24. Frequency response of 6 m optical diameter devices showing the advantage of drift-layers in improving 3-dB bandwidth.

2.4 Device modeling On-wafer s-parameter measurements of the photodiodes biased at 4 V were made using a 40 GHz network analyzer to extract an equivalent circuit model of the photodetector. Fig. 2.27 shows the equivalent circuit used. The diodes were modeled in Agilent-EEsofs ADS software using these measured s-parameters.

35

30

Bandwidth (GHz)

25 20 15 10 5 0 0 500

drift-enhanced control

1000 1500 2000 2500 3000

Area (m2)
Figure 2.25. Measured bandwidth of drift-enhanced and control structures as a function of area; drift-enhanced structure exhibits improved bandwidths over control structure, up to 30% for 6 m optical diameter devices.

30

Bandwidth (GHz)

25 20 15 10 5

0.5

Area (x 10 m )
Figure 2.26. Measured bandwidth of drift-enhanced devices as a function of inverse area.

-1

1.5
9

2
-2

2.5

36

Rs

Ls

I(t)

Rd

Cd

Cp

Cx

Figure 2.27. Lumped element equivalent circuit used to describe photodiodes; Rd is the diode shunt resistance, Cj is the junction capacitance due to depletion, Rs is the series resistance of the diode (sum of contact resistance and bulk resistance), Ls is the total series inductance (mainly due to pads), Cp is the pad capacitance, and Cx is the launch capacitance.

The equivalent circuit assumes that the junction capacitance is completely due to depletion, and the model is valid under dark conditions, so the current source which is usually included in photodiode models to quantify carrier generation due to input optical signal is absent. The measurement setup was controlled by Agilent-EEsofs IC-CAP software and the s-parameters were ported to ADS. Circuit parameters were then extracted in ADS by non-linear least-squares optimization to match the measured sparameters of the device. Fig. 2.28 shows the measured and modeled s-parameters of the photodiode. Excellent agreement between the model and the measured sparameters for 1 to 35 GHz was obtained. Junction capacitances extracted from the measured S-parameters are quite linear with area and are close to the theoretical values (assuming a parallel plate structure) for the TA5000 heterostructure as shown in Fig. 2.29. Series resistances extracted from the model for the dual-depletion devices were around 14 for 6 m devices and around 10 for larger devices (10 m, 15 m and 25 m).

37

1 0.98

11

-10 -20

Magnitude

0.96 0.94 0.92 0.9

Phase

-30 -40 -50 -60 0 5 10 15 20 25 30 -70 35

Frequency (GHz)
Figure 2.28. Measured (dashed) and modeled (solid) s-parameters of TA5000 (10 m optical diameter device).

160

Junction Capacitance (fF)

140 120 100 80 60 40 20 0 0

Theoretical Modeled

200

400

600

800
2

1000

1200

Area (m )
Figure 2.29. Area dependence of modeled and theoretical junction capacitance in TA5000.

38

For the dual-absorption design, the extracted junction capacitances were 52 fF and 75 fF for drift-enhanced and control designs, respectively, for 6 m optical diameter devices. The series resistance extracted from the model was 28 for 6 m drift-enhanced device and is dominated by the spreading resistance of the bottom p-contact. The pad capacitance extracted for our design was 22 fF. These values suggest that the device layout and heterostructure can be further optimized to improve bandwidth.

TABLE 2.1 SUMMARY OF EQUIVALENT CIRCUIT PARAMETERS FOR 6 m OPTICAL WINDOW DIAMETER PHOTODIODES.

Extracted Circuit Parameters

Dual-depletion (TA5000)

Dual-absorption Control 13 74.5 26.1 65.6 22.1 1.4 Drift-enhanced 1.8 51.8 27.8 49.5 22.4 3

Depletion resistance, Rd (k) Junction capacitance, Cj (fF) Series resistance, Rs , () Series inductance, Ls , (pH) Pad capacitance, Cp , (fF) Launch capacitance, Cx , (fF)

20.8 14.6 13.7 20 13.7 2.3

39

2.5 Device simulation The frequency response of the photodiodes was analyzed theoretically using both an analytical and numerical model to assess their fundamental BWE limitations. The numerical model used a one-dimensional transit-time calculation coupled with the extracted circuit parameters. A carrier drift model is used to compute the transit time in the device assuming a parallel plate structure. The impulse response at the terminals of the device is then computed by time-domain convolution of the transit-time limited impulse response and the impulse response of the small-signal equivalent circuit of the device in the absence of illumination [57]. The quasi-static carrier drift model assumes the device is fully depleted, which is usually true when incident light intensity is small and applied bias is large. The model also assumes space charge eects and carrier piling at the heterointerfaces are negligible to further simplify the problem.

dx e i h
+

+ + + + + + + + + + +

Figure 2.30. Schematic diagram showing the initial carrier distribution as result of impulse optical excitation.

40

The transit-time limited behavior of the carriers was calculated assuming an exponential initial carrier concentration as shown in Fig. 2.30 (corresponding to impulse of incident light shone at t=0 from anode side of the device) and by dividing the depletion region into very small cells and considering charge transport between two short-circuited parallel plate electrodes. The intial exponential carrier distribution accounts for absorption through the intrinsic layer of the incident light. The induced current as a function of position x and time t is given by Q(x, t)v(x) W

I(x, t) =

(2.7)

where Q(x, t) is the number of carriers at position x and v is their velocity. The contribution of all moving charges within a given time step gives the total transittime limited current in the device. Since the device terminals are assumed to be short-circuited, device capacitance need not be considered for this calculation. The resulting calculated current is the transit-time limited current of the device, and can be represented by a time-dependent current source in the equivalent circuit model. For terminal load impedances other than a short circuit, the impulse response at the terminals of the diode is simply the convolution of the impulse response of the equivalent circuit and the transit-time limited impulse response. The drift velocities of electrons and holes were computed using the empirical analytic equations used by Williams [53]. The velocities are given by E(n + vnhf |E|) 1 + E 2 p vphf E InGaAs hole velocity, vp (E) = vphf + p E E(n + vnhf E 2 ) InP electron velocity, vn (E) = 1 + E 3

InGaAs electron velocity, vn (E) =

(2.8) (2.9) (2.10)

41

TABLE 2.2 MATERIAL CHARACTERISTICS USED IN SIMULATION.

Properties Electron mobility, n (cm2 /V s) Hole mobility, p (cm2 /V s) Electron saturated velocity, vnhf , (cm/s) Hole saturated velocity, vphf , (cm/s) Electron velocity tting parameter, Permittivity

InGaAs 8000 300 1x107 6x106 0.8x107 13.9

o

InP 3500

1x107

0.8x1012 12.6
o

The saturation velocities used in the calculation were obtained by tting the measured frequency response of the simple single absorption drift-enhanced structure (TA5000). This can be justied from the fact that the velocities reported in the literature vary over a wide range as shown in the case of electrons in Fig. 2.31. The saturation velocity values used in the simulation are consistent with those reported in the literature [8],[49],[54]. For the dual-absorption structures, using the tting parameters extracted from TA5000, this analysis leads to a bandwidth of 23.3 GHz for control design and 29 GHz for the drift-enhanced design (for the 6 m optical diameter devices), which matches the measured bandwidths closely. If the parasitics in the equivalent circuit are neglected, we can estimate the fundamental performance limits of an ideal device. Considering only junction capacitance and a 50 load resistance, this model estimates a bandwidth of 37.5 GHz for the drift-enhanced structure and 31.5 GHz for the control device, 42

Figure 2.31. Electron drift velocities of InGaAs, InAs and GaAs as a function of electric eld. Light shaded area comprises data for In0.53 Ga0.47 As on InP substrates from dierent authors, dark shaded area refers to GaAs bulk values [7].

Transit-time Impulse Response (arb. units)

1.2 1 0.8 0.6 0.4 0.2 0

10

15

20

25

30

Time (ps)

Figure 2.32. Simulated transit-time limited impulse response in TA5000.

43

corresponding to BWEs of 23 GHz and 19.3 GHz respectively. An analytical model of the drift-enhanced photodiode was also developed to assess its fundamental BWE limitations and to verify the results obtained from numerical analysis. Neglecting diusion and recombination in the absorption regions and carrier pile-up at the heterointerfaces, the transit-time limited current density frequency response for a drift-enhanced structure can be expressed as:

q0 W 1 eje 1 eW J() = + + W + je je W eW1 1 eW1 (ejh 1) q0 W1 + W jW/vh W1 jh

(2.11)

where W1 is the thickness of the InGaAs absorption layer and W is the sum of InGaAs absorption and InP drift layer thicknesses, e and h are the electron and hole transit times, 0 is the incident photon ux density, and is the absorption coecient of InGaAs. This expression was derived following the treatment in [4], extended for a drift-enhanced structure. The transit-time limit for a dualabsorption structure is the same as in a simple drift-enhanced design due to the device symmetry. Assuming only the device capacitance and load resistance (50 ) contribute to the RC limit and charge carriers travel at their saturation velocities, the diodes 3-dB bandwidth was computed as a function of W1 and W . The saturation velocities used in the calculation were the same as those used in numerical analysis. Neglecting diusion and assuming unity internal quantum eciency, the responsivity for a single-pass design is given by q (1 R)(1 e2W1 ) h 44

(2.12)

27

1.8 1.6

Maximum BWE (GHz)

26 25 24 23 22 21 20 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

drift-enhanced PINIP PINIP (no drift)

1.2 1 0.8

W1 (m)
Figure 2.33. Maximum BWE and corresponding total depletion width as a function of absorption layer thickness for drift-enhanced dual-absorption photodiode structure, as extracted from simulation. A peak BWE of 26 GHz is obtained. For W1 1.35 m, a dual-absorption structure without drift layer is optimal (W1 = W ).

where R is the surface reectance. This analysis leads to a maximum BWE product of 26 GHz for this design (single-pass) with a bandwidth of 36 GHz for W1 of 0.95 m and W of 1.15 m (for a 6 m optical diameter device) with AR coating (R=0). This BWE is nearly 5 GHz larger than what is achievable by conventional vertically illuminated PIN diodes of similar geometry. For a two-pass design, the analysis projects a maximum BWE of 35 GHz. For the drift-enhanced dual-absorption layer structure used in our fabricated diodes, the analysis estimates a 3 dB bandwidth of 40 GHz, corresponding to a maximum achievable BWE of 25 GHz. The less-than-expected measured bandwidth of the device is mainly due to the high series resistance (28 ) in these rst-generation devices. The pad layout capacitance in our structure estimated

45

W (m)

1.4

from the circuit model is 22 fF, which combined with the high series resistance results in a substantial reduction in RC-limited bandwidth. Improved pad layout and the use of a thicker anode contact layer is expected to ease this restriction.

TABLE 2.3 MEASURED AND MODELED RESULTS FOR 6 m OPTICAL DIAMETER DRIFT-ENHANCED DUAL-ABSORPTION DEVICE.

Measured Design Hf fT data f3dB

Numerical model fT f3dB

Analytical model fT f3dB

Control

29

55

24

46.7

23.3

58.3

24.9

Drift-enhanced

40

54

30

50

29

53.7

30.8

Note: All bandwidths are in GHz

A summary of measured and modeled values is given in Table 2.3. In the table, Hf is the bandwidth of the equivalent circuit, fT is the transit-time limited bandwidth, and f3dB refers to the 3 dB bandwidth of the photodiodes into a 50 load. The transit-time limited bandwidth was extracted from the measured frequency response assuming a single-pole roll o, and is denoted as measured fT in the table. Even though the numerical model is modestly pessimistic, the performance projected makes drift-enhanced dual-absorption devices very attractive for 40 Gbps receivers. 46

CHAPTER 3 HIGH ELECTRON MOBILITY TRANSISTORS

Photodetectors by themselves are generally insucient to produce directly usable signals for optical information processing systems. In most cases, the generated photocurrent is quite weak and needs electronic amplication before it can be used for further processing. Since PIN diodes have no internal gain, it is essential to have an amplication circuit along with the detector. The amplication can be provided by either a eld eect transistor- or bipolar transistor-based amplier, and the choice of transistor technology is a very important issue in receiver design. A key issue in integration is that the performance of the implemented devices must not be degraded due to the integration process. To realize OEICs with devices which individually oer state-of-the-art performance, separate optimization of each device is necessary. Since in PIN-HBT receivers the active layers are usually shared which makes individual device optimization dicult, the PINHEMT receiver is chosen for this work. In this chapter, we focus on developing a high-speed HEMT structure which can be integrated with our photodiodes to realize a photoreceiver. HEMTs, also known as modulation-doped-eld-eect transistors (MODFETs) rely on modulation doping to increase carrier mobility in the conduction channel. When a layer of undoped low-bandgap material and heavily doped high-bandgap material form a heterojunction, due to the dierence in electron anities of the 47

two layers, electrons are transferred from the high-bandgap material to the lowbandgap material to form a two-dimensional electron gas (2DEG). The advantage of modulation doping is that the mobile charge carriers are spatially separated from the ionized dopant atoms and hence Coulombic scattering is greatly reduced resulting in higher carrier mobility. Typically, an undoped spacer layer is added between the heavily doped wide-bandgap region and the undoped low-bandgap region to further improve electron mobility. By applying an external voltage across the heterointerface, one can modulate the 2DEG density, and thus its conductivity. The improved transport properties in a modulation-doped structure by itself does not necessarily lead to high speed performance of HEMTs because their speed also depends on the the ability to modulate high speed electrons [36]. The key gures of merit for a high-speed HEMT are its transconductance (gm ) and cut-o frequencies (ft and fmax ). Transconductance is a measure of ecient channel current modulation and is given by, Id Vgs

gm =

(3.1)
Vds =const.

The device ft is the frequency at which the short circuit current gain falls to unity. This can be related to the lumped element parameters by, gm 2(Cgs + Cgd )

ft =

(3.2)

where (Cgs + Cgd ) is the total gate capacitance associated with the Schottky gate contact. Hence to achieve high ft , we need to increase gm and decrease gate capacitance, the latter usually achieved by making the gate length small. The other cut-o frequency, fmax , is the frequency at which the Masons unilateral power gain falls to unity. Under saturation conditions when output conductance 48

is negligible, fmax can be approximated by [31], ft 8Rg Cgd

fmax =

(3.3)

Due to fmax s dependence on Rg (gate resistance), to achieve high ft and fmax at the same time, we need to achieve short gates with reduced Rg . As a result, a number of mushroom or T-gate processes have been developed to increase the gate cross-sectional area and thus reduce its resistance, while still maintaining a small gate footprint. This reduction in gate resistance signicantly increases the power gain cuto frequency (fmax ) and reduces the noise gure of sub-micron gate length HEMTs [36]. A schematic of a HEMT structure with T-gate is shown in Fig. 3.1.

Figure 3.1. Schematic cross-section of a typical InP-based HEMT.

49

The HEMT structure has the advantage of placing the channel in close proximity to the gate (typically less than 500 ). As the gate length is reduced, the A vertical dimensions need to be proportionally reduced in order to maintain a reasonably high aspect ratio (the ratio between gate length and eective gate-tochannel separation). This geometrical parameter is very important in controlling the eld eect action of HEMTs and should be maintained at least over ve to reduce short-channel eects [36]. Assuming the classic saturation velocity model (SVM),

gm =

d + d

vavg

(3.4)

where is the dielectric constant of the semiconductor layer beneath the gate, d is the gate-to-channel separation, and d is the displacement of the two-dimensional electron gas from the heterojunction interface [35]. As shown by this expression, minimizing the gate-to-channel separation increases transconductance. If the barrier layer is uniformly doped, the sheet carrier density and gate-tochannel separation are directly related to each other. The threshold voltage is related to the barrier layer thickness as given by [9], Ec qND (dbarrier dspacer )2 q 2

Vth = B

(3.5)

where B is the Schottky barrier height, Ec is the conduction band discontinuity between spacer and channel, ND is the doping concentration in the uniformly doped barrier layer, dspacer is the thickness of the undoped spacer layer, and dbarrier is the thickness of the barrier layer including dspacer . Thus a decrease in gate-tochannel separation would shift the threshold voltage to more positive values and thus reduces drain current. To overcome this problem, in most practical HEMT 50

structures, a silicon -doped layer is used instead of a uniformly doped InAlAs layer. Since having a -doped layer decouples sheet charge and gate-to-channel separation, this helps to suppress threshold voltage shifts due to non-uniform gate recess and hence provides a tighter control on the threshold voltage.

3.1 Material structure, fabrication, and results To facilitate integration with the photodetectors already demonstrated, we focus on InP material system. Two promising HEMT designs were evaluated - one structure had a lattice matched InGaAs channel and the other had a composite channel (pseudomorphic) made of three InGaAs layers with varying indium composition. The composite structure has several potential advantages for high speed performance since the electron mobility increases with indium content in InGaAs, and the conduction band discontinuity at the InGaAs/InAlAs heterojunction also increases as the energy bandgap approaches that of InAs. An increased conduction band discontinuity leads to higher channel charge density and greater connement. Though a lower bandgap channel improves the high-frequency performance, it also reduces the breakdown voltage of the device. Also, since the lattice constant becomes larger compared to InPs lattice constant, the pseudomorphically grown channel layers experience a strain which limits the total thickness of channel achievable and may also lead to increased defects. The heterostructures were grown by MBE and their schematics are given in Fig. 3.2. In the lattice matched structure, a pseudomorphic AlAs layer (which is lattice mismatched to InP) was used as a etch stop for gate recess. In both structures, Si was used as n-type dopant in the InGaAs cap layer and for the -doping plane in the InAlAs barrier layer.

51

 80 n+ InGaAs (contact) A 25 AlAs (etch stop) A 170 i InAlAs (barrier) A *-*-*-*-*-*-*-* doping*-*-*-*-*-*-*40 i InAlAs (barrier) A 200 i InGaAs (channel) A 2000 InAlAs (buer) A SI InP (substrate)

250 n+ InGaAs (contact) A 100 i InAlAs (barrier) A *-*-*-*-*-*-*-* doping*-*-*-*-*-*-*40 i InAlAs (barrier) A 30 i In0.53 Ga0.47 As (channel) A 70 i In0.63 Ga0.37 As (channel) A 80 i In0.58 Ga0.42 As (channel) A 3000 InAlAs (buer) A SI InP (substrate)

(a)

(b)

Figure 3.2. Schematic HEMT layer structure with (a) lattice matched channel (b) composite channel.

The HEMT fabrication process sequence comprises three mask layers. The active region is rst dened by wet chemical etching of the n-InGaAs cap, InAlAs barrier, InGaAs channel, and part of the InAlAs buer using 20:1 citric acid/H2 O2 solution. Etching into the buer region ensures that the active regions are electrically isolated from each other. Once the mesa was dened, a mushroom etch was done with 1:1 citric acid/H2 O2 to etch InGaAs selectively over InAlAs. This ensures that the channel does not come in contact with the gate metal at the mesa edges during gate metallization. Ohmic contacts were then dened by thermal deposition and alloying of AuGe/Ni/Au as for the photodiodes. TLM patterns laid along with ohmic contacts were used to test the contact resistance of the metallization. Gate patterns were then dened optically or through electron beam lithography. Optically dened gates in our lab are limited to 1 m, so electron beam lithography was used to achieve submicron gate lengths. To get T-gates with electron beam lithography, a tri-layer resist structure was used: a MMA (methyl methacrylate) layer sandwiched between two PMMA (poly

52

Figure 3.3. SEM image showing end view of T-gates fabricated.

methyl methacrylate) layers. The lower PMMA layer had a molecular weight of 950 k, the sandwiched MMA layer with 8.5 % methacrylic acid (MAA), and the top PMMA layer had a molecular weight of 50 k. The thickness of the layers used were 1600/4500/1500 , optimized to achieve a gate length of 0.3 m. The A PMMA layer at the bottom requires a higher electron dose to become soluble in developer solution than the layer over it due to its larger molecular weight. This gives rise to a preferential development, leading to a T-shaped cross-section. Fig. 3.3 shows a typical T-gate end view, showing the small gate footprint and large gate head for low resistance. The exposed patterns were developed in 1:3 MIBK (methyl isobutyl ketone)/IPA solution and were subject to descum in UV

53

ozone (UVO) cleaner to remove any resist residue that might have been left over after development. Optically dened gates were descummed in RIE using oxygen plasma. After gate denition, the InGaAs cap layer was etched o to achieve a Schottky gate contact (gate recess). Optimal etch depth is achieved by using an iterative gate recess etch. The gate recess etch is broken into a series of short etch steps, and the drain current as a function of drain bias is monitored between each step. Before the recess etch, the I-V is nearly linear, since conduction takes place mostly through the heavily doped cap layer. As the cap layer is progressively etched o, the I-V characteristic gradually saturates and ideally attens out when the cap layer is fully removed. The etch is completed when a target drain current density is achieved. Once the recess is complete, Cr/Au was thermally deposited on to the sample and lifted o to form the gate electrode. Since etching rates of InGaAs and InAlAs can be signicantly modied due to the electrochemical etching component of the citric acid when exposed to metal electrodes [58], only the recess region was exposed during gate denition. On-wafer DC and RF measurements of fabricated devices were performed using an Agilent 4155C semiconductor parameter analyzer and 8722D network analyzer in a microwave probe station. DC measurements were also done through RF probes to suppress oscillations due to the high gain and bandwidth of these devices. The pseudomorphic HEMTs exhibit higher transconductance and larger current density as expected. Figs. 3.4 and 3.5 show drain current dependence on gate voltage; the lattice matched device exhibits a maximum transconductance of 501 mS/mm and a threshold voltage of -0.37 V, while the pseudomorphic device exhibits a higher maximum transconductance of 648 mS/mm and a threshold

54

300

600 500 400 300 200 100 0 0.4

Transconductance (mS/mm)

Drain Current (mA/mm)

250 200 150 100 50 0 -0.6

-0.4

-0.2

0.2

Gate Voltage (V)

Figure 3.4. Ids vs Vgs charactersitics of lattice matched HEMT with 0.3 m gate length.

350

700 600 500 400 300 200 100 0 -0.4 -0.2 0 0.2

Transconductance (mS/mm)

Drain Current (mA/mm)

300 250 200 150 100 50 0 -0.6

Gate Voltage (V)

Figure 3.5. Ids vs Vgs charactersitics of pseudomorphic HEMT with 0.3 m gate length.

55

voltage of -0.11 V. Figs. 3.6 and 3.7 show the drain current dependence on the drain voltage of 0.3 m devices. Both the lattice matched and pseudomorphic devices exhibit high output conductance. The output conductance is exacerbated by kink eect, a sharp increase in the saturated drain current with respect to drain bias. This eect is believed to be because of trapping and detrapping of carriers in the InAlAs buer layer [37], and impact ionization in the InGaAs channel [13]. Surface states also play a role and passivation has been shown to drastically reduce the I-V kink in InP-based HEMTs [51]. Although it has been demonstrated to be mainly a DC eect [13], it is still associated with reduced gain and excess noise at high frequencies, and may be related to on-state breakdown and premature burnout [46], [11].

350

Drain Currrent (mA/mm)

300 250 200 150 100 50 0 0

V : -0.7 V to 0.5 V in steps of 0.15 V

gs

0.4

0.8

1.2

1.6

Drain Voltage (V)

Figure 3.6. Ids vs Vds charactersitics of lattice matched with 0.3 m gate length.

56

500

Drain Current (mA/mm)

V : -0.7 V to 0.5 V in steps of 0.15 V

gs

400 300 200 100 0

0.4

0.8

1.2

1.6

Drain Voltage (V)

Figure 3.7. Ids vs Vds charactersitics of pseudomorphic HEMTs with 0.3 m gate length.

ft and fmax were calculated from s-parameters measured with the network analyzer. Since h21 is the short-circuit current gain, ft can be determined by determining the frequency at which h21 becomes unity. To estimate fmax we calculate Masons unilateral power gain (U ) from measured s-parameters. In terms of Y-parameters, U is given by [31] |Y21 Y12 |2 4[Re(Y11 )Re(Y22 ) Re(Y12 )Re(Y21 )]

U=

(3.6)

At fmax , U goes to unity. If the cuto frequencies of the device are beyond the measurement range of the network analyzer, a 20 dB/decade linear extrapolation is typically used to estimate ft and fmax . Figs. 3.8 and 3.9 show the cuto frequencies of a 0.3 m lattice matched and pseudomorphic device respectively.

57

ft s of pseudomorphic HEMTs were higher, consistent with their higher transconductance values. The fmax s of both lattice matched and pseudomorphic HEMTs were comparable, though the pseudomorphic structure could be expected to have a higher fmax due to its higher ft . The lower-than-expected fmax of the pseudomorphic devices is due to larger parasitics compared to lattice matched devices, as fmax dependence on parasitics is larger when output conductance is not negligible.

40

40 35 30 25 20 f
max

Current Gain, |h | (dB)

35 30 25 20 15 10 5 0 109 f ~ 70 GHz
t

Unilateral Gain (dB)

21

~ 145 GHz

15 10 5 0

1010

1011

Frequency (Hz)
Figure 3.8. ft and fmax of 0.3 m gate length lattice matched HEMTs.

The DC and RF results of both lattice matched and pseudomorphic HEMTs are summarized in Table 3.1. The table clearly shows that reduction in gate length has favorable eect on transconductance and cuto frequencies. To get a measure of breakdown voltage, we measured the gate voltage induced for a reverse gate

58

40

40 35 30 25 f
max

Current Gain, |h | (dB)

35 30 25 20 15 10 5 0 109 f ~ 92 GHz
t

Unilateral Gain (dB)

21

~ 144 GHz

20 15 10 5 0

10

10

10

11

Frequency (Hz)
Figure 3.9. ft and fmax of 0.3 m gate length pseudomorphic HEMTs.

current of 1 mA/mm with grounded drain and source. The 0.3 m pseudomorphic devices exhibit a mean induced gate voltage of 3.7 V, and the lattice matched HEMTs had a mean value of 9.3 V, indicating that lattice matched devices would have a higher gate-drain breakdown voltage. Both the structures were easily overetched during gate recess. Even in the lattice matched structure with an AlAs etch stop layer, the gate recess etch was dicult to control consistently. In order to reduce the short-channel eects and get more repeatability, another heterostructure design with reduced channel and barrier layer thicknesses (to improve the aspect ratio) and a more eective etch stop was investigated. To avoid possible problems associated with material growth, the layers were all kept lattice matched to InP. The new design had a lattice matched channel and an InP etch stop as shown in Fig. 3.10. Also, InP as a etch stop layer has been shown to improve bias induced kink eect and the frequency dispersion of the transconductance [33].

59

TABLE 3.1 SUMMARY OF FABRICATED LM-HEMT AND P-HEMT RESULTS.

Mean values Lgate (m) gm,dcmax (mS/mm) Vth (V) ft (GHz) fmax (GHz)

LM-HEMT 1.4 361 -0.7 11.6 28.9 0.32 577 -0.3 62.9 143.9

P-HEMT 1.4 306 -0.2 11.5 23.1 0.29 654 -0.36 82.1 136.6

300 n+ InGaAs (contact) A 30 InP (etch stop) A A 115 i InAlAs (barrier) *-*-*-*-*-*-*-* doping*-*-*-*-*-*-*35 i InAlAs (barrier) A 150 i InGaAs (channel) A 2000 InAlAs (buer) A SI InP (substrate)

Figure 3.10. Material structure of modied lattice matched HEMT with reduced layer thicknesses and InP etch stop.

Photoreceivers using InP-based HEMT technology for 40-Gb/s applications found in the literature indicate that as a rule of thumb the cuto frequencies (both ft and fmax ) need to be four times the system bit rate, i. e. 172 GHz for 43 Gb/s [50]. To achieve this level of speed performance, the gate length was further shrunk to 0.1 m. To achieve 0.1 m gate lengths, the thicknesses of the electron beam lithography resists were thinned down to 800/2500/750 of 950 k PMMA/MMA A

60

(8.5) MAA/50 k PMMA by diluting the resists and re-optimizing the spin speeds. The lithographic conditions and developing time were correspondingly readjusted. A typical fabricated 0.1 m T-gate structure is shown in Fig. 3.11.

Figure 3.11. SEM image showing end view of 0.1 m T-gates.

Due to the small etch window in 0.1 m devices, a wetting step with isopropyl alcohol was employed prior to gate recess etching to improve gate recess wet etch uniformity and reproducibility [16]. Wet etching with citric acid was further assisted by means of ultrasonic agitation. The InP etch stop was left in place before gate metallization due to lack of a highly selective wet-etchant against InAlAs. DC and RF results of devices made in the modied structure were measured on-wafer as described earlier. The 0.1 m device exhibits a maximum transcon-

61

ductance as high as 706 mS/mm (Fig. 3.12), better than the 0.3 m devices made in the earlier structures.

500

800 700

Transconductance (mS/mm)

Drain Current (mA/mm)

400 300 200 100 0

600 500 400 300 200 100 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.4

Gate Voltage (V)

Figure 3.12. Ids vs Vgs charactersitics of 0.1 m gate length device.

The drain current dependence on drain voltage was free from kink eect observed in the devices fabricated earlier (most likely due to the passivation provided by InP etch stop layer) as shown in Fig. 3.13. The device exhibits an output conductance of 156 mS/mm and a mean gate-drain breakdown voltage of 3.2 V for the 0.1 m devices and 7.5 V for the 1.2 m devices. Using measured s-parameters, the maximum projected ft and fmax were 193 GHz and 218 GHz (Fig. 3.14), enough to design lumped element ampliers for 40 Gbps receivers [48]. A summary of DC and RF results is tabulated in Table 3.2.

62

600

Drain Current (mA/mm)

V : -650 mV to 250 mV in steps of 75 mV 500 400 300 200 100 0

gs

0.5

1.5

Drain Voltage (V)

Figure 3.13. Ids vs Vds charactersitics of 0.1 m gate length device.

50

50

Current Gain, |h | (dB)

Unilateral Gain (dB)

40 30 20 10 f ~ 193 GHz
t

40 30 f ~ 218 GHz 20 10 0 1010 1011

21

max

0 109

Frequency (Hz)
Figure 3.14. Current gain and Masons Unilateral power gain of 0.1 m gate length device.

63

TABLE 3.2 SUMMARY OF DC AND RF RESULTS FOR THE MODIFIED LM-HEMT.

Mean values Lgate (m) gm,dcmax (mS/mm) Vth (V) ft (GHz) fmax (GHz) 3.2 Device modeling

modied LM-HEMT 1.2 423 -0.12 18.9 33.1 0.1 676 -0.55 185 202

For circuit design, a scalable, simple model that accurately reects the actual device performance is essential. The EEHEMT model included in Agilent-EEsofs IC-CAP data acquisition and modeling software was used to model our devices [1]. It is a measurement-based empirical analytic model, i. e., there is no direct relationship between the model equations and basic physical laws. Parameter extraction was based on tting the model equations to the measured data. The equivalent circuit topology used in the EEHEMT model is given in shown Fig. 3.15. The circuit can be divided into two parts: intrinsic and extrinsic elements. Extrinsic elements include the parasitic inductances (Lg , Ls , Ld ), parasitic resistances (Rg , Rs , Rd ) and the capacitances (Cxgd , Cxds , Cxgs ), while the intrinsic elements include all other parameters. Dispersion eects are modeled using Rdb , Cdb and a non-linear source Idb (Vgs , Vds ). Ris , Rid and the gate charges Qgc and

64

Cxgd

Igd Gate Lg Rg + Qgy Igs + Qgc Ris Rid Ids Cbs Rdb Idb Cdso Rd Ld Drain

Rs Cxgs Cxds

Ls

Source

Figure 3.15. EEHEMT circuit schematic [1].

Qgy are used to model charging delay between depletion region and the channel. The charges are simple closed form expressions whose derivatives t typical observed bias dependencies in capacitance data for HEMTs. Output charge delay is modeled using a constant output capacitance Cdso . Forward conduction in the gate contact is modeled using Igs which has the normal exponential diode current dependence on Vgs . Most of the intrinsic parameters are bias dependent, while the extrinsic parameters are not. Since the intrinsic device has a modied -topology, it is convenient to use the admittance (Y) parameters to characterize its electrical properties. After determining the extrinsic elements, the intrinsic admittance was found by de-embedding the extrinsic elements.

65

The source resistance is extracted using the Yang-Long method [60]. This method computes the value of Rs from changes in Vgs due to application of two drain currents, which are 50 to 100 times greater than the gate current in the linear region. Once Rs is known, Rg and Rd can be extracted by the cold FET method made with the gate strongly forward-biased at zero drain-source voltage [10]. Though the original formulation of the cold FET method assumed Vds and Vgs to be zero to optimize contact resistances and parasitic inductances of the bond wires, further simplication can be achieved by strongly forward biasing the gate [2]. This is because in strong gate forward bias, the intrinsic gate charge model of the FET is shunted by the small resistances of the forward active diode and the fully open channel between drain and source. Both the drain and gate resistances are separable if the value of source resistance is known by an independent method, such as Yang-Long. In addition to the access resistances, this method also can yield an estimate of the lead inductances by evaluating the imaginary part of the s-parameters during the cold-FET measurement. These values were then used as starting points to get better approximations in the Arnold-Golio method [3], where s-parameters were measured for a number of Vgs biases at the nominal Vds operating point. Since the lead inductances are independent of bias, they can be readily extracted by evaluating the device s-parameters over a range of bias conditions. The DC I-V parameters (e.g., transconductance, threshold voltage) are extracted once the extrinsic elements are known. Fig. 3.16 shows the modeled and measured drain current dependence on gate voltage and Fig. 3.17 shows the drain current dependence on drain voltage. Four dierent measurement setups were used to establish the values of these parameters from their preliminary estimates.

66

500

800 700

Transconductance (mS/mm)

Drain Current (mA/mm)

400 300 200 100 0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2

600 500 400 300 200 100 0 0.4

Gate Voltage (V)

Figure 3.16. Measured (symbols) and modeled (solid) Ids vs Vgs charactersitics.

600

Drain Current (mA/mm)

500 400 300 200 100 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4

Drain Voltage (V)

Figure 3.17. Measured (symbols) and modeled (solid) Ids vs Vds charactersitics.

67

Then the charge and dispersion parameters were extracted from s-parameter data measured at dierent bias points. A built-in transform with IC-CAP was used to compute the linear equivalent circuit parameters based on the measured sparameter data. The actual model parameters were extracted from this linear equivalent circuit data [2]. The measured and modeled s-parameters for various Vgs at a constant Vds of 1.3 V are shown in Figs. 3.18, 3.19, 3.20. The device shows peak ft at Vgs of -0.2 V and a Vds of 1.3 V. Since the variation of ft typically saturates with Vds , the performance of the model is shown for dierent Vgs values. Forward transmission, s21 , in the model is slightly pessimistic and hence circuits designed using this model are expected to exhibit more gain than predicted by the simulator. The cut-o frequencies predicted by the model were 167 GHz for ft and 216 GHz for fmax against measured (extrapolated) values of 193 GHz and 218 GHz respectively. The performance projected by the model is sucient to design lumped element 40 Gbps receivers.

68

-15 -20

90 80

Magnitude (dB)

-25 -30

Phase (deg)

70 60

-35 -40 -45 -50 0 5 10 15 20 25 30 35 50 40 30

Frequency (GHz)

s11
20 180

s12

Magnitude (dB)

15

160

Phase (deg)

10

140

120 5 100 0 0 5 10 15 20 25 30 35

Frequency (GHz)

s21

s22

Figure 3.18. Measured (symbols) and modeled (solid) s-parameters for Vgs =0 V and Vds =1.3 V.

69

-15 -20

90 80

Magnitude (dB)

-25 -30

Phase (deg)

70 60

-35 -40 -45 -50 0 5 10 15 20 25 30 35 50 40 30

Frequency (GHz)

s11
20 180

s12

Magnitude (dB)

15

160

Phase (deg)

10

140

120 5 100 0 0 5 10 15 20 25 30 35

Frequency (GHz)

s21

s22

Figure 3.19. Measured (symbols) and modeled (solid) s-parameters for Vgs =-0.2 V and Vds =1.3 V (corresponds to peak ft , high gain).

70

-10 -15

90 80 70 60 50 40 30 5 10 15 20 25 30 35 20

Magnitude (dB)

-20 -25 -30 -35 -40 -45 -50 0

Phase (deg)

Frequency (GHz)

s11
20 180

s12

Magnitude (dB)

15

160

Phase (deg)

10

140

120 5 100 0 0 5 10 15 20 25 30 35

Frequency (GHz)

s21

s22

Figure 3.20. Measured (symbols) and modeled (solid) s-parameters for Vgs =-0.5 V and Vds =1.3 V (low noise bias condition).

71

CHAPTER 4 PHOTORECEIVERS

The important performance characteristics of a photoreceiver are operating bandwidth/bit rate, sensitivity, and dynamic range. While bandwidth determines the speed of the receiver, sensitivity and dynamic range encompass essential properties of the received signal, such as extinction ratio, signal distortions and intersymbol interference (ISI). Receiver sensitivity is dened as the minimum average optical power level needed to achieve a particular bit error rate (BER). Dynamic range is the ratio of maximum to minimum average optical power with a given BER, and represents the range of input signal levels over which the receiver is usable. Typically a BER of 109 is required for long-haul ber optic communication systems, but this value depends on the data rate and the modulation format used for transmission. The bandwidth requirement of the photoreceiver is also dictated by the coding scheme and the transmission bit rate of the system. Typically, Return-to-Zero (RZ) schemes where the optical pulses occupy only a fraction of the bit duration have larger bandwidth requirements than NonReturn-to-Zero (NRZ) schemes, where the optical pulse duration equals the bit duration. Depending on the system, modulation formats can be made to utilize bit-correlations to make a format more resilient to distortions accumulated along the ber. For a given average optical power at the receiver, RZ coding yields improved sensitivity over NRZ [38]. Though RZ coding leads to enhanced system 72

performance, it comes at the expense of higher bandwidth requirements, as well as more complicated transmitter structures [55].

bias iph Output Amplifier iph

bias iph Output Amplifier Equalizer

bias

Output Amplifier

(a)

(b)

(c)

Figure 4.1. Common receiver topologies: (a) low impedance design (b) high impedance design (c) transimpedance design.

The choice of preamplier topology plays an important role in determining the overall photoreceiver performance. Fig. 4.1 shows the three basic topologies commonly used in integrated photoreceivers: 1) low impedance design, 2) high impedance design, and 3) the transimpedance design [45]. The low impedance design is the easiest to monolithically integrate and was used in many of the early OEIC receivers, but it suers from poor sensitivity due to high Johnson noise arising from the input shunt resistor [34], [25]. The high impedance design overcomes this problem, but the input admittance is dominated by the total input capacitance. This leads to low bandwidth and usually requires an equalization circuit to extend the bandwidth [27]. The transimpedance design, in its simplest form, is an inverting voltage amplier with resistive feedback from output to input. The circuit architecture in this case can be designed to compensate for the

73

reactive impedance presented by the photodiode and hence eliminates the need for post-equalization. In general, the noise performance of transimpedance ampliers is usually not as good as can be achieved with a high impedance amplier. This is mainly due to the eect of feedback resistance on the frequency response of the amplier. With proper design, the noise performance of transimpedance amplier can almost match that of high-input impedance design. Kuebart et al. [30] have compared all three topologies for a PIN-HEMT receiver and shown experimentally that the transimpedance design achieved the highest sensitivity for the same bandwidth as the other designs. Hence a transimpedance amplier would oer good sensitivity and better bandwidths than high impedance design without need for equalization. The transimpedance amplier also has better dynamic range than that of high impedance front end. This is because in the high impedance amplier, the low frequency components which are attenuated by the equalization process cause saturation of the amplier prior to the equalizer at high signal levels. In the transimpedance amplier, attenuation of the low frequency components is achieved via negative feedback and hence the low-frequency components are amplied by the closed-loop, instead of the open-loop gain of the amplier. This leads to an improvement in the dynamic range of the amplier by approximately the ratio of the open- and closed-loop gains [45]. Due to its potential for high bandwidth, large dynamic range, and good noise performance, in this work, we chose to design a transimpedance receiver.

74

4.1 Transimpedance amplier design The most common transimpedance amplier (TIA) conguration is the shuntshunt feedback topology, where a negative feedback network senses the voltage at the output and returns a proportional current to the input. This conguration lowers both the input and output resistances; lowering input resistance improves the input pole magnitude and hence leads to higher bandwidth and lowering output resistance leads to better current drive capability. For the simple topology shown in Fig. 4.2, where RF provides feedback around an ideal voltage amplier, the transimpedance gain (ZT ) is given by (neglecting the input conductance of the amplier and the photodetector), ARF A + 1 + sRF CD

ZT =

(4.1)

where A is the open-loop voltage gain of the amplier, CD is the sum of photodiode and amplier input capacitances, and RF is the feedback resistance. The maximum transimpedance gain possible using this conguration is limited by RF . So to increase the transimpedance gain we need to increase RF , but this would lower the bandwidth, as larger RF reduces the input pole magnitude. Due to this tradeo, a gure of merit used to characterize a TIAs high speed performance, independent of the feedback resistance, is the transimpedance-bandwidth product (TZBW). For the amplier in Fig. 4.2, using ZT at low frequencies, TZBW can be approximated by [28], A 2CD

T ZBW =

(4.2)

75

RF

-A Iin CD

Vout

Figure 4.2. Simple feedback transimpedance amplier.

Improvement in amplier design and the transistor structure leads to better A, while monolithic integration and device scaling leads to reduced CD . Similar to TZBW for the amplier, to evaluate the performance of the photoreceiver (amplier + photodetector), the responsivity-bandwidth product is commonly used.

4.1.1 Single-ended design A simple way to implement the core amplier shown in Fig. 4.2 is to use a common source amplier. But, if the common source stage were to drive a low impedance load, there will be loss of signal level at the output. So a source follower is usually used as a buer to isolate the loading eect of the output stage. The source follower also provides a low capacitance load to the common source stage. A transimpedance amplier with a common source amplier and a source follower output designed using a 0.1 m HEMT model developed earlier is shown in Fig. 4.3. Since the HEMT models used in the simulation were for discrete 76

7V

RD=100

5.3 V

H2 Vout H1 Photodiode 3V RF=225 2.8 V D1 D2 D3

RC1=30 1.1 V RC2=120 -0.2 V H4 H3

Figure 4.3. Feedback common source amplier with source follower output.

devices, the parasitic capacitances and inductances due to the probe pads were neglected during the simulation. Gate nger inductance was estimated using sparameters measured on shorted devices and was included in the model. Level shifting diodes were used to appropriately bias the circuit so that all the transistors are biased very close to their peak ft values. The level shifters are modeled as forward biased gate Schottky contacts with drain and source contacts shorted. All 77

transistors in the design are 100 m wide with two ngers, similar to the discrete devices used for modeling, except for the level shifters which were 500 m wide with ve ngers. The level shifters require wider devices because the gate diode needs to carry the high bias current with a reasonable forward bias voltage. A cascode current source is used to bias the source follower as it gives a high output impedance. The damping resistors Rc1 and Rc2 were added to the transistor gates in the current source to suppress oscillations at high frequencies.
1 If the output impedance of the source follower, gm2 , is much less than RF , the

open loop voltage gain of the core amplier is approximately equal to gm1 RD and the low-frequency closed loop transimpedance gain is given by (from Eqn. 4.1), gm1 RD RF 1 + gm1 RD

ZT =

(4.3)

This suggests that to improve the transimpedance gain we need to increase RF , which as mentioned earlier comes at the cost of bandwidth. Since bandwidth cannot be estimated analytically due to the complex non-linear nature of the HEMT model, we used the Agilent ADS simulator to maximize TZBW. Using the simulator, the feedback amplier gave a low-frequency transimpedance gain of 180 with a bandwidth of 53 GHz. Since practical 40 Gbps systems require a gain of 1 k to 5 k [29], we need to increase the gain further. This can be achieved by cascading more stages to the amplier. It is important to recognize that the TIA of Fig. 4.3 exhibits an inductive output impedance. This is because, as the frequency increases, the feedback becomes weaker, lowering the loop gain [41]. This inductive output impedance may lead to ringing if the circuit drives substantial load capacitance. If the cascaded amplier stage were to have feedback within the common source stage, the output node of

78

the source follower in Fig. 4.3 would see a resistive component in addition to the gate capacitance which can be used to control ringing. Such a cascaded stage also makes biasing easier. Keeping the 3-dB bandwidth to at least 50 GHz and maximizing the gain, we added three more stages to the feedback amplier as shown in Fig. 4.4. This conguration leads to a transimpedance gain of 4550 (73.2 dB) and a 3-dB bandwidth of 50 GHz (Fig. 4.5). For the dual depletion photodiode (TA5000) with a responsivity of 0.3 A/W, this corresponds to a responsivity of 1350 V/W. These results do not include the eect of interconnect parasitics. Since the interconnects are short, they are not expected to degrade the performance greatly. Assuming a lumped element RLC model for interconnects between transistors in the signal path with a series inductance of 20 pH, a series resistance of 10 , and a capacitance (to ground) of 1 fF, the bandwidth and gain of the amplier was found to remain almost the same. The series resistance of the parasitics themselves are not expected to be as high as 10 , but this serves as a worst-case estimate. Inductive peaking from the interconnects can even be exploited to improve the performance of the circuit by careful modeling and design.

79

7.3 V

12.2 V 200

10.7 V 100 7.6 V 9.2 V 500 H6 H10 H9 6.6 V H7 6.2 V 120 H8 3.2 V 4.7 V H12 4.9 V 30 H11 500

12.2 V 100

100

6.1 V 500 H2 H5

Vout

H13 8.1 V

H1 Photodiode 3V 270 3.2 V

D1 D2 D3

5V 4.3 V

30

120 3V

80
-0.2 V

30 1.3 V 120 H4 H3

Figure 4.4. Transimpedance amplier with four amplifying stages.

Transimpedance gain (dB)

75

200 150 100

Phase (deg.)

70

50 0

65

-50 -100 -150

60

10

20

30

40

50

-200 60

Frequency (GHz)
Figure 4.5. Transimpedance gain assuming open load.

The noise performance of the HEMTs was estimated using the equivalent circuit modeled to characterize its performance (Fig. 3.15). The noise model assumes resistors Rg , Rs , Rd , Ris , Rid , and Rdb included in the EEHEMT model generate thermal noise with spectral density, 4kT < i2 > = f R

(4.4)

where k is the Boltzmanns constant, T is the simulation temperature (taken to be 290 K), q is the electron charge, and f is the noise bandwidth. Channel noise generated by the DC transconductance gm was characterized by assuming a spectral density given by [1],

81

< i2 > 8kT gm = f 3

(4.5)

The model neglects icker noise, and assumes all the thermal noise sources are uncorrelated. The thermal noise contribution of all resistors external to the device were included with a spectral density similar to Eqn. 4.4. Including these noise sources in a two port s-parameter simulation, the noise parameters of the circuit were calculated. For any source admittance Ys , the noise gure of a two-port network is given by [17], Rn |Ys Yopt |2 Gs

F = Fmin +

(4.6)

where Fmin is the minimum noise gure, Rn is the equivalent noise resistance of the circuit, and Yopt is the optimum source admittance for the circuit which results in the minimum noise gure. Alternatively, the system can also be characterized by noise temperature, Te , related to noise gure by, Te T0

F =1+

(4.7)

where T0 is the ambient temperature, usually 290 K. Since noise gure and noise temperature denitions assume a matched input source [39], the equivalent noise temperature Te of the circuit can be calculated using the conjugate of input admittance of the circuit (determined from s11 ) for the source admittance. Using Te , the equivalent input-referred noise current of the circuit can be calculated. Sensitivity for a particular BER can be estimated by the relation [45],

82

 Q P =

< i2 > c

(4.8)

where < i2 > is the total input-referred noise current, Q is a parameter related c to the BER (Q=6 for BER=109 , Q=7 for BER=1012 etc.), and is the re-

sponsivity of the photodetector. The total input-referred current is calculated by integrating the input-referred noise current obtained earlier from Te over the noise bandwidth. The noise bandwidth for a system is dened by [18], 1 A2 0

fN =

|A(f )|2 df
0

(4.9)

where A is the gain of the circuit, and A0 is the low frequency gain. This denition gives a noise bandwidth of 70 GHz for our amplier. Using these relationships, a sensitivity of -8.6 dBm is projected for the TIA based receiver assuming the diode structure of TA5000 with responsivity of 0.3 A/W. For a receiver based on photodiode design AA7000, with a responsivity of 0.38 A/W, this corresponds to a responsivity of -9.6 dBm. These responsivity values were measured without any anti-reection coating. If silicon nitride was used as a anti-reection coating, we could expect a 30 % improvement in responsivity leading to a sensitivity of -10.7 dBm. A standard 40 Gbps (231 -1) RZ PRBS test pattern assuming a peak input photocurrent of 100 A was used to generate the output eye diagram shown in Fig. 4.6. The eye diagram includes thermal noise in the system calculated with the knowledge of noise bandwidth estimated using s-parameter simulation. The open eye indicates that the eect of ISI is not signicant, and the receiver has sucient noise margin. The transimpedance gain can be further increased by including more stages, but adding further stages would decrease the dynamic range of the receiver and 83

Figure 4.6. Eye diagram of the output waveform for a 40 Gbps RZ PRBS pattern of length (231 1).

add more complexity to the receiver. Also, adding further stages will require accurate modeling of interconnect parasitics to calculate the performance metrics as they can play a signicant role in determining the performance of the circuit. Since the input stage has both current and voltage gain, adding further stages will not have a signicant penalty in the noise performance of the receiver. A summary of recent TIA work is given in Table 4.1. The table compares the results which have the best TZBW for dierent technologies reported so far, including this work. Though our design does not include interconnect parasitics, with proper layout and design the amplier can achieve bandwidths and gain very close to the best reported values.

4.1.2 Dierential design The dual-absorption photodiode design evaluated earlier had a maximum bandwidth of 30 GHz. This bandwidth would suce for 40 Gb/s NRZ systems, but RZ scheme requires higher bandwidths for optimum performance [56]. Since the 84

TABLE 4.1 STATUS OF HIGH-SPEED TRANSIMPEDANCE AMPLIFIERS.

Technology InP HEMT GaAs MHEMT InP HBT SiGe HBT InP HEMT

Bandwidth (GHz) 49 50 60 50 50

ZT (dB) 52 66 71 49 73

Reference Shigematsu et al. (2001) [44] Roux et al. (2003) [42] Kobayashi (2003) [29] Weiner et al. (2000) [52] This work

dual-absorption design is essentially two diodes stacked on top of each other and is dominated by RC-limited bandwidth, we can improve the bandwidth if we decouple the two diodes and feed the outputs to a dierential TIA. Since practical limiting ampliers and clock and data recovery circuits which follow the TIA in a full receiver system are typically dierential [40, 42], there is a need to convert single-ended output from a photodiode to dierential anyway. To estimate the bandwidths of each half-diode from the measured parameters, we used the analytical simulation technique developed for the dual depletion diodes. The equivalent circuit parameters of the half-diodes were estimated from the extracted values for a drift-enhanced dual-absorption diode in Table 2.1 by using the half-diode junction areas (from the mask layout) to calculate the junction capacitance and depletion resistance, and by halving the parasitics (series resistance, series inductance, and parasitic capacitance). The resulting equivalent circuit, combined with the transit-time limit obtained using the previously obtained drift velocities, leads to bandwidths of 50 GHz and 39 GHz for the top and bottom half-diodes respectively, sucient for 40 Gb/s RZ schemes.

85

However, the output current of both the half-diodes in a dual-absorption design have the same phase, so to use a dierential amplier, we need to have a broadband phase dierence of 180 between the two inputs. This was achieved by using a simple inverting common source amplier. The closed-loop transimpedance amplier stage used in the single-ended receiver with a common source stage at its output does oer 180 phase dierence at low frequencies with another identical transimpedance stage with source follower at its output, but the phase dierence degrades for frequencies above 20 GHz. Using an open-loop common gate amplier as the input transimpedance stage with a common source stage in one of the common gate output segments and a source follower in the other, the voltage waveforms achieve a broadband 180 phase dierence (Fig. 4.7). The gain of both the stages were designed to be very close to each other; the dierence in the output voltages were due to the dierence in the currents generated in the top and bottom half-diodes. The schematic of the complete dierential design is shown in Fig. 4.8. Transistors H1 H3 and H14 H16 form the input common gate transimpedance stage to the half-diodes. Transistors H4 H6 form a source follower and transistors H11 H13 form the inverting common source feeding into the dierential amplier. The source follower fed by the common gate stage reduces the output impedance, and keeps the poles at the inputs of the dierential amplier comparable. The biasing was done such that the DC bias points at the input of each arm of the dierential pair was matched and all the transistors were at their peak ft s. The current source transistors H9 and H10 are 200 m wide to accomodate larger bias current through them, all other devices are 100 m wide. All the transistors had gate length of 0.1 m.

86

50 40 30 20 10 0 Vo1 Vo2

200 150 Vo1 Vo2

Magnitude (mV)

Phase (deg.)
60

100 50 0 -50 -100 -150

10

20

30

40

50

-200

10

20

30

40

50

60

Frequency (GHz)

Frequency (GHz)

(a)

(b)

Figure 4.7. (a) Output voltage magnitude of the transimpedance stages for a 1 mW incident optical power - Vo1 corresponds to the common gate stage followed by a source follower (top diode); Vo2 corresponds to a common gate amplier followed by a common source stage (bottom diode) (b) Vo1 and Vo2 showing a 180 broadband phase dierence.

87

10.1 V 8.4 V 100 100 7V

Vout

10.1 V 8.4 V 100 H11 120 H12 5.6 V H8

Vo2

30 6.9 V 7.1 V 100

4.1 V

50 H1 4.3 V 30 3 V 120 H2

H4

Vo1

H7

H5 H6 3.2 V 4.5 V 3.2 V 30 H9 120 H10

H13 4.5 V H14

50 2.4 V

2.8 V

30

88
3V

1.5 V 120
Photodiode

30 H15 1.1 V 120 H16 -0.2 V

H3 1.7 V 3.4 V

Figure 4.8. Dierential transimpedance amplier using a drift-enhanced dual-absorption photodiode at the input.

Using the measured responsivity of the drift-enhanced dual-absorption diode, a 1 mW input optical power would lead to 506 A of photocurrent in the top half-diode, and 314 A in the bottom half-diode. Using these diodes in the differential amplier design shown in Fig. 4.8, we get a output voltage of 243 mV (corresponding to a transimpedance gain of 296 ) with a 3-dB bandwidth of 44 GHz as shown in Fig. 4.9. If the same conguration is used with single absorption layer design (AA7000), we get a output voltage of 150 mV with the same bandwidth. This corresponds to a responsivity-bandwidth product of 22.3 GHz-A/W for the single ended design and 36.1 GHz-A/W for the dierential design.

300

200 150

Output voltage (mV)

250

Phase (deg.)

100 200 50 0 150 -50 100 -100 60

10

20

30

40

50

Frequency (GHz)
Figure 4.9. Output voltage of the dierential amplier corresponding to 1 mW optical power.

89

Figure 4.10. Eye diagram for the dierential transimpedance amplier for a 40 Gbps PRBS pattern of length (231 1); each division corresponds to 50 mV.

The noise performance of the circuit was analyzed considering all the thermal noise sources similar to the single-ended design. To calculate the input referred noise current, a four port s-parameter simulation of the circuit was done in ADS. Using the current correlation matrix generated, the corresponding matrix of the equivalent two port for common mode input and dierential output can be calculated. Using these values and the Y -parameters of the circuit, the noise parameters of the two port was calculated, from which input referred noise current was inferred as in the case of single-ended amplier. Using the measured responsivity of 0.82 A/W for the drift enhanced dual absorption photodiode, this leads to an estimated sensitivity of -6.93 dBm. The low sensitivity is mainly due to the low gain of the input common gate stage. The output corresponding to a standard (231 1) 40 Gbps RZ PRBS pattern with 1 mW of incident optical power is given in Fig. 4.10. The open eye shows that the receiver has sucient bandwidth for 40 Gbps performance. Thus the dierential design combined with the dual absorption photodiodes provides an improved bandwidth-responsivity product compared to single ended design. 90

CHAPTER 5 SUMMARY

5.1 Conclusions High speed photodiodes and HEMTs in the InP material system essential for photoreceivers in long-haul ber-optic communication systems have been designed and fabricated. Photodiodes with bandwidths as high as 60 GHz with a responsivity of 0.3 A/W have been demonstrated. A novel drift-enhanced

dual-absorption photodiode design was proposed and demonstrated to ease the bandwidth-eciency tradeo common in PIN detectors. Diodes fabricated using this design achieved bandwidths of 30 GHz into a 50 load with a responsivity of 0.82 A/W. Theoretical models indicate that the drift-enhanced dual-absorption design can achieve 24% improvement in bandwidth-eciency over the conventional top-illuminated PIN photodetectors. Since photodiodes need electronic preamplication, high frequency HEMTs with gate lengths as small as 0.1 m were demonstrated using electron beam lithography. The T-gate structure developed for these short gate HEMTs allowed these transistors to achieve cuto frequencies over 200 GHz. Non-linear models were developed to describe the performance of both the high-speed photodiodes and the HEMTs. These models were used to design monolithic PIN/HEMT transimpedance photoreceivers. Using the dual-depletion photodiodes with 0.1 m HEMTs, a single-ended transimpedance amplier was

91

designed which achieved a gain of 4.5 k with a 50 GHz bandwidth, corresponding to a better TZBW than the best reported value in the literature for HEMT based TIAs. A novel dierential transimpedance amplier design using dual-absorption photodiodes was proposed to ease the responsivity-bandwidth product further. This design achieved better responsivity than conventional designs and makes the dual-absorption photodiode a very attractive candidate for the high-speed higheciency photoreceivers required in long-haul ber-optic communication systems.

5.2 Future work The dual-absorption design can be easily extended to improve the eciency of other photodetector architectures. For example, UTC-PDs rely on absorption in a doped (undepleted) layer with subsequent electron injection into a non-absorbing wide-bandgap drift layer. Since UTC-PDs depend only on electrons for carrier transport, they are much faster than conventional photodiodes where holes play a signicant role. But the UTC-PD structure is inherently limited in responsivity due to the thin absorption layer in its design. By extending the dual-absorption concept to UTC-PDs, this limitation can be eased considerably. The dual-absorption design combined with the proposed dierential TIA design leads to some interesting possibilities and requires further investigation. The photoreceivers need to be optimized as a whole to improve their bandwidthresponsivity product. Noise characterization of both the single-ended and differential TIAs needs to be done to understand the limitations of the noise model and to better estimate the sensitivity of the photoreceiver.

92

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