Chapter 07 Notes

Digital Design: An Embedded Systems Approach Using VHDL
Chapter 7 Processor Basics
Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
VHDL
Embedded Computers p
A computer as part of a digital system
Performs processing to implement or control the systems function y
Components
Processor core Instruction and data memory Input, output Input output, and input/output controllers
For interacting with the physical world
Accelerators
High-performance circuit for specialized functions
Interconnecting buses o g bu
Digital Design Chapter 7 Processor Basics 2
VHDL
Memory Organization y g
Von Neumann architecture
Single memory for instructions and data
Harvard architecture
Separate instruction and data memories Most common in embedded systems
C U CPU Instruction memory Data memory Accelerator cce e ato
Input controller
Output controller
I/O controller
Digital Design Chapter 7 Processor Basics
VHDL
Bus Organization g
Single bus for low-cost low-performance g p systems Multiple buses for higher performance p g p
Data memory Accelerator
Instruction memory
CPU
Input controller
Output controller
I/O controller
VHDL
Bus Organization g
Traditional Bus Topology
VHDL
Bus Organization g
Typical Switch Fabric Topology
VHDL
Bus Organization g
Alteras System Interconnect Fabric Example
VHDL
Bus Organization g
Alteras Memory-Mapped and Streaming System Interconnect Fabrics
SRIO: Serial RapidIO is a highperformance, point-topoint, packet-switched interconnect technology defined by the RapidIO Trade Association. Full duplex point to point Full-duplex point-to-point links are established with single or multiple highspeed serial lanes (1x and 4x are currently defined), and industry-standard industry standard 8B/10B-encoded data transmission at signaling rates of 1.25, 2.50, or 3.125 Gbaud for peak bandwidth of up to 20 Gbps.
VHDL
Microprocessors p
Single chip Single-chip processor in a package External connections to memory and I/O b buses Most commonly seen in general purpose computers
E.g., E g Intel Pentium family, PowerPC, family PowerPC
VHDL
Microcontrollers
Single chip combining g p g
Processor A small amount of instruction/data memory y I/O controllers
Microcontroller families
Same processor, varying memory and I/O
8-bit microcontrollers
Operate on 8-bit data Low cost, low performance
16-bit and 32-bit microcontrollers

Higher performance
NXPs 50-MHz ARM CortexM0-based LPC1100 microcontroller family represents the latest 32-bit challenge to 8- and 16-bit processors. The parts are available now with prices starting at 65 to 95 cents (10,000). CoreMark Benchmark measures 40 to 50% better 0 0% b code density for the LPC1100 than that of 8- and 16-bit 10 microcontrollers.
VHDL
Processor Cores
Processor as a component in an FPGA or ASIC In FPGA, can be a fixed-function block FPGA
E.g., PowerPC cores in some Xilinx FPGAs
Or O can be a soft core b ft

Implemented using programmable resources E.g., Xilinx MicroBlaze, Altera Nios-II
In ASIC, provided as an IP block

E.g., ARM, PowerPC, MIPS, Tensilica cores Can be customized for an application
VHDL
Digital Signal Processors g g

DSPs are processors optimized for signal processing operations
E.g., audio, video, sensor data; wireless E di id d t i l communication
Often combined with a conventional core for processing other data

Heterogeneous multiprocessor
12
VHDL
Instruction Sets
A processor executes a program
A sequence of instructions, each performing a small step of a computation p p
Instruction set: the repertoire of available instructions

Different processor types have different instruction How are new instructions chosen to be sets added to Instruction Set?
High-level languages: more abstract

E.g., C C++ Ada E g C, C++, Ada, Java Translated to processor instructions by a compiler
CPU _ time = IC (CPI execution + Memory _ stall _ cycles M t ll l ) Clock _ period Instruction
13
VHDL
Instruction Execution
Instructions are encoded in binary
Stored in the instruction memory
A processor executes a program by repeatedly

Fetching the F t hi th next i t ti t instruction Decoding it to work out what to do Executing the operation
Program counter (PC) g ( )

Register in the processor holding the add ess o t e e t st uct o address of the next instruction
VHDL
Data and Endian-ness

Instructions operate on data from the data memory p y Byte: 8-bit data
Data memory is usually byte addressed
16-bit, 32-bit, 64-bit words of data 6 bi 32 bi 6 bi d fd

Little endian
0 8-bit data 0
Big endian
8-bit data
m m+1
least sig. byte g y most sig. byte
16-bit data
m m+1
most sig byte sig. least sig. byte
16-bit data
Little endian Intel x86
LSB=lowest address
Big endian
n least sig. byte l i b 32-bit data most sig byte sig. n n+1 n+2 n+3 least sig. byte l i b most sig. byte
n+1 n+2 n+3
PowerPC
32-bit data
MSB=lowest address
15
VHDL
The Gumnut Core

A small 8 bit soft core 8-bit
Can be used in FPGA designs
Instruction set illustrates features typical of 8bit cores and processors in general Programs written i assembly language P itt in bl l
Each processor instruction written explicitly Translated to binary representation by an assembler
Resources available on companions web site R il bl i b it
16
VHDL
Gumnut Storage g
General-Purpose Registers
How many registers should you encode for in the instruction? Two? Three? How many registers should there be?
Condition Code Registers

C Z
r0 r1 r2 r3 r4 r5 r6 r7
Carry Zero Program C P Counter
PC
Data Memory (256 8-bit, 8-bit addresses)

0 1 2 0 1 2
Instruction Memory (4K 18-bit, 12-bit addresses)
254 255
4094 4095
17
VHDL
Arithmetic Instructions
Operate on register data and put result in a register
add, addc, sub, add addc sub subc Can have immediate value operand
Condition d C diti codes

Z: 1 if result is zero, 0 if result is non-zero C: carry out of add/addc, borrow out of sub/subc
addc and subc include C bit in operation p

VHDL
Arithmetic Instructions
Examples
add add dd sub add add r3, r4, r1 r5, r1, 2 5 1 r4, r4, 1 r4, r4, r3 r4 r4 r4, r4, 1 ; double x ; then add 1
Evaluate 2x + 1; x in r3, result in r4
19
VHDL
Logical Instructions g
Operate on register data and put result in a register
and, or, xor, mask ( d not) d k (and t) Operate bitwise on 8-bit operands Can have immediate value operand
Condition codes
Z: 1 if result is zero, 0 if result is non-zero C: always 0
20
VHDL
Logical Instructions g
Examples p
and or xor and sub r3, r4, r5 r1, r1, 0x80 r5, r5, 0xFF ; set r1(7) ; invert r5
Set Z if least-significant 4 bits of r2 are 0101 g

r1, r2, 0x0F ; clear high bits r0, r1, 0x05 ; compare with 0101
21
VHDL
Shift Instructions
Logical shift/rotate register data and put result in a register
shl, shr, rol, ror hl h l Count specified as a literal operand
Condition codes
Z: 1 if result is zero, 0 if result is non-zero zero C: the value of the last bit shifted/rotated past th end of th b t t the d f the byte
22
VHDL
Shift Instructions
Examples p
shl ror shl shl shl add r4, r1, 3 r2, r2, 4 r4, r4, 3 r1, r4, 1 ; multiply by 2 , , p y y r4, r4, 3 ; multiply by 8 r4, r4, r1
Multiply r4 by 8, ignoring overflow Multiply r4 by 10, ignoring overflow
23
VHDL
Memory Instructions y
Transfer data between registers and data g memory
Compute address by adding an offset to a base register value
Load register from memory

ldm stm ldm r1, (r2)+5 r1, (r4)-2 r3, 23 ldm r3, (r0)+23
Store from register to memory Use r0 if base address is 0 Condition codes not affected
VHDL
Memory Instructions y
Increment a 16-bit integer in memory 16 bit
Little-endian: address location ldm r1, (r2) add r1, r1, 1 stm r1, (r2) ldm r1, (r2)+1 addc r1 r1, 0 r1, r1 stm r1, (r2)+1 of lsb in r2, msb in next ; increment lsb
; increment msb ; with carry
25
VHDL
Input/Output Instructions p / p
I/O controllers have registers that govern their operation
Each has an address, like data memory address Gumnut has separate data and I/O address spaces
Input from I/O register

inp out r3, 157 inp r3, (r7) out r3, (r0)+157 r3, (r7)+0
Output to O t t t I/O register i t Condition codes not affected Further examples in Chapter 8 p p
VHDL
Branch Instructions
Programs can evaluate conditions and take alternate courses of action
Condition codes (Z, C) represent outcomes of (Z arithmetic/logical/shift instructions
Branch instructions examine Z or C

bz, bnz, bc, bnc Add a displacement to PC if condition is true Specifies how many instructions forward or backward to skip
Counting from instruction after branch
27
VHDL
Branch Example p
Elapsed seconds in location 100
Increment, ldm r1, add r1, sub r0, bnz +1 add r1, stm r1 r1, wrapping to 0 after 59 100 r1, 1 r1, 60 ; Z set if r1 = 60 ; Skip to store if r0, 0 ; Z is 0 100
28
VHDL
Jump Instruction p
Unconditionally skips forward or backward to y p specified address
Changes the PC to the address
Example: if r1 = 0, clear data location 100 to 0; otherwise clear location 200 to 0

Assume instructions start at address 10 10: sub r0, r1, 0 11: bnz +2 11 b 2 12: stm r0, 100 13: jmp 15 j p 14: stm r0, 200 15: ...
VHDL
Subroutines
A sequence of instructions that perform some operation
Can call them from different parts of a program using a jsb instruction Subroutine returns with a ret instruction
jsb m m subroutine instructions ret jsb m b
30
VHDL
Subroutine Example p
Subroutine to increment second count
Address of count in r2 ldm r1, (r2) add r1 r1, 1 r1, r1 sub r0, r1, 60 bnz +1 add r1 r0, 0 r1, r0 stm r1, (r2) ret add jsb add jsb r2, r0, 100 20 r2, r0, 102 20 Dgtl ein Chapter 7 Processor Basics ii D s a g
31
Call to increment locations 100 and 102
VHDL
Return Address Stack

The jsb saves the return address for use by the ret
But h t the b ti includes jsb? B t what if th subroutine i l d a j b?
Gumnut core includes an 8-entry p y pushdown stack of return addresses

return addr for third call return addr for second call return addr for first call return addr for second call return addr for first call
32
VHDL
Miscellaneous Instructions
Instructions supporting interrupts
See Chapter 8 reti R t i Return f from i t interrupt t enai Enable interrupts disi Disable interrupts wait Wait for an interrupt stby Stand by in low power mode until an interrupt occurs
33
VHDL
The Gumnut Assembler

Gasm: translates assembly programs
Generates memory images for program text (binary coded instructions) and data (binary-coded See documentation on web site
Write a program as a text file

Instructions Directives Comments C t Use symbolic labels
VHDL
Example Program p g
; Program to determine greater of value_1 and value_2 text t t org 0x000 ; start here on reset jmp main ; Data memory layout t e o y yout data value_1: byte value_2: byte result: bss ; Main program text g org main: ldm ldm sub bc stm jmp value_2_greater: stm finish: jmp 0x010 r1, value_1 r2, value_2 r0, r1, r2 value_2_greater _ _g r1, result finish r2, result finish
10 20 1
; load values ; compare values ; value_1 is greater ; value_2 is greater ; idle loop 35
VHDL
Gumnut Instruction Encoding g

Instructions are a form of information
Can be encoded in binary
Gumnut encoding
18 bits per instruction p Divided into fields representing different aspects of the instruction
Opcodes and function codes The VAX has a computer architecture with easily Register numbers the most complex instruction set. Addresses The instruction set has a highly variable format
where the minimal instruction length is 1 byte and the longest instruction is 37 bytes (296 bits). d h l b ( b )
36
VHDL
Gumnut Instruction Encoding g

Arith/Logical g Register Arith/Logical Immediate Shift Memory, I/O Branch Jump Miscellaneous
4 3 3 3 2 3
1 1 1 0
1 3
rd d
3
rs
3
rs2 2
8
fn f immed
0
3
fn
1
rd
3
rs
3 3
1 1 0
2 2
rd
3
rs
3
count
8
fn offset
1 0
fn
6
rd
2
rs
2
1 1 1 1 1 0
5 1
fn
12
disp addr
3 8
1 1 1 1 0 fn
7
1 1 1 1 1 1 0
fn
37
VHDL
Encoding Examples g p
Encoding for addc r3, r5, 24 r3 r5
Arithmetic immediate, fn = 001
1 3 3 3 8
fn
rd
rs
immed
0 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0
05D18
Instruction encoded by 2ECFC

1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0
6 2 2 8
Branch
1 1 1 1 1 0
fn
disp
bnc -4
38
VHDL
Other Instruction Sets

8 bit 8-bit cores and microcontrollers
Xilinx PicoBlaze: like Gumnut 8051, 8051 and numerous like it
Originated as 8-bit microprocessors Instructions encoded as one or more bytes Instruction set is more complex and irregular Complex instruction set computer (CISC) C.f. Reduced instruction set computer (RISC) Cf R d di i
16-, 32- and 64-bit cores

Mostly RISC E.g., PowerPC, ARM, MIPS, Tensilica,
VHDL
Instruction and Data Memory y

In embedded systems
Instruction memory is usually ROM, flash, SRAM, SRAM or combination Data memory is usually SRAM
DRAM if large capacity needed
Processor/memory interfacing / y g
Gluing the signals together
40
VHDL
Example: Gumnut Memory p y

instruction ROM
clk_i en D Q
gumnut
clk_i rst_i inst_cyc_o inst_stb_o inst stb o inst_ack_i clk data_we_o data we o data_cyc_o data_stb_o data stb o data_ack_i Q D clk we adr dat_i dat_o inst_adr_o inst_dat_i clk_i en
data SRAM
adr dat_o
data_adr_o data_dat_o data_dat_i
41
VHDL

IMem : process (clk) is begin if rising edge(clk) then rising_edge(clk) if inst_cyc_o = '1' and inst_stb_o = '1' then inst_dat_i <= instr_ROM(to_integer(inst_adr_o(10 downto 0))); ( g ( ( ))); inst_ack_i <= '1'; else inst_ack_i <= '0'; end if; end if; end process IMem;
42
VHDL

DMem : process (clk) is begin if rising_edge(clk) then a d t e if data_cyc_o = '1' and data_stb_o = '1' then if data_we_o = '1' then data_RAM(to_integer(data_adr_o)) <= data_dat_o; data_dat_i <= data_dat_o; ; data_ack_i <= '1'; else data_dat_i <= data_RAM(to_integer(data_adr_o)); data_ack_i <= '1'; end if; else data_ack_i <= '0'; d k i ' ' end if; end if; end process DMem; d DM
VHDL
Example: Microcontroller Memory p y

8051 P2 SRAM A(15..8) D D Q LE A(16) WE OE CE A(7..0)
P0 ALE PSEN WR RD
PSEN (program store enable)
44
VHDL
32-bit Memory y
Four bytes per memory word
Little-endian: lsb at least address Big endian: Big-endian: msb at least address
0 4 8 1 5 9 2 6 10 3 7 11
Partial-word read
Read all bytes, processor selects those needed
Partial-word write
Use byte-enable signals
VHDL
Example: MicroBlaze Memory p y

Addr dd Data_Write AS Write_Strobe Byte_Enable(0) Byte_Enable(1) Byte Enable(1) Byte_Enable(2) Byte_Enable(3) Read_Strobe Data_Read Data Read 8:15 A D_in D_out en wr clk SSRAM 16:23 A D_in D_out en wr clk SSRAM 24:31 A D_in D_out en wr clk lk 24:31 16:23 2:16 0:7 A D_in D_out en wr clk SSRAM 8:15 SSRAM 0:7
+V
Ready Clk
46
VHDL
Cache Memory y
For high-performance processors high performance
Memory access time is several clock cycles Performance b l P f bottleneck k
Cache memory y
Small fast memory attached to a processor Stores most frequently accessed items items, plus adjacent items Locality: those items are most likely to be L lit th it t lik l t b accessed again soon
VHDL
Cache Memory y
Memory contents divided into fixedfixed sized blocks (lines)
Cache copies whole lines from memory
When processor accesses an item

If it item i in cache: hit - f t access is i h fast
Occurs most of the time
If i item is not in cache: miss i i h i

Line containing item is copied from memory Slower, but less frequent Sl b tl f t May need to replace a line already in cache
VHDL
Fast Main Memory Access y

Optimize memory for line access by cache
Wide memory
Read a line in one access
Burst transfers
Send starting address, then read successive locations
Pipelining
Overlapping stages of memory access E.g., address transfer, memory operation, data transfer
Double data rate (DDR), Quad data rate (QDR)

Transfer on both rising and falling clock edges
49
VHDL
Summary y
Embedded computer
Processor, memory, I/O controllers, buses
Microprocessors, microcontrollers, Microprocessors microcontrollers and processor cores Soft-core processors f ASIC/FPGA S f for S C/ G Processor instruction sets
Binary encoding for instructions
Assembly language programs Memory interfacing


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Digital Design: An Embedded Systems Approach Using VHDL

Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

16-bit and 32-bit microcontrollers

Or O can be a soft core b ft

In ASIC, provided as an IP block

Digital Signal Processors g g

Often combined with a conventional core for processing other data

Digital Design Chapter 7 Processor Basics

Instruction set: the repertoire of available instructions

High-level languages: more abstract

Digital Design Chapter 7 Processor Basics

A processor executes a program by repeatedly

Program counter (PC) g ( )

Data and Endian-ness

16-bit, 32-bit, 64-bit words of data 6 bi 32 bi 6 bi d fd

least sig. byte g y most sig. byte

most sig byte sig. least sig. byte

Little endian Intel x86

n+1 n+2 n+3

Digital Design Chapter 7 Processor Basics

The Gumnut Core

Resources available on companions web site R il bl i b it

Digital Design Chapter 7 Processor Basics

Condition Code Registers

Carry Zero Program C P Counter

Data Memory (256 8-bit, 8-bit addresses)

Instruction Memory (4K 18-bit, 12-bit addresses)

Digital Design Chapter 7 Processor Basics

Condition d C diti codes

addc and subc include C bit in operation p

Evaluate 2x + 1; x in r3, result in r4

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Set Z if least-significant 4 bits of r2 are 0101 g

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Multiply r4 by 8, ignoring overflow Multiply r4 by 10, ignoring overflow

Digital Design Chapter 7 Processor Basics

Load register from memory

; increment msb ; with carry

Digital Design Chapter 7 Processor Basics

Input from I/O register

Branch instructions examine Z or C

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

Example: if r1 = 0, clear data location 100 to 0; otherwise clear location 200 to 0

Digital Design Chapter 7 Processor Basics

Call to increment locations 100 and 102

Return Address Stack

Gumnut core includes an 8-entry p y pushdown stack of return addresses

Digital Design Chapter 7 Processor Basics

Digital Design Chapter 7 Processor Basics

The Gumnut Assembler

Write a program as a text file

Digital Design Chapter 7 Processor Basics

Gumnut Instruction Encoding g