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Xilinx ISE Step-by-Step Tutorial using and Gate

This tutorial intends a step-by-step guide to simulate an AND Gate using ISE 10.1i It is understood that the tutorial is not generous enough in terms of picking a design as simple as, an and gate is singled out, nevertheless, it is just an illustration and the reader has to try his/her own design. It is left with you guys to try the designs of Half Adder Full Adder Multiplexer De-multiplexer Encoder Counter Go on-fold your vision and unleash your imagination.

Getting Started:

On a Windows platform, it is as easy as double clicking

and off you fly. Couldnt be easier,

just double click the ISE icon on the desktop. On, Linux, it is bit of a work-out so bear with it. On Linux platform, open the terminal by right click anywhere on the blank desktop area and choose terminal. Now you have to type some commands on the prompt to launch the ISE application. Lets first of all see how you are going to create your directory in btech. In terminal $ type as follows $ cd /home/btech/btech_proj0609 $ mkdir your_directory //replace your_directory by your NAME

Now you have made a directory with your name in /home/btech/btech_proj0609 This is where you are going to work and save all your work and projectsAny other place and your work will be deleted One more thing, you will find a file named nit.cshrc. DONT DELETE this.

Lets resume with ISE Close the terminal and Start with a fresh terminal Commands to run ISE in Linux are: $ cd /cad/xilinx10/ISE/ $ source settings64.sh $ export DISPLAY=:0 $ ise This will open ISE in gui as shown in the following fig and now onwards, the rest is the same for both Windows and Linux. Fig 1.

Close the Tips of the Day bit and carry on. 1. New Project with Project Wizard: You use project wizard through the Project Manager. File>New Project to open fig3 Fig2

Enter the project name, say for instance, and_gate2 in the Project Name field and browse the directory you created by your name in the Project Location field and hit next. You will be asked for the device properties. Here, select as shown in Fig4 and hit next.

Fig3

Next, hit new source to open a pop-up where you will click on verilog module to highlight it and then you can use the same file name here ie, and_gate2 and hit next (it could be different than the project name as it will be the name of the module, mostly it is different because bigger projects normally have sub modules). Fig4

You will be asked for input and outputs, enter them and hit next.

Fig5

Finally hit Finish tab.

You should see something like this..

Fig6

Now write the body of the design by altering already available information and/or altering some of them. Notice that the lines starting with // are comments and wont effect your design in actual. So you might like to change above to this: Fill the `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Create Date: // Module Name: 02:05:36 06/01/2009 and_gate2 // Design Name: gate level // Project Name: and_gate ////////////////////////////////////////////////////////////////////////////////// module and_gate2(input a,b,output c); and a1(c,a,b); endmodule

what are you waiting for? Save the project! Now note that when you select your design from the source pan (make sure implementation is current option) to highlight it, the processes pan will show extended processes that are available to you. Now you are all set to do variety of stuff and play around. Checking the Syntax: Now you would like to check whether what you coded actually is correct or not. Click the + of synthesize XST to see extended fields and hit check syntax. Processing it will take, leads you to either successful or unsuccessful message (Check the console at the bottom-every information is reflected here). Fig7

Mine is a success YAY! Not a big deal it was just a tiny design anyways and gate hah.

2. Simulate the design: This is what we have been up to, simulating the design. You will create a test bench using the Waveform Generator. Pull down the Project menu and select New Source. Select TestBench Waveform as source, and enter file name and_gate2_tb, Fig8. Fig8

Click Next twice, and Finish to enter the Initial Timing and Clock Wizard. Change the default parameters to those shown in Fig9.

Fig9

You are good to hit Finish now.

You will land this window. Clicking on any of the inputs, a or b around the shaded areas should toggle the waveform, set the waveform and SAVE (make sure the source pan has the Behavioral Simulation selected as the source. I have done it so Fig10

Having done so, you are ready for a taste of your, perhaps, first simulation in ISE so hold on tight. Make sure that behavioral Simulation is the current source in the Source pane, here select the .tbw

Finally, double click on the Simulate Behavioral Model from the processes pane to see something like this. Fig 11

We will try something else next time. For now, thats it and its your turn to try some other designs so take off.

-OJ