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Transaction Level Modeling of High Level DMA Controller

R. Divya Praneetha , Y. Padma Sai & Paleti Lakshmi Kanth AbstractAbstraction of the design is a powerful technique for the design and implementation of complex systems. It allows us to tackle complexity by first hiding unnecessary details and then working them out later. Hence, it is much essential to follow the design methodology that starts at a high-level of abstraction in the context of todays increasingly complex system level design. Transaction level modeling is considered to be this new abstraction level. Transaction level modeling is a high-level approach of modeling digital systems where details of communication among modules are separated from the details of the implementation of the functional units or of the communication architecture. Direct Memory Access (DMA) is a feature of modern computers and micro processors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. This paper discusses the modeling of DMA using TLM and compares the TLM modeling style of DMA with HDLs modeling. Keywords SystemC, TLM, DMA, Channel, Interfaces, Flow Control.

1. INTRODUCTION
The level of abstraction at which hardware is designed has increased significantly with the widespread adoption of Hardware Description Languages (HDLs) as the specification format, or the design entry point, which has led to an enormous increase in productivity over the earlier schematic entry based design methodology. The leap in productivity came about because HDLs such as VHDL and Verilog allowed designers to specify complex functionality at the behavioral and register transfer level (RTL) in a relatively succinct manner compared to the earlier structural-only view. However, after a decade of successful deployment, it appears that the current generation of HDLs is insufficiently equipped to handle the ever-increasing complexity hardware design and system level design. It is no longer productive for designers to model at the level of individual bits imposed by HDL; more sophisticated data abstraction capabilities are needed.

Further, hardware is no longer designed as an independent entity. Hardware modules frequently co-exist on the same chip with processor cores, embedded software, and other complex IP blocks, which forces designers to perform slow and inefficient co-simulations of hardware and software parts when attempting to simulate the entire system together. A cleaner mechanism for handling software and hardware components in the same environment is badly needed. In the context of todays increasingly complex level system design there is a need for design methodologies that start at higher levels of abstraction. Transaction level modeling can become this new abstraction level. The transaction-level model is built as a set of interfaces that define how models communicate. In its most primitive form the TLM basic interface provide with the fundamental communications and synchronization constructs that can be used to create TLM models. It is also necessary to provide a solution for verification and synthesis while keeping the modeling style easy. This trend is enabled and supported by SystemC [1, 2] . SystemC is a C++ class library and a methodology that we can use to effectively create a cycle-accurate model[1] of software algorithms, hardware architecture, and interfaces of System on a Chip (SoC) and system-level designs. The primary level of transactional modeling is to achieve dramatically increased simulation speeds, while still offering enough accuracy for the design task at hand [2] .

R. Divya Praneetha, Member Technical Staff, Kasura Technologies, Bangalore, Karnataka, India. Y. Padma Sai, Professor(ECE), VNR Vignana Jyothi Institute of Engineering and Technology, Bachupalli, Hyderabad, AP, India. Paleti Lakshmi Kanth, Assistant Professor(IT), Vignans LARA Institute of Technology and Science, Vadlamudi, Guntur, AP, India.

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Transaction Level Modeling (TLM) applies to a class of design problems where protocol based communication (i.e. designs with bus or network structures) is dominant [2]. The primary goal of TLM is to achieve dramatically increased simulation speeds, while still offering enough accuracy for a given task. TLM is proposed as a way to minimize the amount of events and information processed during simulation. Instead of driving the individual signals of a bus protocol, the goal is to exchange only what is really necessary (payload)[2]. TLM is also intended to reduce the amount of details that the designer must handle and therefore modeling becomes relatively easy. Transactional modeling is a high-level approach to model digital systems where details of the communication among modules are separated from the details of the communication among modules are separated from the details of the implementation of the functional units or of the communication architecture.

The DMAC enables the following transactions: memory-to-memory memory-to-peripheral peripheral-to-memory peripheral-to-peripheral The current DMAC model offers : Eight DMA channels. Each channel can support a unidirectional transfer. 16 DMA requests. The DMAC provides 16 peripheral DMA request lines. Single DMA and burst DMA request signals. Each peripheral connected to the DMAC can assert either a burst DMA request or a single DMA request. The DMA burst size can be set by programming the DMAC. Scatter or gather DMA support through the use of linked lists. Programmable DMA burst size. You can programme the DMA burst size to transfer data more efficiently. The burst size is usually set to half the size of the FIFO in the peripheral. Big-endian and little-endian support. The DMAC defaults to little-endian mode on reset. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and you can access them through the same master, or one area by each master.

2. DMA CONTROLLER
Direct memory access[5] is system that can control the memory system without using the CPU. On a specified stimulus, the module will move data from one memory location or region to another memory location or region. DMA is one of the faster types of synchronization mechanisms, generally providing significant improvement over interrupts, in terms of both latency and throughput. An I/O device often operates at a much slower speed than the core. DMA allows the I/O device to access the memory directly, without using the core. DMA can lead to a significant improvement in performance because data movement is one of the most common operations performed in processing applications. DMA transfer essentially copies a block of memory from I/O device to another. DMA can be used to offload expensive memory operations, such as large copies or scatter-gather operations, from CPU to a dedicated I/O device.

2.2. DESCRIPTION OF DMA CONTROLLER The DMAC that is currently been implemented contains 8 channels, so that it can handle more than one transaction request at a time. The channel registers corresponding to the free channel will be loaded with the transaction parameters like source address, destination address, number of bytes to be transferred. DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7 has the lowest priority. If the DMAC is transferring data for a lower priority channel, and then a higher priority channel goes active, it completes the number of transfers delegated to the master interface by the lower priority channel before switching over to transfer data for the higher priority channel.

Figure 1. Datapath of DMA

2.1. CURRENT DMA MODEL

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and then starts transaction. Up to 16 peripherals can be interfaced to the current DMA model. Interrupt Request The interrupt request[3] generates interrupts to the ARM processor either after the transfer is completed or if transaction is interrupted while transfer. Master interfaces The DMAC contains two masters. Figure 3 shows a block diagram of the two masters connected into a system. This enables, for example, the DMAC to transfer data directly from the memory connected to Master port 1 to any peripheral connected to Master port 2. It also enables transactions between the DMAC and any peripheral to occur independently of transactions on Master bus-1.

Figure 2 . 8-CHANNEL DMA

DMA Interface All transactions on the slave programming bus of the DMAC are 32 bits. This eliminates endian issues when programming the DMAC. Control Logic and Register Bank The register block stores data written, or to be read across the AMBA AHB interface. The DMAC is programmed with this block using DMA interface. All the registers regarding enabling DMAC, synchronization registers Interrupt requests registers, enabled channels register are programmed according to the signals coming from DMA Interface. Channel Logic and Channel Register Bank The channel logic and channel register bank[3] contains registers and logic that each DMA channel requires. The channel Register bank contains 8 sets of channel registers which stores source and destination addresses, linked link register if nonsequential access, control register and configuration register with each set for each channel. DMA Request and Response Interface Requests from the peripherals will be handled. If the peripheral is memory device then the DMA transfer may not wait for the request signal. If it is not so, then DMA waits for the request the devices

Figure 3. Dual Masters The two AHB masters are each capable of dealing with all types of AHB transactions, including: Split, retry, and error responses from slaves. If a peripheral performs a split or retry, the DMAC stalls and waits until the transaction can complete. Locked transfers for source and destination of each stream. Setting of protection bits for transfers on each stream.

Figure 4. TLM Modeling of DMA Controller

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3. MODES OF OPERATION
In the present DMAC model either mode can be the flow controller or Peripheral can be the flow controller. The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the DMAC, where the packet length is programmed by software before the DMA channel is enabled. If the packet length is unknown when the DMA channel is enabled, you can use either the source or destination peripherals as the flow controller. For higher performance peripherals, where the peripheral is the flow controller, use the DMAC flow control signals: DMACLBREQ, DMACLSREQ. Based on the type of transaction and the flow controller, there can be 8 transfer types[3] between the peripherals as shown in figure 4.

6.

7.

8. 9.

After completion of the transfer DMACEnbldChns field of that channel will be cleared. Processor can terminate the transfer be clearing the channel bit in DMACEnbldChns or using active H (halt) bit of DMACCxConfiguration. DMAC generates interrupt to the processor to indicate the completion of transfer. After completing the channel with the highest priority select the next channel with the highest priority for transfer.

Prerequisite for this algorithm 1. Processor has to first configure the DMAC by writing into channel register and enable the DMAC by writing DMACConfiguration. Algorithm assumes that Peripheral involved in the transfer will request the DMAC for transfer. Processor has to read the register of DMAC to know the status of the transfer when interrupt is generated.

2. 3.

Figure 5. Transfer Types

4. ALGORITHM TO MODEL DMAC

1. 2. 3. 4. 5. DMAC reads the channel register when E bit is enabled in DMACConfiguration. DMAC set DMACEnbldChns by reading channel register. DMAC selects the channel with the highest priority(lower number highest priority) . If it is memory to memory it begins the transfer DMAC will be flow controller. If peripheral is involved it waits for the peripheral request to begin the transfer Flow is controlled by DMAC or peripheral.

Figure 6. Flow Diagram of the operation of DMA Controller from the starting of transfer

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5. EXPERIMENTAL RESULTS
The current DMA model can perform 8 types of transfers between any two peripherals out of 16 peripherals interfaced to the bus at a time. The remaining channels are used to maintain a queue of the DMA requests from the peripherals with the highest priority requests entering the lower channels and lower priority requests like Memory Memory transfers occupying the higher channels. The simulation results for Memory - Peripheral are shown in the Figure 7 and Figure 8. RTL model needs much operation time for data transfer because it is descriptive of all in/out port of module for operation. TLM model is read/write or transmit/receive operations operating on data structures that is being exchanged between the functional units. The TLM model effectively creates an executable system model that simulates order of magnitude faster than RTL model[5].

In TLM models once the transaction starts, the payload of TLM model contains the number of bytes to be transferred at a time so that the kernel may not load the configuration parameters like source address and destination address many times if the transaction type is of burst transfers. Once the source address, destination address, number of bytes to be transferred in a burst and data length are loaded into TLM generic payload[2] the values are loaded from source to destination at once which can not be done in RTLs. The simulation speed is around 3 times faster if the transfers are of burst type as there will be no overhead of loading the addresses and values for each word transferred as in case of RTL.

6. CONCLUSION AND FUTURE SCOPE

With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally becoming insufficient to fit into this new role. SystemC, a C++ library, comes to the rescue. It facilitates a conceptualization of the coexistence of HW and SW designs together. Along with the TLM transport library, which permits interfacing between transaction-level models, SystemC speeds up the overall verification. Another important aspect is the enhanced portability across differently abstracted architectures. The same test setup can be seamlessly used with different abstraction levels of design. In this paper we have developed a TLM model for High Level DMA Controller and compared the simulation results with the RTL model. It is clear that the TLM models are faster compared to RTL models by orders of magnitude. The DMA can be extended to include more channels so that it can be effectively used in System on Chips connecting many peripherals. The number of channels that are implemented in DMA should be taken care of because if the number of channels are more then the lower priority channels may not be given chance for the DMA transfer and the transaction will be lost.

Figure 7. RTL Simulation trace for performance analysis

Figure 8.TLM Simuation Trace for performance analysis

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REFERENCES
1.) IEEE Standard SystemC Language Reference Manual 2.) OSCI TLM-2.0 USER MANUAL 3.) ARM PRIMECELL DMA CONTROLLER PL080 4.) Frank Ghenassia TRANSACTION LEVEL MODELING WITH SYSTEMCTLM Concepts and Applications for Embedded Systems Springer 2005 5.) Young-Jin Oh Implementation of DMAC using SystemC The 23rd International Technical conference on Circuits/Systems. 6.) Preeti Ranjan Panda Synopsys Inc. SystemC - A modeling platform supporting multiple design abstractions.

wish to serve IETE and ISTE students in building their professional carrier and faculty advisor for IETE and ISTE. Under her chairmanship the ISTE chapter of VNRVJIET, Won the Best Chapter Award-2009 for A.P. Section. Paleti Lakshmi Kanth is currently working as Assistant Professor in Department of Information Technology, Vignans LARA Institute of Technology and Science, Vadlamudi, Guntur. He obtained his Masters of Technology degree in Computer Science and Engineering from JNTU, Kakinada. His research interests include Embedded Systems, Data Mining, Network Security, Image Processing.

AUTHORS
R. Divya Praneetha is currently pursuing Masters of Technology in VLSI System Design from V.N.R. Vignana Jyothi Institute of Engineering and Technology and doing her intern in Kasura Technologies, Bangalore. She obtained her Bachelor degree in Electronics and Communications from JNTU, Kakinada. Her research interests include Chip Designing, Embedded Systems and System on Chip Architectures. Dr.Yarlagadda Padma Sai has received B.Tech (Electronic and Communication Engineering) from Nagarjuna University, M.E (Systems and Signal Processing) and Ph.D (ECE) from Osmania University. She started her career as Quality Control Engineer and served for 5 years at M/S.Suchitra Electronics Ltd., Hyderabad. She worked as a lecturer in ECE Department of Deccan College of Engineering and Tech, Hyderabad for one year and later joined VNRVJIET. She worked as a lecturer in the Department of ECE from July 1999 to 10th November 2000. She was promoted as Associate Professor and worked from 11th November 2000 to 20th August 2009. She is currently a Professor in the ECE department. She is a Fellow of IETE, a member of ISTE and ISOI. She has presented and published 15 research papers in National, International Journals and Conferences. Her areas of research interest are Bio-Medical Signal and Image Processing. She