ELEC6027: VLSI Design Project Part1: Microprocessor Research Topic: Test and Branch

Name: Niu Yunfei Team Name: A5 Course tutor: B Iain McNally Date: 16/02/2011

Contents

1. Instruction ........................................................................................................................................ 1 2. Branch with Condition Codes(8086) ............................................................................................... 1 2.1 Condition code flags ............................................................................................................ 1 2.2 Conditional branch instructions .......................................................................................... 2 3. Branch without Condition Codes(MIPS) ......................................................................................... 2 3.1 Compare/test and branch in MIPS ...................................................................................... 2 3.2 PC-relative addressing ......................................................................................................... 3 3.3 Branch delay slot ................................................................................................................. 3 4. Conclusion ....................................................................................................................................... 3 Appendix ............................................................................................................................................... 3 Reference .............................................................................................................................................. 4 Bibliography ......................................................................................................................................... 4

1. Instruction In a processors control flow, instructions are generally executed in sequence as stored in the memory. This flow can be changed by some ways [1]. Branch is one of these ways. If a branch is taken, the next instruction is that stored in the address specified by the branch instruction; otherwise, the program counter increments to point to instruction address in sequence [2]. In some reference, it is also called jump .However, there is no consistent terminology for control flow transfer [3].Branches facilitate to implement loops or if-else statements. Branches can be divided into two types [1][2][3]: 1) Unconditional branch: the branch is always taken under any conditions. 2) Conditional branch: whether a branch is taken depending on some conditions. The branch is only taken when the condition is met. In conditional branch, there are two common ways to specify the condition. One is with status flags and another kind branch is decided without status flags. This report will discuss both situations. 2. Branch with Condition Codes (8086) Most processors provide one or multiple status registers which store the condition code flags. These registers can be set 1 or 0 by some operations especially arithmetic operation such as add, compare and so on[3].Branch instructions test these registers whether is zero or nonzero to make branch decisions. 8086 is a CISC processor and use condition codes to branch. 2.1 Condition code flags Condition code flags are one or more bits that can be set by some operations and then be tested by some other instructions [3].8086 makes branch decisions according to one or more flags. Table I lists some of flags involved in branch operations of 8086 [4]. Table I condition code flags in 8086 Flag CF ZF SF/N VF Name Carry flag Zero flag Signed flag (also called negative flag in some other machines). Overflow flag Description Flag is set to 1 when a carry or borrow is generated by an operation. Flag is set to 1 when result of an mathematical or logical operation is zero. Flag is set to 1 when the ALU operation result is negative. Flag is set to 1 when operation produces a signed overflow. This is used in signed operations.

As shown above, flags are set according to arithmetic and logic (such as compare) operations. Compare/test operation do comparison and test by subtracting two operands and then set the flags but does not change the operand value while arithmetic operations can also change the value in the destination operand as well as flags. As shown in appendix, there are two addition operations to achieve a 64-bit addition in a 32-bit machine. Carry flag help to pass the carry result from the first addition to the second one.

2.2 Conditional branch instructions Conditional branch instructions test one or multiple flags and then execute branch operation. Table II lists parts of 8086 branch instructions copied from [5]. Table II Mnemonic JA JAE JB JBE JC JE JG JGE JO JS JZ JNG JCXZ . . conditional branch instructions in 8086 Meaning Jump if above Jump if above or equal Jump if below Jump if below or equal Jump if carry Jump if equal Jump if greater than Jump if greater than or equal Jump if overflow Jump if sign Jump if Zero Jump if not greater than CX register is Zero . . Flags condition CF=0 and ZF=0 CF=0 CF=1 CF=1 or ZF=1 CF=1 ZF=1 ZF=0 and SF=OF SF=OF OF=1 SF=1 ZF=1 ((SF XOR OF) or ZF)=1 (CF or ZF)=0 . .

To do branch if Rx less than or equal Ry: CMP Rx, Ry // compare the value of Rx and Ry ,set flags SF,OF and ZF JNG label // test if SF xor OF=1 or ZF=1,if true, branch to label After this set of operations, flags OF,ZF and SF are affected. 3. Branch without Condition Codes (MIPS) Some processors make branch decision by using a tree-address instruction to compare whether two registers are equal or not equal. The branch-target address is specified by the third register (or an immediate). MIPS is a RISC processor which does not have condition code flags. 3.1 Compare /test and branch in MIPS MIPS has 3-address compare instructions slt to compare two general registers .The destination address is set to 1 if the first register is less than the second ,otherwise the value is 0 .There is a R0 register in MIPS which always return value 0.This design facilitates compare operation as most comparisons are done with zero. There are also two branch instructions bne and beq to test whether two registers are equal or not .If condition is met, processor counter points to branch target address specified by the same branch instruction. Bne is branch if not equal while beq is branch if equal[7] .

Branch based on other kind conditions can be achieved by combining the compare and branch instructions. For example, to branch if Rx is less than or equal Ry: slt Rz, Rx, Ry // if Rx<Ry ,Rz is set to 1 or it is 0.

bne Rz,R0, label // test whether Rz is not 0, if true, it indicates Rx less than Ry, branch to label beq Rx,Ry ,label // branch to label if Rx equals Ry 3.2 PC-relative addressing It can branch to both higher address and lower address. Conditional branch instructions in MIPS use PC-relative addressing. It jumps relative to the PC. Branch instructions provide a 16-bit immediate value as an offset which can be added to the current address to get the destination address [3]. 3.3 Branch delay slot For pipeline benefits, there is one instruction (delay slot instruction) between branch instructions and the execution of branch. This one instructions delay is called branch delay slot. That is to say MIPS executes branch instruction, delay slot instruction, branch in sequence [8]. 4. Conclusion As discussion above, branch with flags makes the control program easier while without flags can make the datapath simpler. As some arithmetic operation can also use flags (such as addition with carry) , we prefer add flag registers in ALU. A RISC-like machine can reduce the opercodes but may need more instructions to implement one operation than a CISC machine do. We should balance this when our design. We can use PC-relative addressing mode to expand the addressing range. Branch delay is not useful in this non-pipeline design. (the main body of the report has 791 words ) Appendix Do a 64-bit addition in a 32 bit machine-using with carry in 8086 Assume two 64-bit operands are stored in the memory as: operand1=(2043h)(2042h)(2041h)(2040h) and operand2 =(1043h) (1042h) (1041h) (1040h). MOV DX, [2040]; // load data in address [2041] and [2040] to DX, it is the lower word of operand1 MOV BX, [1040]; // load data in address [1041] and [1040] to BX, it is the lower word of operand1 CLC ; // clear the carry flags ADD DX, BX ; // (DX) = (DX)+(BX), CF will be set 1 if carry is generated MOV BX, [2042];// load data in address[2042]and [2043] to BX, it is the higher word of operand1 MOV CX, [1042]; //load data in address[1043]and [1042] to CX, it is the higher word of operand2

ADC CX, BX; // add with carry,(CX)=(CX)+(BX) + (CF), CF will be set to 1 if carry is generated Now the higher word result of two 64-bit operands addition has been stored in CX and lower word is stored in DX. As seen above, there are two addition operations to achieve a 64-bit addition. The two additions are linked by passing carry result from the first addition to the second one. Reference [1] Patterson D A and Hennessy J L, Computer Architecture: A Quantitative Approach, 2nd Edition Morgan Kaufman 1996, pp B35-B45. [2] Wikipedia (2011), Branch (computer science) [online].Available from: http://en.wikipedia.org/wiki/Branch_(computer_science) [Accessed 8th Feb 2011] [3]William Stallings, Computer Organizations And Architecture Design For Performance,8th Edition, Prentice Hall 2010,pp 369-373. [4]Wikipedia (2011), Status Register [online]. Available from: http://en.wikipedia.org/wiki/Status_register [Accessed on 8th Feb 2011] [5] Sanyasi A.[2007],8086 Instructions Set [online] Scribe. Available from: http://www.scribd.com/doc/26677897/8086-Instruction-set-ppt [Accessed 11th Feb 2011] [6] Dandawate Y.H., Intel 8086 manual,2006 . [7] Patterson D A and Hennessy J L, Computer Organization and Design, Morgan Kaufmann 2009, pp105-109. [8] Wikipedia, branch delay slot [online].Available from: http://www.m5sim.org/wiki/index.php/Branch_delay_slots [Accessed 11th Feb 2011]

Bibliography [1] McNally B I, Full Custom Design Exercise, http://users.ecs.soton.ac.uk/bim/notes/fcde, last viewed on 23/1/2011 [2] Gajski D D , Principles of Digital Design, Prentice Hall 1997, pp388-433