Chapter 1 Abnormalities in CSC based HVDC

1.1 Eect of Sudden Inverter AC Source Isolation

In this paper the eect of sudden isolation of Inverter side AC volage for a Back to Back HVDC System is discussed. All the analysis and strategy to overcome this problem is applied to McNeil HVDC link. But this method can be applied to all types of HVDC systems. It does not mean that isolation of AC source doesnt mean that collapse of inverter operation. Eects are i. Due residual voltage in lters, reactive elements on Inverter AC side, inverter commutation process continues and generates of its own an AC voltage source. So real power exchange takes place from rectier to inverter. And these power directly goes to reactive elements present in the inverter so inverter AC bus voltage increases causes surge arrester to break down. Now surge arrester has to absorbe all full load power of HVDC link which is beyond of its rating. ii. Frequency of the inverter AC Bus voltage is solely depends on the interaction between Ac system components and the transformer saturating reactor. So this frequency is significantly higher than the normal fundamental frequency. The local load e.g colling pumps, connected to inverter bus are adversely eected due to this high ferquency. So isolation must be detected and protective actions should be taken as fast as possible to avoid the above abnormal consequences.

1.1.1

Detection of Islanding Condition

By knowing the status of AC circuit breaker whose operation causes isolation, detection can be possible. Bue as CB may be situated very away from the inverter station so we need a very high speed communication link. SO it is not possible. Simmilarly it cannt be possible to detect islanding by seeing the surge arresster conuction.As some ofthe arrestes may be located outside and also as we need to know the conduction status of all the arrtsrs present in the system. Measurement of power ow coming out from the inverter bus is not sucient to detect fault as if the isolation CB is very far away from the inverter bus, it draws a signicant amount of reactive currents from the inverter. So by measuring only active current , it can be possible but during fault, the fault current is also highly reactive so it cant dierenciate whether the normal fault of isolation condition. As simulator shows 1

that there is signicant dierence in ferquency of inverter bus during isolation and during normal condition, so it can be uses to detect isolation but this frequency is depends on somany paprameters like active power, system components etc, it is not possible to set a particular frequency or range of frequency for detection of islanding detection. But this detection may operate for long duration ( 200ms) mazor faults. But detection based over voltage on the inverter AC Bus can be used to dierenciate between normal operation and islanding operation. Normally over voltages are limited within two cycles by converter control during normal operation. So by setting detection level to a lower level of surge arrester voltage rating for duration of over two cycle but less than the maximum permitted operating time, a reliable detection of islanding can be possible.

1.1.2

Converter Isolation Protecton Method

Suddenly we cannt block the DC link as it causes over voltage in rectier side for weak system unless the lter ckt and compesation ckt switched o. If this happend the immediate normal power restoration on reclosure of the isolating CB is not posssible. But blocking of inverter or bypassing of inverter during islanding leaves the energy trapped in lters and capacitors. As the resistance is very small, to decay the trapped energy which is exchanged between lters and transformer takes long time. Also it is dicult to dierenciate between the voltage due to reclosure osolating breaker and due to lter energy decay within a resonable time. So on detection of islanding, inverter becomes diode rectier and feed energy back to the rectier. This is called as Enhanced rectier mode (ERM). So graduaaly inverter voltage decayes and aer 20ms after invoking ERM mode, the inverter reverts to bypass pair ring. Upon detection of closure of isolating circuit breaker, the system is restarted.

Figure 1.1: Series resonance scheme

Figure 1.2: Series resonance scheme

1.2

Eect of dierent voltage control devices (SVC,SC,FC) in the dynamic performance of HVDC Link

In [16], the eect of dierent voltage control devices on the transient over voltage of inverter bus is discussed. Diernt voltage control devices used in this work are given below i. Fixed capacitors(FC) ii. Synchronous Compensator(SC) iii. Thyrister controlled reactor (TCR) iv. Thyrister switched capacitor (TSC) v. Metal Oxcide Vaqrister (MOV) vi. Series Capacitor Device (SCD)

Figure 1.3: Series resonance scheme

Figure 1.4: Series resonance scheme They have used a HVDC system having inverter of low SCR value. A dynamic over voltgae(DOV) crieteria(for safe operation of loads conneted at this bus) is used to compare the eect of these compensating devices. Series capacitor device (SCD) is considered as a new proposal for DOV control. They have considered a very slow exciter in SC to control reactive power. Dierent abnormal conditions considered are like DC link block, three phase fault at inverter and all possible type of faults. But they found that at DC Block condition produces higher DOV as compared to other faults. So they considered 3

only DC link block faults for comparision. The conclusions made for dierent VCDs are given below: i. Except FC, all the compensators are able to reduce DOV and able to follow DOV crieteria. ii. SCD is highly eective as compared to other devices for DOV control. iii. The TCR is little faster in comparision with SC for DOV control iv. Due to presence of slow rotor oscillation in SC, reactive power compensation is effected. v. They have also shown than recovery from fault is resonable with all VCDs. A very simillar type of work is discussed in [17]. They have not considered SCD and MOV but combined TSC and TCR called SVC for analysis. They have used a dierent DOV crieteria as shown in g. 12. and used response time as shown in g. 12 DC link block case for comparison among dierent VCDs. They used very fast thyristerrise exciter for SC and argued that the speed of action of both SC and SVC are comparable. As SC is ecient in decreasing the rst peak over voltage following DC block but have little higher response time in comparision with SVC but SVC have higher voltage peak following fault.So they combined both the devices. So they got a good response time as well as less rst peak of DOV. Comparision values for dierent VCDs are given below. Type Response Time First Peak of DOV SC 470ms 1.3pu SVC 173ms 1.7pu SVC + SC 173ms 1.5pu

Figure 1.5: Series resonance scheme

Figure 1.6: Series resonance scheme They have also tested the recovery from dierent faults with dierent VCDs. As the inverter AC system is very weak system, so they have modied the the control system at inverter to avoid continious commutation. The modications are given below. 4

i. Introduction of 20ms lag in the measurement of the current error signal to gamma regulator to avoid the ripple in dc causing ring angle delay which subsequently causes long recovery. ii. During fault, both converters ring angle retard to 135 degree and kept for 200ms after which it is gradually rambed down to start normal operation. iii. For fast recovery from continious commutation failure, a ring angle reduction and ramping ckt at the inverter is used as shown in Fig. 21. The recovery time for with dierent VCDs for three phase to ground and single phase to ground fault are shown in Table 1 and Table 2 respectively. Three phase fault FC SC SVC SVC+SC 235ms 135ms 485ms 135ms Single phase fault FC SC SVC SVC+SC 335ms 135ms 585ms 135ms AS AC system at inverter is very weak, SO during recovery in case of SVC, TSC gradually switches capacitor banks which causes a further decrease in SCR and subsequently causes a control system instability for TCR to control ring angle alpha. As aresult continious commutation failure occures. To avoid this, modied gammacontroller shown in FIg. 10 is used.SO the recovery with only SVC takes more time.They also argued that this problem can be solved by decreasing the TCR gain but then it can not control the dynamic DOV for which it is used. Its opearation is more severe for single phase fault. AS by use of SC increaes SCR of the system, so there is no problem of commutation failure as a result fastest recovery possible. They also considered DC line fault and corresponding recovery and found that there is no signicant eect on fault recovery by these dierent VCDs. So thay nally concluded that SVC + SC combination is the better option for HVDC system having lower SCR for TOV reduction and fastest recovery.

1.3

AC-DC Interaction

When same tower is used to carry both AC and DC line in AC-DC parallel system, the electromagnetic interaction between the line has been reported in [17]. In steady state as dc has zero induction on AC line but there is 50 hz component of current is induced on DC line for AC line operated at 50 Hz. This 60Hz current in DC line produces 120 Hz and DC current in the secondary of converter transformer. If dc current has a signicant value, then it causes saturation in transformer and causing harmonic instability by injecting harmonics to both AC and DC side. In [17], they used blocking lter(BF) in positive and negative poles at the neutral end of rectier to limit the 60 Hz component. At dierent condition i.e with and without transposition of AC line, with and without of BF the magnitude of 60 HZ component in DC side and the corresponding dc component and 120 Hz component in the in the AC side of converter transformer are shown. By using BF and transposition of AC line these magnitudes are considerably decreased. It is also shown that the induced over voltage on 5

both AC and DC line at dierent faults. These overvoltage are higher in case of weak AC system for all faults except conductor DC fault where it is higher for stronger system due to large fault current causing large induced voltage. Overvoltage generated during abnormal conditions in dc line is higher in AC-DC line as compared to DC line alone. Generally the voltage accross the BF is very small as 60 HZ induced current is also small. But during single phase fault or dc-AC line contact faults, a 60 HZ undamped oscillation starts in BF which causes a very high voltage accross BF. So for safe operation of converter thyrister valve, ZNO surge arrester along with a pattallal resistor (damping improvement) is used accross BF as shown in g. 12.

Figure 1.7: Series resonance scheme

Figure 1.8: Series resonance scheme

1.3.1

Zero sequence currents in AC line due to transients in adjacent dc line

The HVDC and AC system considered for analysis [17] are shown in g-9. Here two parallel AC line and two parallel HVDC link (Name of Link). The gap between the AC and DC line is 183m.It is shown in this article that due to the change of groungd current of HVDC system during deparallel operation of HVDC system. The earth current of HVDC system and also the neutral current of GIA AC circuit is shown in g. 13. It was recorded during deparrallel operation test in the real sytem. Earth fault relay of GIA trips as the GIA neutral current has a negative peak of 20 % of dc peak can be seen from gure 12. TO nd the exact explanation for the above fact, a simpilied circuit as shown in g.12 is used to analyse the above problem. In the gure the current source represent the HVDC link and below the link is the AC link with zero sequence impedance. In g 20, the amplitude of current in AC link (I2) due to current (I1=1A) in HVDC link at various frequencies and at zero ground resistance are shown It can be seen from thge gure that there is a minor induction for frequencies below 100Hz. But the frequency scanning of g 10 shows that it contains frequencies between 0-30Hz. So it contradicts the simulation result. Then they have considered dierent earth resistance value like 10m, 100mand1000m. The respose curve with 10 m resistivity is shown in g. 21. It can be seen that there is a signicant current induction for frequencies below 30 Hz and there is no signicant dierence of these frequencies magnitudes for other resitivities. By using earth resistance and transformer neutral resistance in simulation, they have created a replica that canseen in eld as shown in g.12. Thay have also shown that there is no eect of change in induced current at low frequency due to ground wire above ac line i.e no cancellation for low frequency eld.

Figure 1.9: Series resonance scheme

Figure 1.10: Series resonance scheme

Figure 1.11: Series resonance scheme

Figure 1.12: Series resonance scheme

Figure 1.13: Series resonance scheme

Figure 1.14: Series resonance scheme

Figure 1.15: Series resonance scheme

They have given an intuitive explanation for, why it is so for some resitivity of ground but not so for ideal ground system. From the image made in g. 21 it can be seen that for perfect ground sytem, the the electromagnetic ux link to the conductor b due to conductor a is very small as compared to the second case where the linkage is maximum. This is due to the depth of penetration of current into ground. So there is no signcant voltage induced in zero resistance of earth. The depthof penetration of current into ground inversely proportional to frequency. So at low ferquency causes high penetration as a result the mutual induction between a and b is more at low frequency. They have also shown that even a gap distance of 1Km between HVDC and AC line, there is a signicant voltage induction in AC line due to transient in DC line. From g. 9 it can be seen that thhere is also a signicant induction at 60 Hz also. Thay have argued that why in normal AC system which has two parallel line operating at 60 Hz, no zero sequence current induced. This is due to the cancellation of ux one by another. In g. 15 it can be seen that a fault in the middle X, there is three loops but the voltage induced in loop 3 is almost zero as the induced voltages by loop1 and loop 2 gets cancelled each other. If there is a fault at Y, then the current in loop 1 which mainly induces voltages in line 3 is is very small so there is a very less induction. They also given a solution to AC system to avoid the trip by utilizing lter to ground in the transformer neutral.

1.3.2

ring angle modulation for cancellation of dc current in converter transformer

In this paper the dc current produced by 60Hz current induced in DC link in hybrid HVDC system is eleminated by ring angle modulation at both rectier and inverter. If Ia0 , Ib0 and Ic0 are the dc components in the three phases of converter transformer secondary and Ipk is the peak of induced 60Hz component in dc link, then Eq.1 is satised for an ideal case having equidistance ring angle of 60 degree. 9 Ipk 2 2 2 Ia0 + Ib0 + Ic0 = ( )2 (1.1) 2 First they have proved mathmatically is it possible to eleminate dc component by ring angle modulation. The pro as given below. If m/sin(wt + ) is the modulating signal, the ring angle after modulation will be = 0 + m sin(t + ) As 3 Vd = Vd0 cos ( Xc Id ) (1.3) Vt [cos cos( + )] (1.4) Id = 2Xc Putting Eq.1 and Eq.3 in Eq.2 and separating dc component and frequency component, we get, 3Vt m Vd60 = [sin 0 sin(0 + )] sin(t + ) (1.5) 2 10 (1.2)

Where Vd =Dc terminal voltage at rectier Vd60 = The voltage component with rectier DC voltage due angle modulation i.e Vdnew = Vd60 + Vd Xc = Commutating reactance Vt = RMS value of converter terminal voltage Id =Dc current and = frequency in radian per second and phase with respect to the positive zero crossing of converter terminal voltage respectively

Figure 1.16: Series resonance scheme

Figure 1.17: Series resonance scheme

Figure 1.18: Series resonance scheme

11

Figure 1.19: Series resonance scheme

Figure 1.20: Series resonance scheme From Eq. 2 if we change frequency and phase angle of modulating signal then V( d60) can be made exactly opposite in phase with with the 60Hz voltage induced over dc line. So there is no 60Hz current in dc link as a result no dc current in converter transformer. They applied above concept to a simple test system as shown in g. 12. The inverter side represented by a single dc voltage source and 60Hz voltage induced in dc line due to AC line is represented as a 60 hz voltage source. But they found that there is no 60Hz current in dc link but dc cu8rrents in the converter transformer i.e Ia0,Ib0 and Ic0 increases signicantly. This is shown in g.12. This is a contradict to the Eq.1. and also to the concept that if f is the frequency of a component in dc current, then its reection in AC throgh converter will be f++f0, where f0 is the nominal frequency. As this true only in ideal condition where equidistance ring is assumed but in this case due to ring angle modulation, ring scheme is no more equidistance. This is clear from the g. 21 where the width of positive and negative pulses are not equal. SO they have used a second strategy where they have tried to nd the quenching

12

angle 0 to 5 as shown in g. 4 by minimising the objective as given in Eq. 12.

2 2 2 Ia0 + Ib0 + Ic0 = 0

(1.6)

So they applied this calculated quenching angles and found that dc current fully vanishes at ac side. But they also told that the iterative solution based method is dicult to implement in real system. But fortunately the calculated quenching angles are following a sinusoidal curve for ring angle 30 degere as shown in g 12. So it seems simillar to nd a modulating signl in Eq.1. But authors mentioned that it is dicult to nd its amplitude and phase also its frequency. But this thing can be obtained by a closed control loop. The concept behind the control is decrease the width of positive puse and increase negative pulse width of a AC side line current if it carries positive dc current and vice versa. The conrol loop is shown in g. 14. They have applied toa HVDC system and found that it works properly. But one major draw back they encounetrd is that the production of uncharacteristics harmonics increases as shown in g 13 due to nonequidistance ring.They also argued that if 60Hz voltage induced in dc line can be reduced by transposition of AC line then this method can be applied as compensation is less as resul;t unchracteristic harmonic production will be less. They also found the I60 component is not reduced to zero by use of above control but dc current vanishes. So it needed to apply this control at both inverter and rectier side.

1.4

Commutation Failure

COmmutation failure means the incoming thyrister fails to conduct and the out going thyristr continues to conduct.

1.4.1

Commutation Failure Analysis

In this paper, the mathematical derivation of the change in voltage magnitude at the converter bus causes commutation failure is derieved for both single phase and three phase symmetrical fault. The inverter is connected to an symmetrical harmonic free AC source through converter transformer. The mathmatical derivation as given below.

For Symmetrical 3- condition Volt time area A in a commutating voltage wave required for commutation and process of commutation is shown in Fig. 1. If a constant dc current is assumed then area A will be directly proportional to dc link current Id . As,
+

A=

E sin t d(t) 2

So, A= 2E [cos + cos ] 2 13 (1.7)

If there is a symmetrical voltage reduction to E as shown in g 1, assuming constant current, no change in ring angle during this period, as volt-time area remain constant so the extinction angle gets reduced to as shown in g.1. As the new volt-time area and old volt-time area are equal.So, 2E 2E [cos + cos ] = [cos + cos ] 2 2 So, E cos + cos = E cos + cos The dc link current before disturbance will be E [cos + cos ] 2Xc If disturbance taken into account then dc link current will be, Id = (1.9) (1.8)

E Id = [cos + cos ] (1.10) 2Xc If 0 is the critical extinction angle below which commutation failure may occure, the dc link current for this critical extinction angle will be E [cos + cos 0 ] Id = 2Xc So by deviding Eq.1 by Eq.2, we get Id cos + cos 0 = Id cos + cos By putting the value of from Eq.5 in Eq.3, we get E I cos + cos = ( d) E Id cos + cos 0 (1.13) (1.11)

(1.12)

L If Xcpu = 2IdFL Xc represent p.u commutation reactance, then putting the value of cos EF from Eq.2, Eq.3 becomes

I Id Xcpu E = d E Id Id Xcpu + IdF L (cos 0 cos ) Then p.u change in voltage V = V = 1

EE E

(1.14)

will be (1.15)

Id (Id /IdF L ) Xcpu Id (Id /IdF L ) Xcpu + cos 0 cos

Generallt Id IdF L so Eq.10 becomes V = 1 Xcpu Id Id Xcpu + cos 0 cos (1.16)

14

Eq.7 gives the maximum terminal voltage redution for which commutation failure does not occures. Here only a 3- symmetrical fault without any harmonic disturtion and no phase angle shift is considered.

Unsymmetrical 3 Condition In this case, voltage magnitude reduction is applied to only one phase and corresponing p.u change in voltage does not cause commutation failure is evaluated. As shown in Fig.12, due to single phase voltage reduction, it aects two line voltages as a result there is a phase shift() in the zero crossing. For some value For some valves this phase shift is positive and others have a negative value. Due to this phase shift, the valves having negative value, extiction angle reduced and positive value extiction angle increases.In g. 12 represent the decrease in tne extinction angle due to single phase disturbance. So, it is necessary to consider phase shift () which is also a function of voltgae reduction,in calculating of V . So, Eq. 12 becomes, V = 1 Id Xcpu Id Xcpu + cos(0 + ) cos (1.17)

They also argued about the consideartion of only phase shift () not the voltage reduction eect which only two line voltages. As during commutation, the commutation voltage which is the substraction og two phase voltages, one of them is nearer to zero value and other one has a nite value. So it is not a matter whether there is a single phase of three phase voltage reduction occures. They have tested this with simulation and the error is less. They also derived the relationship between single phase voltage reduction(V ) and phase shift ().The relation is given Eq.13. 3/2 0 (1.18) = 30 arctan[ ] (1/2) + (1/(1 V ) SO Eq.9 and Eq.10 are to be solved iteratively to nd the the p.u voltage reduction for commutation failure. Some of the results given in the paper as given below. Fig. 10 for three phase fault and FIg. 11 for single phase fault.

Parameter Bahaviour of Commutation Failure For symmetrical fault Fig.1 shows the parameter behaviour upon commutation failure calculated from the above derived formulle. As it is expected for higher comutation margin angle, the p.u voltage reduction causes commutation failure is more. It also shows the efect of commutating reactance on commutation failure. It can be easily predicted how much commutation margin angle to be increased not to cause commuattion failure if there is a abnormality. So there is no trial and error method is needed to increase commutation margin to avoid succesive commutation failures. They also show that by reducing commutating reactance, commutation failure can be avoided.

15

Figure 1.21: Series resonance scheme For Unsymmetrical fault As shown in Fig.4, when single phase voltage reduction takes place, the two line voltages are aected in a Y-Y transformer and only one line voltage will be aeted in star-delta transformer. Also the phase shift angle () is very less in star-delta case as compared to star-star case.So, there is a voltage reduction due single phase fault, the star side converter bridge is more prone to commutation faillure as compared to delta side bridge.Fig.5 shows the eect of dierent parameter in the onset of commuattion failure in single phase fault. From the gure it can be seen that single phase is more prone to commutation failure as compared to three phase due to phase shift (). These are shown from the above derived formulle. They also tested the above said result in a HVDC simualtion with three phase fault and single phase fault. But the calculation almost matched with three phase case but there is a signicant dierence in single phase case. This is due to the harmonic distertions. They also calculated the probability of getting commutation faillure at dierent voltage reduction values. These are shown in Fig.8 and FIg.9 . This is done by applying same type of fault for 100 times with time gap of 0.2 millisecond time on wave distribution over one cycle(20ms at 50Hz). In [15] and [16], the authors have shown, the decrease in voltage (V )causes commutation failue as discussed before is not accurate. They have used a HVDC system and created a three phase fault at the inverter side so that the voltage reduction is 13.5 % and corresponding current rise is 12 % but no commutation failure is observed. According to Eq.13, the voltage reduction greater that 5.8 percent causes commutation failure. As steady state conditions are used, transient phase shift and ring angle dynamic are not considered, so this error arises. They have dened another index called immunity index as given Eq. 12 for analysis 16

Figure 1.22: Series resonance scheme

Figure 1.23: Series resonance scheme of CF.

Criticalf ailurelevel (1.19) Rateddcpower Where critical fault level is the fault level where the CF just starts. And system having high Immunity Index value, less susceptible to CF and vice versa. They have found the immunity index for dierent type of faults i.e resistive fault, inductive fault and capacitive fault (switching on an un discharged capacitor or lter) The corresponding indexes are shown in Fig.13 for three phase faults. It can be seen from the gure that for capacitive faults which has higher Immunity index but depends on the point on the wave where faault created where as inductive fault has less Immunity Index. Simmilarily they have shown this for single phase faults in Fig.11. For single phase faults, the indices for the above three faults are highly dependant upon the time when the fault occures. It can also observed that, on certain period on the wave, capacitive faults are even very small Index. So from indeces it was conformed that the inductive fault is the most severe fault causing CF. They also anlysed CF for multi-Infeed HVDC system. They have developed certain new terms as given below and multi-infeed sytem used for analysis is shown in Fig.7. ImmunityIndex = Commutation Failure Immunity Index (CFII) CF II =
2 Vac worstCriticalf aultM V A = RatedDclinkP ower wLmin Pdc

(1.20)

17

Figure 1.24: Series resonance scheme

Figure 1.25: Series resonance scheme As the inductive fault is the most severe fault so for worst critical MVA is calculated from inductive fault, this signies Lmin . Multi Infeed Interaction Factor (MIIF) M IIF2,1 = percentageV2 onepercentagevoltagechangeatV 1 (1.21)

M IIF2,1 is the MIIF from converter 1 to converter 2. If there is a one percentage change in Converter 1, the corresponding change in volgae at converter 2 is used to nd M IIF2,1 . Both the Eq.11 and Eq.12 is used to analyse CF in ths sytem. For a single infeed system, the eect of dc reactor on CFII is shown in FIg.12. It can be seen that for low inductance and higher inductance values, the CFII is less i.e more prone to CF. They also dened two other term Local CFII and Concurrent CFII. Concurrent CF II2,1 is evaluated as in Eq.4, but the cases which causes CF at both the inverters is to be cosidered. For Local CF II2,1 , the cases which causes only commutation failure at its local converter is to be considered. They have considered three dierent cases as given below to nd the probability of CF of converter 2as increase in fault levels at BUS 1to study multi-infeed system interaction. These cases outputs are shown in FIg. 1-4 respectively. Case 1: Converter 1 is blocked and fault at Bus 1 case 2: Fault is created at Bus 1 when both the converters are working at full load and by seeing the CF at converter 1, converter 1 is blocked.

18

Figure 1.26: Series resonance scheme

Figure 1.27: Series resonance scheme Case 3: Same as Case 2 , no control action of blocking is taken for Converter 1. In case 1, fault greater than 35MVA, CF starts but in Case 2, fault greater than 25MVA, CF starts. This indicates that operation of HVDC converter increases the susceptibility of CF of Case2. But certain abnormalities are observed foe Case 3. When fault level greater than 20MVA, CF starts as expected But for for lower MVA from 5-15MVA, a very high probability of CF is observed and for 15-20mva NO cf IS observed. This is due to the high low order harmonics distortions presence in the medium fault level causes advancing commutating voltage zero crossing as shown in Fig.13 as a result commutation margin increased so CF is not observed. Where a shigh level faults, causes a sucient voltage drop subsequently causes CF. They also proved by measuring harmonic distortion levels for dierent fault levels which is shown in in Fig.9. They also found out certain co-relation between MIIF and fault level as shown in Fig.10. So for MIIF0.6 any fault at converter 1 causes local CF , causes CF at converter 2. But MIIF0.06, a very high level faults at converter faults at converter 1 causes CF at Converter 2. So MIIF0.15 can be treated as there is no interation between inverter Buses.

1.4.2

Commutation faulure prevension

In [17], a constant extintion angle control (CEA) is discussed. Here autor used the commutating voltage and intigrating it from + c to t where c is the commutation margin w.r.t positive going zero of respective commutasting voltage, when this integral value matches with 2LId , then ring p[ulse is issued at that instat for this converter valve. This means it satisfy converter equation given Eq.2. It uses individual commutating voltages and integrate it and issues ring signal to that converter and then it resets the intigrator and waits for next cycle for ring of that valve. They also used this scheme for ring rectier by adding a extra voltage vcc with

19

Figure 1.28: Series resonance scheme

Figure 1.29: Series resonance scheme 2LId for coparison of intigrator value. This is used when same station can be used for rectier and inverter. They also proposed a method to nd the transient change in voltage during intigration of commutating voltage and corresponding increase in by a xed aamount to avoid commutation failure. 2E cos t 2E cos c + 2LId = 0 (1.22)

In [18], authors used prediction of commutation are to re inverters. So that CEA is maintaied. As shown in g.10, at t=t1 , valve 2 red, at t=t3 , valve 3 has to be red. SO the ring angle for valve 3 can be calculated as given below. The prdicted area as given in E.1 is to be evaluated at every time step after valve 2 is red with trangular approximation as given Eq 10. Ukn (t) t kId (1.23) 2 The rst of the above equation is the triangular approximation of commutation volt-time area. The second part i.e kId is the overlapping area of the converter as shown in g. 12. When Am(t) becomes equal with some reference value Amref , the ring to valve 3 is issued at this instant. The rerence area Amref is the area equal to margin area as shown in g.12. But due to some transient or abnormalities in system, the prediction area may not be accurate So a correction to this ia also proposed as given below. Am (t) = (Ampred )k = Amref + (A)k1 (1.24)

Where (Ampred )k is the prediction at k th period and (A)k1 is the error in k 1t h period as given below. (A)k1 = (Amactual )k1 (Ampred )k1 20

Figure 1.30: Series resonance scheme

Figure 1.31: Series resonance scheme So in this way angle of advance can be increased to maintain CEA. In [18], closed loop extinction angle controller is discused. The corresponding block diagram is shown in g.13. Here gamma measuring circuit measures the minimum gamma value of previous actual gamma values of ve valves for a six-pulse converter. Distribing magnitude is used to increase ref during abnormal conditions to avoid commuattion failure. In [17], a closed loop extiction angle controller with asymmetrical controller is used as shown in g.12. In this asymmetrical controller, when extiction angle (EA) is smaller than the reference value, the loop gain is high so control is fast. When EA is higher than the reference value, control gain is small so control is slow. This is used during power recovery to reduce the speed of action of ring controller to avoid continious commuattion failure. And during disturbances, increases the speed of controller so rise in commutation failure can be decreased. In [18], author has discussed a hybrid margin angle control method for inverter. As open loop always fast as compred to closed loop, where as certain problems in open loop contol like un symmetrical conditions, so here the author mixed two controllers. The control block diagram is shown in g.13. It consists of two controllers , one is open loop gamma controler ans second one is closed loop gamma controller. Open loop gamma controller nds from two non linear characteristic as shown in the block diagram. Here a delay time block of time constant T5 is used to gradually decreases decrease during fault recovery to avoid continious commutation failure. Simillarlity delay time block of time constant T4 in closed lop gamma controller is used to gradually decrease to avoid commutation failure during fault recovery. -Advance value is an external signal given by user during any abnormal conditions i.e after commutatiopn failure occures, has to be increased to a safe value to avoid futher commutation failure, this done by -Advance value. Harmonic detection unit detects harmonics and increases ref to avoid commutation failure. They also proposed a method for rst detacting the voltage 21

Figure 1.32: Series resonance scheme

Figure 1.33: Series resonance scheme amplitude and harmonics content. Eect of AC system frequency spectrum on commutation failure in HVDC inverters Commutation failure is the mazor concern in the design of HVDC system. COntinious commuattion failure causes temperary blocking of HVDC links which adversely eect the dynamical stability of the system. Commutation failure mainly aected by so many factors like the magnitude of voltagfe dip due to fault,phase shift, dc current rise. These facts mainly depends on the SCR of theinverter bus, also the lters, compensators presence. So in a weak SCR network, commuattion faillure is a mazor concern of problem which also causes slower recovery from a fault. Generally when commutation faillure occures or going to occure, the control system advances the gating angle to reduce the probability of commutation failuer. Sometimes VDCOL also helps to reduce the commutation failure rate by reducing the current order. when there is a decrease in dc link voltage due disturbance. In [17], author has shown that as we have a gamma controller, , or VDCOL or some protecting device , to avoid commutation failure but if the disturbance occures exactly when the ring pulse is going to be issued to the thyrister valve, the probability of commutation failure is more as no immediate action by controller is not possible. So they have used a new concept of changing the AC frequency spectrum of inverter bus. They have found that when a disturbance occures the voltage of the inverter bus decreases. SO the transient response of voltage at that period consists of two major components 1) One Exponencial decaying compoinent 2) a undrdamped oscillatory component consists of many harmonic components. The exponential component mainly determines the nal change in the fundamental voltage. The rst component mainly depends on the location of fault and SCR of the inverter bus but the second component mainly depend on local 22

Figure 1.34: Series resonance scheme

Figure 1.35: Series resonance scheme network impedances and AC harmonic lters and size of capacitor banks. They have rst explained the eect of dierent type of voltage dip on commutation failure. Fig. 2 and g.3 shows the two dierent fault conditions and their eect on commutating voltage time area.acdfa is the normal volt-time area where as bcdeb is the volt-time area during voltage disturbance. In gure, it is shown thhat the disturbance occures at teh peak of commutating voltage. As the volt-time area has to be remain constant assumind constant dc link current, so bcdcb and acdfa should be equal or greater. If during fault (bcdcb) the volt-time area is less tahn the normal volt-time area abdfathen there is a commutation failure. Asssuming commutation margin is zero. So it can be seen in comparision to g.2 and g.3, the volt-time area is signicantly increased in g.3 as compared to g.2 for fault condition. It can be seen that in g.3, the commutating voltage contains a dominant low frequency harmonic oscillatory coponent where as g. 3 contains a very high frequency. So thay have tried to create a high frequency oscillatory component in the faulted voltage curve by connecting a lter with network. The system considered in this work is shown in g.4. Here at bus 2 a fault is created. They rst nd out the transfer functions V1 as shown in g.4. Then by eigen value analysis they nd that the dominant V2 mode area exponential decay component and a oscillatory underdamped component of 196HZ. Now they considered a single tuned series LC lter tunesd to second harmonic at the inverter bus SO it can also provide reactive power at fundamental frequency. Now they again do the eigen analyss with lter and foungd the dominat mode as 466Hz. In g.5 and g.65 shows the commutating voltage during fault without lter and with lter respectively. They also shown by by simulation that probability of commutation failure decreases signicantly.

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Figure 1.36: Series resonance scheme

Figure 1.37: Series resonance scheme

1.5

Harmonic Instability

In [1-2], fourier analysis techniques is used to ndout the harmonic spectrum of DC side voltage cnsidering commutation overlap. Here they have considered dierent conditions like AC supply voltage distortion, AC side voltage imbalance with dirent ring control schmes like individual phase ring and equidistance ring. They also considered small ring angle excursion limits about the nominal value. Due to abnormalities (may be single or in combination) causes increase in strength of uncharacteristics harmonics. They have also shown that during all cases equidistance ring scheme always produces less harmonic as compared to individula phase schme. In [2], they have shown above cases for production of harmonics with considering a practical impedances. In [3], authors has considered dierent cases for uncharacteristics harmonic generation. The cases are converter transformer impedances unbalance and the ring angle imbalance between two six-pulse bridges in a 12-pulse converter. They have not considered AC network impedance. They have shown that in these cases there is a signicant amount of third harmonic component in AC current and all 6n 1 also generated in 12 pulse converter. They independently analyse the eect of transformer impedance imbalance and ring angle imbalance. They also shown that harmonics are also dependant on ring angle. They have considered ideal AC source with no lters at converter bus. Transformer impedance imbalance causes unequal overlap angle. In [14], author considered the case of AC system voltage distortion during three phase fault recovery on transformer energigation and have tried to get dc side harmonc voltages. The following conclusions are made: 1. Odd balanced ac harmonics do not generate any non characteristic harmonic at dc side. 2. Unbalanced odd ac harmonics generate all even harmonics on the dc side.

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Figure 1.38: Series resonance scheme

Figure 1.39: Series resonance scheme 3. Even balanced ac harmonics generate only tripplen harmonics on the dc side. 4. Even unbalanced ac harmonics generate all odd harmonics on the dc side. The bus voltage distortion during transient ( fault recovery or energigation of converter transformer) lasts for long time causing overloading of lters in dc side which subsequently causes trip of lter and shut down of pole. In [5], harmonic instability caused by the parallal resonace between AC network impedance and lter ckt isdiscussed. Sometimes controller action favoures harmonic instability. As by use of SC increases eective SCR, so improves harmonic instability. In [17], they have found three pulse harmonics in a real New England-Hydro-Quebec plant and this is due to the ring pulse imbalance between two converetrs in 12 pulse HVDC systems.

1.5.1

Minimisation of uncharacteristics harmonics by ring angle modulation

In thsi paper the control voltage is modulated by a modulating signal so that a particular harmonics or group of harmonics (uncharacteristics) can be eleminated.The modulating signal is generated from the dc current ripple. The block diagram representation of generation of MS and its addition with the control voltage is shown in g.12. They have shown that if control voltage is modulated by a 50Hz modulating signal then a 2nd harmonic component of current which causes a 2nd harmonic voltage in AC side can be created. So, if this 2nd harmonic is exactly opposite to the initial 2nd harmonic on the converter bus then they gets cancelled. So by this way any uncharacteristics harmonic or group of harmonics can be eleminated on AC side by modulating the control voltage Vc . 25

Figure 1.40: Series resonance scheme In g.1 they have shown how the modulating signal is added to the control voltage .They have get modulating signal by lterring the dc link current error value from reference value. This is done by frequency selector unit. Then injecting circuit modulate the phase and amplitude of modulating signal and nally its output gets added with control voltage Vc . Transient detector which detects any sudden change in current then it bypass the modulating signal by grounging the mmodulating port. They have chossen dc current to get modulating signal as if uncharacteristics voltage is in the converter AC bus then its transformation frequency from is produced in the dcvoltage terminal and produces corresponding frequency current. SO by seeing the current, it is possible to know the uncharacteristic harmonc strength in converter AC voltage. To cancell a particular uncharacteristic harmonics what modulating signal is required is given in Table 1. They have shown this by testing in HVDC simulator. DONT FORGET TO ADD TABLE They also discussed there wiil be abnormal eect if MS is not chosen properly. They 26

Figure 1.41: Series resonance scheme

Figure 1.42: Series resonance scheme have given strategy to choose MS as given below. Step 1: Injection into the control voltage of a very small amlitude of the selected MS (amplitude nearer to 0.1 Volt) Step 2: Tuning of MS phase to minimise the selected AC harmonics. Step 3: MS amplitude increased untill the AC side harmonics has reached its minimum value. Step 4: COnvergence to optimum value can be reached by repeating Step 2 and Step 3. In [17], author has shown by simulation how harmonic instability occures. The DC current and volage is shown in g. 12. Author uses a very stable control system so they have shown that the harmonic instability is not caused by alone AC side or DC side resonance but due to some complementary resonances frequencies between AC and DC side. They have also used an ring angle modulation scheme to avoid harmonic instability. The control diagram is shown in Fig.3. In g. 3, shows a low pass and band pass lter are in series.So that a band of lower order harmonics is extracted and which are used to modulate dc voltage by ring angle modulation. They also used on modulation of the current order so taht the harmoniocs in the current order both 3rd anf 5th gets cancelled. The current order modulation is shown in g. 7. In [18], a C-type lter as shown in g. 13 is used to improve harmonic instability. Here L1 and C1 tuned to AC bus frequency and where the combination of all components are tuned to lower harmonic between 3rd and 6th. As argued by author generally harmonic instability occure due to the parrallel resonance at AC side with lower damping and its complementary exit in DC line side. So by using C-type lter they improve the damping of parrallel resonance of AC side ad decrease the correspong harmonic impedance. They also shown that through simulation , the the improvement of harmonic instability during

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Figure 1.43: Series resonance scheme

Figure 1.44: Series resonance scheme start up. If possible show the gure]. FIg. 7 shows how harmonic instability occures to lower damping of parral resonance of AC side So the system needs to be shut down after some time when AC breaker trips or commutation failure occure. In [18], modulation theory is used to calculate harmonic transfer from AC to DC side and vice versa. Also harmonics due to ac voltages at rectier and inverter opearting at dierent frequencies. Dc side resonance Initial transformer energigation, transformer after fault recovery causes magnetic inrush. Frequency spectrum in magnetic inrush currents are dc,2nd,3rd,4th and many more. Single phase faults create unbalance which causes 2nd harmonic osscillation on dc side. Also persistent commutation failure causes 50HZ component of bus voltage on DC link. Core Saturation Instability Generally the lter impedance and ac side impedance froms parallel resonance conditions at lower harmonic frequencies. So these lower harmonic frequencies generally generated by the transformer during its core saturation and causing over voltage at the AC converter 28

Figure 1.45: Series resonance scheme

Figure 1.46: Series resonance scheme bus. If a rectier supplied from isolated AC system with no local load, this voltage may rise to two times two times its rated value. These overvoltage persists foa a many cycles of fundamental ferquency due to its slower decay rate. This phenomena is known as core saturation instability. If ther is any controllable reactive power device present at the bus bar, then this can be controlled otherwise slower tap changing operation limits the voltage to a lower value after a long time. This is the problem most frequently faced faced by the HVDC system during transformer energigation. OTher abnormal conditions like blocking and deblocking of bridge, ac-dc faults, dc load change,causes a parrallel resonance condition by exciting the corresponding parallel resonance frequency but this over voltage decays very fastly. These over voltage might be seen only once within a disturbance cylcle. But transformer inrush current over voltages remain for long time and it rings the parallel resonance once per cycle and continue for many cycles of fundamental frequency. Causes of Magnetic Inrush Current When a transformer deenergiged, the transformer core is left with a residual ux which in case of cold rolled steel used in modern high power transformer can be approximately 80 percent of rated magnetic ux. Upon energigation of this transformer at a instant when the generated ux adds the residual ux, the transformer goes to saturation region and draws a high value of current. (High current peaks can be seen once in acycle). In [17], the basic concept behind magnetic inrush phenomena and eect for both starstar and star-delta transformer is discused. Due to distortion in current (3rd harmonic) in delta transformer, the width of peaky current pulse during saturation increased. But

29

Figure 1.47: Series resonance scheme

Figure 1.48: Series resonance scheme magniture remain unchanged. They have considered a HVDC system with lters and did test of energigation at dierent instants on voltage wave. The ipedance of lter ckt and ac network independently shown in g. 2. The following conclusions are made 1. Ac bus bar over voltage can build up slowly over a number of cycles and decays slowly as inrush current peak decays. 2. Over voltage peaks are produced even in lower peak inrush currents. 3. Over voltage increases as the AC system impedance angle increases (resitive part decreases) and it decreases as SCR increases. The type of lter they considered is capacitive at below 5th harmonics. If AC system becomes inductive at these frequencies then there is a parallel resonance (considering synchronous machine). It can be seen from g. 1that the system is ringing at 3rd harmonics for SCR=3 and ringing at 4th hrmonics for SCR =6. Through simulation, it is also shown that due to transformer inrush, a parrallal resonance occures at 3rd harmonics. and generate a high voltage of 2p.u. and slowly decreases. They also explain intuitively how this 2p.u over voltage occures. As shown in g. 2when transformer goes to saturation, the saturable reactance(XT ) of transformer as shown in g. 12 is very small so the lter capacitor discharges at this period through saturable reactor. When transformer goes out of saturation, capacitor starts charging and charged two double the previous value i.e 2p.u. this process continues on each cycle ans as inrush curent decreases, the over voltage also decreases. They also have suggested some of the methods to reduce these over voltage, these are given below.

30

Figure 1.49: Series resonance scheme

Figure 1.50: Series resonance scheme 1.Selecting lter impedance During decrease in power throgh the DC link, the generators connected in parallel are tripped which causes an incrase in ac network impedance. IF lters are designed properly for normal condition, now causes parral resonance with ac ssystem. So they must be selected prperly so that this will not happen. Sometimes lter switching can be done to avoid parral resonance tyupe of condition. 2.Damped lters By increasing the resistance of ac lter, more damping can be provided to inrush current. But ler eciency is degraded. 3. Switched register During transformer energigation resister banks can be connected in series with the transformer so that inrush current can be damped quickly. Timed Transformer Energigation If the transformer could be timed such that energigation take palce at the instants on wave which coincides with previous de-energigation time. This method can be made even simpler by injecting dc-current and making the residual usx as desired for timed energigation. In [13], authors also discussed simmilar way of creation of harmonic instability. They designed a transformer model during saturation and validated with eld data. In [13], they also discussed above overvoltages due to transformer saturation. They have the frequency component of inrush current as shown in g. 14 and also their decay w.r.t to time cycle. By changing the system part dierent parrallel resonance points are achievable i.e 3rd, 4th and 2nd also. As can be seen from the gure how 4th harmonic component rst decays to zero and then creases to peak at the 10 th cycle. SO sometimews afetr a long time overvoltages can be seen. They aslo discussed the eect of system damping and insersion series resistor on damping core saturation instability.

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Figure 1.51: Series resonance scheme

Figure 1.52: Series resonance scheme In [15], authors have projected a problem faced during tripping of a ac line. The system is shown in g.1. here the line 7040 trips as a result converter 2 is blocked but converter 1 is isolated. As a result all transformer and converter 2 transformer works. As there is a mazor power block, a transient high voltage is observed at 120KV and 725KV bus. This transient died down slowly as shown in g.2. This takes a long timed They found that as the voltage increased suddenly due to power shedding, transformer goes to saturation so injects all odd harmonics. It doesnot cause parrallel resonance immediately. They found by fourier analysis the frequency component of g.1 as mostly 5th and 7th harmonics. The AC ssystem in the present condition has a parrallel resonance at 350 HZ. Due load shedding, the ppower frequency increases from 60 to 74Hz. So yhe system has a 5th harmonic resonance when system reached at 70Hz. SO as the system frequency increases the system gradually moves towards parrallel resonance. Then it goes out of that when system frequency goes above 70Hz. A sthe system moves towards parallel resonance, the transient voltage peak further increases but when it just crosses the parrallel resonance, the transients immediately died down. System goes to parallel resonance at 1.7 sec in g.12. The reason for this as given by then as the frequency increases, the voltage increases from 1.2 pu to 1.29pu for frequency change from 60HZ to 70 Hz at. SO the decreases from 32

Figure 1.53: Series resonance scheme

Figure 1.54: Series resonance scheme 1.18pu to 1.10 pu. As a result, as requency increases more and more, the ux decreases and goes out of saturation region. So harmonic injected by transformer decreases so over voltage also decreases quickly. They have proved these things also by simulation. The simulation results are shown in g.1.g.2.g.3.

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Figure 1.55: Series resonance scheme

Figure 1.56: Series resonance scheme

34

Figure 1.57: Series resonance scheme

35