TLV 2771

TLV277x, TLV277xA FAMILY OF 2.
7 V HIGH SLEW RATE RAIL TO RAIL OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS209G JANUARY 1998 REVISED FEBRUARY 2004
D D D D D D D D
High Slew Rate . . . 10.5 V/s Typ High-Gain Bandwidth . . . 5.1 MHz Typ Supply Voltage Range 2.5 V to 5.5 V Rail-to-Rail Output 360 V Input Offset Voltage Low Distortion Driving 600- 0.005% THD+N 1 mA Supply Current (Per Channel) 17 nV/Hz Input Noise Voltage
D D D D D
2 pA Input Bias Current Characterized From TA = 55C to 125C Available in MSOP and SOT-23 Packages Micropower Shutdown Mode . . . IDD < 1 A Available in Q-Temp Automotive High Reliability Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards
description
The TLV277x CMOS operational amplifier family combines high slew rate and bandwidth, rail-to-rail output swing, high output drive, and excellent dc precision. The device provides 10.5 V/s of slew rate and 5.1 MHz of bandwidth while only consuming 1 mA of supply current per channel. This ac performance is much higher than current competitive CMOS amplifiers. The rail-to-rail output swing and high output drive make these devices a good choice for driving the analog input or reference of analog-to-digital converters. These devices also have low distortion while driving a 600- load for use in telecom systems. These amplifiers have a 360-V input offset voltage, a 17 nV/Hz input noise voltage, and a 2-pA input bias current for measurement, medical, and industrial applications. The TLV277x family is also specified across an extended temperature range (40C to 125C), making it useful for automotive systems, and the military temperature range (55C to 125C), for military systems. These devices operate from a 2.5-V to 5.5-V single supply voltage and are characterized at 2.7 V and 5 V. The single-supply operation and low power consumption make these devices a good solution for portable applications. The following table lists the packages available.
FAMILY PACKAGE TABLE DEVICE TLV2770 TLV2771 TLV2772 TLV2773 TLV2774 TLV2775 NUMBER OF CHANNELS 1 1 2 2 4 4 PACKAGE TYPES SHUTDOWN PDIP 8 8 14 14 16 CDIP 8 SOIC 8 8 8 14 14 16 SOT-23 5 TSSOP 8 14 16 MSOP 8 8 10 LCCC 20 CPAK 10 Yes Yes Yes Refer to the EVM Selection Guide (Lit# SLOU060) UNIVERSAL EVM BOARD
A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS DEVICE TLV277X TLV247X TLV245X TLV246X VDD (V) 2.5 6.0 2.7 6.0 2.7 6.0 2.7 6.0 BW (MHz) 5.1 2.8 0.22 6.4 SLEW RATE (V/s) 10.5 1.5 0.11 1.6 IDD (per channel) (A) 1000 600 23 550 RAIL-TO-RAIL O I/O I/O I/O
All specifications measured at 5 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.
Copyright 19982004, Texas Instruments Incorporated

On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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TLV277x, TLV277xA FAMILY OF 2.7 V HIGH SLEW RATE RAIL TO RAIL OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN
TLV2770 and TLV2771 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25C (mV) 2.5 2.5 40C to 125C 1.6 SMALL OUTLINE (D) TLV2770CD TLV2771CD TLV2770ID TLV2771ID TLV2770AID TLV2771AID SOT-23 (DBV) TLV2771CDBV TLV2771IDBV MSOP (DGK) TLV2770CDGK TLV2770IDGK PLASTIC DIP (P) TLV2770CP TLV2770IP TLV2770AIP
0C to 70C
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability. TLV2772 and TLV2773 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25C (mV) 2.5 2.5 40C to 125C 1.6 SMALL OUTLINE (D) TLV2772CD TLV2773CD TLV2772ID TLV2773ID TLV2772AID TLV2773AID MSOP (DGK) TLV2772CDGK TLV2772IDGK MSOP (DGS) TLV2773CDGS TLV2773IDGS PLASTIC DIP (N) TLV2773CN TLV2773IN TLV2773AIN PLASTIC DIP (P) TLV2772CP TLV2772IP TLV2772AIP
0C to 70C
TLV2774 and TLV2775 AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25C (mV) 2.7 2.7 40C to 125C 2.1 SMALL OUTLINE (D) TLV2774CD TLV2775CD TLV2774ID TLV2775ID TLV2774AID TLV2775AID PLASTIC DIP (N) TLV2775CN TLV2775IN TLV2775AIN PLASTIC DIP (P) TLV2774CP TLV2774IP TLV2774AIP TSSOP (PW) TLV2774CPW TLV2775CPW TLV2774IPW TLV2775IPW TLV2774AIPW TLV2775AIPW
0C to 70C
TLV2772M/Q AND TLV2772AM/Q AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25C (mV) 2.5 40C to 125C 55C to 125C Available in tape and reel 1.6 2.5 1.6 SMALL OUTLINE (D) TLV2772QD TLV2772AQD TLV2772MD TLV2772AMD CHIP CARRIER (FK) TLV2772MFK TLV2772AMFK CERAMIC DIP (JG) TLV2772MJG TLV2772AMJG CERAMIC FLATPACK (U) TLV2772MU TLV2772AMU TSSOP (PW) TLV2772QPW TLV2772AQPW
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PACKAGE SYMBOLS PACKAGE TYPE SOT23 PINS 5 Pin PART NUMBER TLV2771CDBV TLV2771IDBV TLV2770CDGK TLV2770IDGK 8 Pin MSOP 10 Pin xx represents the device date code. TLV2772CDGK TLV2772IDGK TLV2773CDGS TLV2773IDGS SYMBOL VAMC VAMI xxTIABO xxTIABP xxTIAAF xxTIAAG xxTIABQ xxTIABR
TLV277x PACKAGE PINOUT

TLV2772M AND TLV2772AM FK PACKAGE (TOP VIEW)
NC 1IN NC 1IN + NC
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC 1OUT NC VDD+ NC NC 2OUT NC 2IN NC

NC No internal connection
NC GND NC 2IN+ NC
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TLV277x PACKAGE PINOUTS(1)
TLV2770 D, DGK OR P PACKAGE (TOP VIEW) TLV2771 DBV PACKAGE (TOP VIEW) OUT GND IN+ 1 2 3 4 IN 5 VDD TLV2771 D PACKAGE (TOP VIEW)
NC IN IN + GND
1 2 3 4
8 7 6 5
SHDN VDD OUT NC
NC IN IN + GND
1 2 3 4
8 7 6 5
NC VDD OUT NC
TLV2772 D, DGK, JG, P, OR PW PACKAGE (TOP VIEW)
TLV2772M AND TLV2772AM U PACKAGE (TOP VIEW)
TLV2773 DGS PACKAGE (TOP VIEW)
1OUT 1IN 1IN + GND
1 2 3 4
8 7 6 5
VDD 2OUT 2IN 2IN+
NC 1OUT 1IN 1IN + GND
1 2 3 4 5
10 9 8 7 6
NC VDD + 2OUT 2IN 2IN +
1OUT 1IN 1IN+ GND 1SHDN
1 2 3 4 5
10 9 8 7 6
VDD 2OUT 2IN 2IN+ 2SHDN
TLV2773 D OR N PACKAGE (TOP VIEW)
TLV2774 D, N, OR PW PACKAGE (TOP VIEW)
TLV2775 D, N, OR PW PACKAGE (TOP VIEW)
1OUT 1IN 1IN+ GND NC 1SHDN NC
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD 2OUT 2IN 2IN+ NC 2SHDN NC
1OUT 1IN 1IN+ VDD 2IN+ 2IN 2OUT
1 2 3 4 5 6 7
14 13 12 11 10 9 8
4OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT
1OUT 1IN 1IN+ VDD 2IN+ 2IN 2OUT 1/2SHDN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
4OUT 4IN 4IN+ GND 3IN + 3IN 3OUT 3/4SHDN
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability. (1) SOT23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1 Printed or Molded Dot
Pin 1 Stripe
Pin 1 Bevel Edges
Pin 1 Molded U Shape
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input voltage range, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Duration of short-circuit current (at or below) 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 125C Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 125C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to GND . 2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below GND 0.3 V. 3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE D DBV DGK DGS FK JG N P PW U TA 25C 25 C POWER RATING 725 mW 437 mW 424 mW 424 mW 1375 mW 1050 mW 1150 mW 1000 mW 700 mW 675 mW DERATING FACTOR ABOVE TA = 25C 5.8 mW/C 3.5 mW/C 3.4 mW/C 3.4 mW/C 11.0 mW/C 8.4 mW/C 9.2 mW/C 8.0 mW/C 5.6 mW/C 5.4 mW/C TA = 70C 70 C POWER RATING 464 mW 280 mW 271 mW 271 mW 672 mW 880 mW 736 mW 640 mW 448 mW 432 mW TA = 85C 85 C POWER RATING 377 mW 227 mW 220 mW 220 mW 546 mW 714 mW 598 mW 520 mW 364 mW 350 mW TA = 125C 125 C POWER RATING 145 mW 87 mW 85 mW 85 mW 210 mW 275 mW 230 mW 200 mW 140 mW 135 mW
recommended operating conditions

C SUFFIX MIN Supply voltage, VDD Input voltage range, VI Common-mode input voltage, VIC Operating free-air temperature, TA 2.5 GND GND 0 MAX 6 VDD + 1.3 VDD + 1.3 70 I SUFFIX MIN 2.5 GND GND 40 MAX 6 VDD + 1.3 VDD + 1.3 125 Q SUFFIX MIN 2.5 GND GND 40 MAX 6 VDD + 1.3 VDD + 1.3 125 M SUFFIX MIN 2.5 GND GND 55 MAX 6 VDD + 1.3 VDD + 1.3 125 UNIT V V V C
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electrical characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted)
PARAMETER TLV2770/1/2 VIO Input offset voltage TLV2773/4/5 VIO IIO IIB Temperature coefficient of input offset voltage Input offset current Input bias current IOH = 0.675 mA VOH High-level output voltage IOH = 2.2 mA VIC = 1.35 V, VOL Low-level output voltage VIC = 1.35 V, AVD ri(d) ci(c) zo CMRR kSVR IDD IDD(SHDN) Large-signal differential voltage amplification Differential input resistance Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply voltage rejection ratio (VDD /VIO) Supply current (per channel) Supply current in shutdown (per channel) TLV2770 V(ON) Turnon voltage level TLV2773 TLV2775 TLV2770 V(OFF) Turnoff voltage level TLV2773 TLV2775 Full range is 0C to 70C. AV = 5 25 C 25C AV = 5 25 C 25C f = 10 kHz f = 100 kHz, VIC = 0 to 1.5 V, RS = 50 VDD = 2.7 V to 5 V, No load VO = VDD/2, AV = 10 VO = VDD/2, VIC = VDD /2, VIC = 1.35 V, VO = 0.6 V to 2.1 V IOL = 2.2 mA RL = 10 k, IOL = 0.675 mA VIC = 0, RS = 50 VO = 0, VDD = 1.35 V 1.35 TEST CONDITIONS TA 25C VIC = 0, RS = 50 , No load VO = 0, VDD = 1.35 V, Full range 25C Full range 25C to 25 C 125C 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C 25C 25C 25C Full range 25C Full range No load 25C Full range 25C Full range 0.8 1.3 1.47 1.43 1.40 1.27 1.21 1.20 V V 60 60 70 70 20 13 1012 8 25 84 82 89 84 1 2 2 1.5 2 dB mA A dB TLV277xC MIN TYP 0.48 0.53 0.8 0.86 2 1 2 2 6 2.6 2.5 2.4 2.1 0.1 0.2 0.21 0.6 380 V/mV pF V V 60 100 60 100 pA pA MAX 2.5 2.7 2.7 2.9 V/C V/C mV UNIT
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operating characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted)
PARAMETER TEST CONDITIONS VO(PP) = 0.8 V, RL = 10 k f = 1 kHz Vn VN(PP) In THD + N Equivalent input noise voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current f = 10 kHz f = 0.1 Hz to 1 Hz f = 0.1 Hz to 10 Hz f = 100 Hz RL = 600 , f = 1 kHz f = 10 kHz, CL = 100 pF AV = 1, Step = 1 V, RL = 600 , CL = 100 pF RL = 600 , AV = 1 AV = 10 AV = 100 Gain-bandwidth product RL = 600 , 0.1% 0.01% CL = 100 pF 25C 25C 25C 25C 25C 25C 25C CL = 100 pF, TA 25C SR Slew rate at unity gain Full range 25C 25C TLV277xC MIN 5 4.7 TYP 9 6 21 17 0.33 0.86 0.6 0.0085% 25 C 25C 0.025% 0.12% 4.8 0.186 s s 0.3 46 12 dB MHz nV/Hz V V fA /Hz V/s MAX UNIT
Total harmonic distortion plus noise
ts m
Settling time
Phase margin at unity gain Gain margin
Full range is 0C to 70C.
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electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA 25C TLV2770/1/2 VIO Input offset voltage TLV2773/4/5 VIO IIO IIB Temperature coefficient of input offset voltage Input offset current Input bias current IOH = 1.3 mA VOH High-level output voltage IOH = 4.2 mA VIC = 2.5 V, VOL Low-level output voltage VIC = 2.5 V, AVD ri(d) ci(c) zo CMRR kSVR IDD IDD(SHDN) Large-signal differential voltage amplification Differential input resistance Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply voltage rejection ratio (VDD /VIO) Supply current (per channel) Supply current in shutdown (per channel) TLV2770 V(ON) Turnon voltage level TLV2773 TLV2775 TLV2770 V(OFF) Turnoff voltage level TLV2773 TLV2775 Full range is 0C to 70C. AV = 5 25 C 25C AV = 5 25 C 25C f = 10 kHz f = 100 kHz, VIC = 0 to 3.7 V, RS = 50 VDD = 2.7 V to 5 V, No load VO = VDD /2, AV = 10 VO = VDD /2, VIC = VDD /2, VIC = 2.5 V, VO = 1 V to 4 V IOL = 4.2 mA RL = 10 k, IOL = 1.3 mA VIC = 0, RS = 50 VO = 0, VDD = 2.5 V 2.5 VIC = 0, , RS = 50 No load VO = 0, VDD = 2.5 V, Full range 25C Full range 25 C 25C to 125C 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C 25C 25C 25C Full range 25C Full range No load 25C Full range 25C Full range 0.8 1.3 2.59 2.47 2.48 2.41 2.32 2.29 V V 70 70 70 70 20 13 1012 8 20 96 93 89 84 1 2 2 1.5 2 dB mA A A dB TLV277xC MIN TYP 0.5 0.6 0.7 0.78 2 1 2 2 6 4.9 4.8 4.7 4.4 0.1 0.2 0.21 0.6 450 V/mV pF V V 60 100 60 100 pA pA MAX 2.5 2.7 2.5 2.7 V/C V/C mV UNIT
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operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS VO(PP) = 2 V, RL = 10 k f = 1 kHz Vn VN(PP) In THD + N Equivalent input noise voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current f = 10 kHz f = 0.1 Hz to 1 Hz f = 0.1 Hz to 10 Hz f = 100 Hz RL = 600 , f = 1 kHz f = 10 kHz, CL = 100 pF AV = 1, Step = 2 V, RL = 600 , CL = 100 pF RL = 600 , TLV2770 t(ON) Amplifier turnon time TLV2773 TLV2775 TLV2770 t(OFF) Amplifier turnoff time TLV2773 TLV2775 Full range is 0C to 70C. AV = 5 RL = Open, Measured to 50% point 25 C 25C AV = 5, RL = Open, Measured to 50% point 25C 25 C AV = 1 AV = 10 AV = 100 Gain-bandwidth product RL = 600 , 0.1% 0.01% CL = 100 pF 25C 25C 25C 25C 25C 25C 25C CL = 100 pF, TA 25C SR Slew rate at unity gain Full range 25C 25C TLV277xC MIN 5 4.7 TYP 10.5 6 17 12 0.33 0.86 0.6 0.005% 25 C 25C 0.016% 0.095% 5.1 0.335 s s 0.6 46 12 1.2 2.4 1.9 335 444 345 ns s dB MHz nV/Hz V V fA /Hz V/s MAX UNIT
Total harmonic distortion plus noise
ts m
Settling time
Phase margin at unity gain Gain margin
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PARAMETER TEST CONDITIONS VIC = 0, VO = 0, RS = 50 VDD = 1.35 V, 1.35 No load TA 25C Full range 25C Full range 25 C 25C to 125C VIC = 0, VO = 0, RS = 50 25C Full range 25C IIB Input bias current IOH = 0.675 mA VOH High-level output voltage IOH = 2.2 mA VIC = 1.35 V, IOL = 0.675 mA VIC = 1.35 V, IOL = 2.2 mA Large-signal differential voltage amplification Differential input resistance Common-mode input capacitance Closed-loop output impedance f = 10 kHz, f = 100 kHz, AV = 10 VIC = 0 to 1.5 V, VO = VDD /2, RS = 50 VDD = 2.7 V to 5 V, VIC = VDD /2, No load VO = VDD /2, No load VIC = 1.35 V, RL = 10 k, k VO = 0.6 V to 2.1 V Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C 25C 25C 25C Full range 25C Full range 25C Full range 25C Full range 0.8 1.3 60 60 70 70 20 13 1012 8 25 84 82 89 84 1 2 2 1.5 2 0.8 1.3 60 60 70 70 TLV277xI MIN TYP 0.48 0.53 0.8 0.86 2 1 2 2 6 2.6 2.5 2.4 2.1 0.1 0.2 0.21 0.6 380 20 13 1012 8 25 84 dB 82 89 dB 84 1 2 2 1.5 2 mA A pF 60 125 60 350 MAX 2.5 2.7 2.7 2.9 TLV277xAI MIN TYP 0.48 0.53 0.8 0.86 2 1 2 2 6 2.6 2.5 2.4 2.1 0.1 0.2 0.21 0.6 380 V/mV V V 60 125 60 350 pA pA MAX 1.6 1.9 2.1 2.2 V/C V/C mV UNIT
TLV2770/1/2 VIO Input offset voltage TLV2773/4/5 VIO IIO Temperature coefficient of input offset voltage Input offset current
VOL
Low-level output voltage
AVD ri(d) ci(c) zo
CMRR
Common-mode rejection ratio
kSVR
Supply voltage rejection ratio (VDD /VIO) Supply current (per channel) Supply current in shutdown (per channel)
IDD IDD(SHDN)
10
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electrical characteristics at specified free-air temperature, VDD = 2.7 V (unless otherwise noted) (continued)
PARAMETER TLV2770 V(ON) Turnon voltage level TLV2773 TLV2775 TLV2770 V(OFF) Turnoff voltage level TLV2773 TLV2775 Full range is 40C to 125C. AV = 5 25 C 25C AV = 5 25C 25 C TEST CONDITIONS TA TLV277xI MIN TYP 1.47 1.43 1.40 1.27 1.21 1.20 MAX TLV277xAI MIN TYP 1.47 1.43 1.4 1.27 1.21 1.2 V V MAX UNIT
PARAMETER TEST CONDITIONS VO(PP) = 0.8 V, RL = 10 k f = 1 kHz f = 10 kHz f = 0.1 Hz to 1 Hz f = 0.1 Hz to 10 Hz f = 100 Hz RL = 600 , f = 1 kHz f = 10 kHz, CL = 100 pF AV = 1, Step = 0.85 V to 1.85 V, RL = 600 , CL = 100 pF RL = 600 , AV = 1 AV = 10 AV = 100 Gain-bandwidth product RL = 600 , 25C 25C 25C 25C 25C CL = 100 pF, TA 25C SR Slew rate at unity gain Equivalent input noise voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion plus noise Full range 25C 25C 25C 25C 25C TLV277xI MIN 5 4.7 TYP 9 6 21 17 0.33 0.86 0.6 0.0085% 25C 25 C 0.025% 0.12% 4.8 0.186 3.92 46 12 MAX MIN 5 4.7 TLV277xAI TYP 9 6 21 17 0.33 0.86 0.6 0.0085% 0.025% 0.12% 4.8 0.186 s s 0.01% 3.92 46 12 dB MHz nV/Hz V V fA /Hz V/s MAX UNIT
Vn
VN(PP) In
THD + N
0.1%
ts
Settling time
Phase margin at unity gain
CL = 100 pF
Gain margin Full range is 40C to 125C.
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11
PARAMETER TEST CONDITIONS TLV2770/1/2 VIO Input offset voltage TLV2773/4/5 VIO IIO IIB Temperature coefficient of input offset voltage Input offset current Input bias current IOH = 1.3 mA VOH High-level output voltage IOH = 4.2 mA VIC = 2.5 V, IOL = 1.3 mA VIC = 2.5 V, IOL = 4.2 mA Large-signal differential voltage amplification Differential input resistance Common-mode input capacitance Closed-loop output impedance f = 10 kHz f = 100 kHz, AV = 10 VIC = 0 to 3.7 V, VO = VDD /2, RS = 50 VDD = 2.7 V to 5 V, VIC = VDD /2, No load VO = VDD /2, No load VIC = 2.5 V, RL = 10 k, k VO = 1 V to 4 V VIC = 0, No load VO = 0, RS = 50 , , VDD = 2.5 V 2.5 TA 25C Full range 25C Full range 25 C 25C to 125C 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C 25C 25C 25C Full range 25C Full range 25C Full range 25C Full range 0.8 1.3 60 60 70 70 20 13 1012 8 20 96 93 89 84 1 2 2 1.5 2 0.8 1.3 70 70 70 70 TLV277xI MIN TYP 0.5 0.6 0.7 0.78 2 1 2 2 6 4.9 4.8 4.7 4.4 0.1 0.2 0.21 0.6 450 20 13 1012 8 20 96 dB 93 89 dB 84 1 2 2 1.5 2 mA A A pF 60 125 60 350 MAX 2.5 2.7 2.5 2.7 TLV277xAI MIN TYP 0.5 0.6 0.7 0.78 2 1 2 2 6 4.9 4.8 4.7 4.4 0.1 0.2 0.21 0.6 450 V/mV V V 60 125 60 350 pA pA MAX 1.6 1.9 2.1 2.2 V/C V/C mV UNIT
VIC = 0, VO = 0, , RS = 50 , VDD = 2.5 V 2.5
VOL
Low-level output voltage
AVD ri(d) ci(c) zo
CMRR
Common-mode rejection ratio
kSVR
Supply voltage rejection ratio (VDD /VIO) Supply current (per channel) Supply current shutdown (per channel)
IDD IDD(SHDN)
12
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electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued)
PARAMETER TLV2770 V(ON) Turnon voltage level TLV2773 TLV2775 TLV2770 V(OFF) Turnoff voltage level TLV2773 TLV2775 Full range is 40C to 125C. AV = 5 25 C 25C AV = 5 25C 25 C TEST CONDITIONS TA TLV277xI MIN TYP 2.59 2.47 2.48 2.41 2.32 2.29 MAX TLV277xAI MIN TYP 2.59 2.47 2.48 2.41 2.32 2.29 V V MAX UNIT

PARAMETER TEST CONDITIONS VO(PP) = 1.5 V, RL = 10 k f = 1 kHz f = 10 kHz f = 0.1 Hz to 1 Hz f = 0.1 Hz to 10 Hz f = 100 Hz RL = 600 , f = 1 kHz f = 10 kHz, CL = 100 pF AV = 1, Step = 1.5 V to 3.5 V, RL = 600 , CL = 100 pF RL = 600 , AV = 1 AV = 10 AV = 100 Gain-bandwidth product RL = 600 , 25C 25C 25C 25C 25C AV = 5, RL = Open, Measured to 50% point AV = 5, RL = Open, Measured to 50% point CL = 100 pF, TA 25C SR Slew rate at unity gain Equivalent input noise voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion plus noise Full range 25C 25C 25C 25C 25C TLV277xI MIN 5 4.7 TYP 10.5 6 17 12 0.33 0.86 0.6 0.005% 25C 25 C 0.016% 0.095% 5.1 0.134 1.97 46 12 1.2 25 C 25C 2.4 1.9 335 25C 25 C 444 345 MAX MIN 5 4.7 TLV277xAI TYP 10.5 6 17 12 0.33 0.86 0.6 0.005% 0.016% 0.095% 5.1 0.134 s s 0.01% 1.97 46 12 1.2 2.4 1.9 335 444 345 ns s dB MHz nV/Hz V V fA /Hz V/s MAX UNIT
Vn
VN(PP) In
THD + N
0.1%
ts
Settling time
Phase margin at unity gain Gain margin Amplifier turnon time Amplifier turnoff time TLV2770 TLV2773 TLV2775 TLV2770 TLV2773 TLV2775
CL = 100 pF
t(ON)
t(OFF)
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PARAMETER TEST CONDITIONS TA 25C VIO VIO Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Full range VDD = 1.35 V, VIC = 0, RS = 50 25C to 125C 25C Full range 25C IIB Full range 25 C 25C VICR Common-mode input voltage range CMRR > 60 dB, RS = 50 Full range 25C VOH High-level output voltage IOH = 0.675 mA IOH = 2.2 mA VIC = 1.35 V, VIC = 1.35 V, Large-signal differential voltage amplification Differential input resistance Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply voltage rejection ratio (VDD /VIO) Supply current (per channel) f = 10 kHz, f = 100 kHz, VIC = VICR (min), RS = 50 VDD = 2.7 V to 5 V, No load VO = 1.5 V, AV = 10 VO = 1.5 V, VIC = 1.35 V, VO = 0.6 V to 2.1 V IOL = 0.675 mA IOL = 2.2 mA RL = 10 k, Full range 25C Full range 25C VOL Low-level output voltage Full range 25C Full range 25C Full range 25C 25C 25C 25C Full range VIC = VDD /2, 25C Full range No load 25C Full range 60 60 70 70 20 13 1012 8 25 84 82 89 84 1 2 2 60 60 70 70 380 0.21 0.6 20 13 1012 8 25 84 82 89 dB 84 1 2 2 mA dB pF 380 V/mV 2.1 0.1 0.2 0.21 0.6 2.45 2.4 2.1 0.1 0.2 V 0 to 1.4 0 to 1.4 TLV2772Q TLV2772M MIN TYP 0.44 0.47 2 1 2 2 6 0.3 to 1.7 0.3 to 1.7 2.6 2.45 2.4 V 60 125 60 350 0 to 1.4 0 to 1.4 MAX 2.5 2.7 TLV2772AQ TLV2772AM MIN TYP 0.44 0.47 2 1 2 2 6 0.3 to 1.7 0.3 to 1.7 2.6 V 60 125 60 350 pA pA MAX 1.6 1.9 mV UNIT
VO = 0,
V/C V/C
IIO
AVD ri(d) ci(c) zo CMRR
kSVR
IDD
Full range is 40C to 125C for Q level part, 55C to 125C for M level part. Referenced to 1.35 V
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PARAMETER TEST CONDITIONS TA MIN 25C SR Slew rate at unity gain Equivalent input noise voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion plus noise Gain-bandwidth product VO(PP) = 0.8 V, RL = 10 k f = 1 kHz f = 10 kHz f = 0.1 Hz to 1 Hz f = 0.1 Hz to 10 Hz f = 100 Hz RL = 600 , f = 1 kHz f = 10 kHz, CL = 100 pF AV = 1, Step = 0.85 V to 1.85 V, RL = 600 , CL = 100 pF RL = 600 , AV = 1 AV = 10 AV = 100 RL = 600 , 25C 25C 25C 25C CL = 100 pF, Full range 25C 25C 25C 25C 25C 5 4.7 TLV2772Q TLV2772M TYP 9 6 21 17 0.33 0.86 0.6 0.0085% 25 C 25C 0.025% 0.12% 4.8 0.186 3.92 46 12 MAX MIN 5 4.7 TLV2772AQ TLV2772AM TYP 9 6 21 17 0.33 0.86 0.6 0.0085% 0.025% 0.12% 4.8 0.186 s s 0.01% 3.92 46 12 dB MHz nV/Hz V V fA /Hz V/s MAX UNIT
Vn
VN(PP) In
THD + N
0.1%
ts
Settling time
CL = 100 pF
Gain margin 25C Full range is 40C to 125C for Q level part, 55C to 125C for M level part.
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PARAMETER TEST CONDITIONS TA 25C VIO VIO Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Full range 25C to 125C 25C Full range 25C IIB Full range 25 C 25C VICR Common-mode input voltage range CMRR > 60 dB, RS = 50 Full range 25C VOH High-level output voltage IOH = 1.3 mA IOH = 4.2 mA VIC = 2.5 V, VIC = 2.5 V, Large-signal differential voltage amplification Differential input resistance Common-mode input capacitance Closed-loop output impedance Common-mode rejection ratio Supply voltage rejection ratio (VDD /VIO) Supply current (per channel) f = 10 kHz, f = 100 kHz, VIC = VICR (min), RS = 50 VDD = 2.7 V to 5 V, No load VO = 1.5 V, AV = 10 VO = 3.7 V, VIC = 2.5 V, VO = 1 V to 4 V IOL = 1.3 mA IOL = 4.2 mA RL = 10 k, Full range 25C Full range 25C VOL Low-level output voltage Full range 25C Full range 25C Full range 25C 25C 25C 25C Full range VIC = VDD /2, 25C Full range No load 25C Full range 60 60 70 70 20 13 1012 8 20 96 93 89 84 1 2 2 60 60 70 70 450 0.21 0.6 20 13 1012 8 20 96 93 89 dB 84 1 2 2 mA dB pF 450 V/mV 4.4 0.1 0.2 0.21 0.6 4.8 4.7 4.4 0.1 0.2 V 0 to 3.7 0 to 3.7 TLV2772Q TLV2772M MIN TYP 0.36 0.4 2 1 2 2 6 0.3 to 3.8 0.3 to 3.8 4.9 4.8 4.7 V 60 125 60 350 0 to 3.7 0 to 3.7 MAX 2.5 2.7 TLV2772AQ TLV2772AM MIN TYP 0.36 0.4 2 1 2 2 6 0.3 to 3.8 0.3 to 3.8 4.9 V 60 125 60 350 pA pA MAX 1.6 1.9 mV UNIT
VDD = 2.5 V, VIC = 0,
VO = 0, RS = 50
V/C V/C
IIO
AVD ri(d) ci(c) zo CMRR
kSVR
IDD
Full range is 40C to 125C for Q level part, 55C to 125C for M level part. Referenced to 2.5 V
16
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PARAMETER TEST CONDITIONS TA MIN 25C SR Slew rate at unity gain Equivalent input noise voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion plus noise Gain-bandwidth product VO(PP) = 1.5 V, RL = 10 k f = 1 kHz f = 10 kHz f = 0.1 Hz to 1 Hz f = 0.1 Hz to 10 Hz f = 100 Hz RL = 600 , f = 1 kHz f = 10 kHz, CL = 100 pF AV = 1, Step = 1.5 V to 3.5 V, RL = 600 , CL = 100 pF RL = 600 , AV = 1 AV = 10 AV = 100 RL = 600 , 25C 25C 25C 25C CL = 100 pF, Full range 25C 25C 25C 25C 25C 5 4.7 TLV2772Q TLV2772M TYP 10.5 6 17 12 0.33 0.86 0.6 0.005% 25 C 25C 0.016% 0.095% 5.1 0.134 1.97 46 12 MAX MIN 5 4.7 TLV2772AQ TLV2772AM TYP 10.5 6 17 12 0.33 0.86 0.6 0.005% 0.016% 0.095% 5.1 0.134 s s 0.01% 1.97 46 12 dB MHz nV/Hz V V fA /Hz V/s MAX UNIT
Vn
VN(PP) In
THD + N
0.1%
ts
Settling time
CL = 100 pF
Gain margin 25C Full range is 40C to 125C for Q level part, 55C to 125C for M level part.
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TYPICAL CHARACTERISTICS Table of Graphs
FIGURE VIO IIB/IIO VOH VOL VO(PP) IOS VO AVD AVD zo CMRR kSVR IDD SR VO VO VO VO Vn THD + N B1 m Input offset voltage Input bias and input offset currents High-level output voltage Low-level output voltage Maximum peak-to-peak output voltage Short-circuit output current Output voltage Large-signal differential voltage amplification and phase margin Differential voltage amplification Output impedance Common-mode rejection ratio Supply-voltage rejection ratio Supply current (per channel) Slew rate Voltage-follower small-signal pulse response Voltage-follower large-signal pulse response Inverting small-signal pulse response Inverting large-signal pulse response Equivalent input noise voltage Noise voltage (referred to input) Total harmonic distortion plus noise Gain-bandwidth product Unity-gain bandwidth Phase margin Gain margin Amplifier with shutdown pulse turnon/off characteristics Supply current with shutdown pulse turnon/off characteristics Shutdown supply current Shutdown forward/reverse isolation vs Free-air temperature vs Frequency vs Frequency Over a 10-second period vs Frequency vs Supply voltage vs Load capacitance vs Load capacitance vs Load capacitance Distribution vs Common-mode input voltage Distribution vs Free-air temperature vs High-level output current vs Low-level output current vs Frequency vs Supply voltage vs Free-air temperature vs Differential input voltage vs Frequency vs Load resistance vs Free-air temperature vs Frequency vs Frequency vs Free-air temperature vs Frequency vs Supply voltage vs Load capacitance vs Free-air temperature 1,2 3,4 5,6 7 8,9 10,11 12,13 14 15 16 17,18 19 20,21 22,23 24 25 26,27 28 29 30 31,32 33,34 35,36 37,38 39,40 41 42,43 44 45 46 47 48 50 51 53 54 55, 56
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TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772 INPUT OFFSET VOLTAGE
40 35 Percentage of Amplifiers % 30 25 20 15 10 5 0 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 VIO Input Offset Voltage mV VDD = 2.7 V RL = 10 k TA = 25C Percentage of Amplifiers % 40 35 30 25 20 15 10 5 0 2.5 2 1.5 1 0.5 0 0.5 1 1.5 2 2.5 VIO Input Offset Voltage mV VDD = 5 V RL = 10 k TA = 25C
Figure 1
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
2 1.5 VIO Input Offset Voltage mV 1 0.5 0 0.5 1 1.5 2 1 VDD = 2.7 V TA = 25C VIO Input Offset Voltage mV 2 1.5 1 0.5 0 0.5 1 1.5 2 1 0.5 VDD = 5 V TA = 25C
Figure 2
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
0.5
0.5
1.5
2.5
0.5
1.5
2.5
3.5
4.5
VIC Common-Mode Input Voltage V
VIC Common-Mode Input Voltage V
Figure 3
Figure 4
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35 30 Percentage of Amplifiers % VDD = 2.7 V TA = 25C to 125C Percentage of Amplifiers % 35 30 VDD = 5 V TA = 25C to 125C
25
25
20
20
15
15
10 5 0
10 5 0
12
12
VIO Temperature Coefficient V/C
VIO Temperature Coefficient V/C
Figure 5
INPUT BIAS AND OFFSET CURRENT vs FREE-AIR TEMPERATURE
I IB and I IO Input Bias and Input Offset Currents nA 0.20 VDD = 5 V VIC = 0 VO = 0 RS = 50 0.15 IIB 3
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
VDD = 2.7 V VOH High-Level Output Voltage V 2.5
TA = 40C
0.10
1.5 TA = 125C 1 TA = 25C 0.5 TA = 85C
0.05 IIO
0 75
50
25
25
50
75
100
125
10
15
20
25
TA Free-Air Temperature C
IOH High-Level Output Current mA
Figure 7
Figure 8
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HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
5 4.5 VOH High-Level Output Voltage V 4 3.5 TA = 25C 3 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 IOH High-Level Output Current mA TA = 125C TA = 85C VDD = 5 V TA = 25C VOL Low-Level Output Voltage V 2.5 TA = 125C 2 TA = 85C TA = 40C 3 VDD = 2.7 V
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
1.5
1 TA = 40C
TA = 25C
0.5
10
15
20
25
30
IOL Low-Level Output Current mA
Figure 9
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
VO(PP) Maximum Peak-to-Peak Output Voltage V 3 VDD = 5 V VOL Low-Level Output Voltage V 2.5 TA = 85C 2 TA = 125C 5 VDD = 5 V 1% THD 4
Figure 10
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY
RL = 10 k
3 VDD = 2.7 V 2% THD
1.5 TA = 25C 1 TA = 40C 0.5
0 0 10 20 30 40 50 IOL Low-Level Output Current mA
0 100
1000 f Frequency kHz
10000
Figure 11
Figure 12
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MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY
VO(PP) Maximum Peak-to-Peak Output Voltage V 5 4.5 4 3.5 VDD = 5 V 3 2.5 2 1.5 1 0.5 0 100 1000 f Frequency kHz 10000 VDD = 2.7 V I OS Short-Circuit Output Current mA THD = 5% RL = 600 TA = 25C 60 45 30 15 0 15 30 VID = 100 mV 45 60 2 VO = VDD /2 VIC = VDD /2 TA = 25C
SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE
VID = 100 mV
VDD Supply Voltage V
Figure 13
SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE
60 I OS Short-Circuit Output Current mA 5
Figure 14
OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE
RL = 600 TA = 25C
40
VID = 100 mV VO Output Voltage V
VDD = 5 V
20 VDD = 5 V VO = 2.5 V
3 VDD = 2.7 V 2
20 VID = 100 mV
40
60 75
50
25
25
50
75
100
125
0 1000 750 500 250
250
500
750
1000
VID Differential Input Voltage V
Figure 15
Figure 16
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LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN vs FREQUENCY
100 A VD Large-Signal Differential Amplification dB VDD = 2.7 V RL = 600 CL = 600 pF TA = 25C 300 240 180 120 Phase 60 0 60 90 10M m Phase Margin degrees m Phase Margin degrees
80 AVD 60 40 20 0 20 40 100
1k
10k
100k
1M
f Frequency Hz
Figure 17
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN vs FREQUENCY
100 A VD Large-Signal Differential Amplification dB VDD = 5 V RL = 600 CL = 600 pF TA = 25C 300 240 180 120 Phase 60 0 60 90 10M
80 60 40 20 0 20 40 100 AVD
1k
10k
100k
1M
f Frequency Hz
Figure 18
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DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE
250 A VD Differential Voltage Amplification V/mV A VD Differential Voltage Amplification V/mV TA = 25C 200 VDD = 5 V 150 VDD = 2.7 V 1000 RL = 10 k
DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
100
RL = 1 M RL = 600
10
100
1 VDD = 2.7 V VIC = 1.35 V VO = 0.6 V to 2.1 V 0.1 75 50 25 0 25 50 75 100 125
50
0.1
10
100
1000
RL Load Resistance k
Figure 19
DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
1000 A VD Differential Voltage Amplification V/mV RL = 10 k 100 VDD = 2.7 V TA = 25C ZO Output Impedance 10 AV = 100
Figure 20
OUTPUT IMPEDANCE vs FREQUENCY
100
RL = 1 M
RL = 600 10
1 AV = 10
1 VDD = 5 V VIC = 2.5 V VO = 1 V to 4 V 0.1 75 50 25 0 25 50 75 100 125
0.10
AV = 1
0.01 100
1k
10k f Frequency Hz
100k
1M
Figure 21
Figure 22
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OUTPUT IMPEDANCE vs FREQUENCY
100 CMRR Common-Mode Rejection Ratio dB VDD = 2.5 V TA = 25C Zo Output Impedance 10 Av = 100 90 VDD = 2.7 V VDD = 5 V 80
COMMON-MODE REJECTION RATIO vs FREQUENCY

VIC = 1.35 V and 2.5 V TA = 25C
70
1 Av = 10 0.1 Av = 1
60
50
0.01 100
1k
10k f Frequency Hz
100k
1M
40 10
100
1k
10k
100k
1M
10M
f Frequency Hz
Figure 23
COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE
120 CMRR Common-Mode Rejection Ratio dB 115 110 105 100 95 90 85 80 40 20 VDD = 5 V VDD = 2.7 V k SVR Supply-Voltage Rejection Ratio dB 120 kSVR+ 100 kSVR 80
Figure 24
SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY
VDD = 2.7 V TA = 25C
60
40
20
20
40
60
80
100 120 140
0 10
100
1k
10k
100k
1M
10M
f Frequency Hz
Figure 25
Figure 26
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SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY
120 k SVR Supply Voltage Rejection Ratio dB kSVR+ kSVR 80 I DD Supply Current (Per Channel) mA VDD = 5 V TA = 25C 1.6 TA = 125C 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 TA = 85C TA = 25C TA = 0C TA = 40C
SUPPLY CURRENT (PER CHANNEL) vs SUPPLY VOLTAGE
100
60
40
20
0 10
100
1k
10 k
100 k
1M
10 M
3.5
4.5
5.5
6.5
f Frequency Hz
VDD Supply Voltage V
Figure 27
SLEW RATE vs LOAD CAPACITANCE
16 SR+ 14 SR SR Slew Rate V/ s 12 SR Slew Rate s 10 8 6 4 2 0 10 100 1k 10k 100k CL Load Capacitance pF 9 12 VDD = 5 V AV = 1 TA = 25C 14
Figure 28
SLEW RATE vs FREE-AIR TEMPERATURE
VDD = 2.7 V RL = 10 k CL = 100 pF AV = 1
13
11
10
8 75
50
25
25
50
75
100
125
Figure 29
Figure 30
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VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE
100 80 VO Output Voltage mV 60 40 20 0 20 40 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t Time s VDD = 2.7 V RL = 600 CL = 100 pF AV = 1 TA = 25C 100 80 VO Output Voltage mV 60 40 20 0 20 40 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t Time s VDD = 5 V RL = 600 CL = 100 pF AV = 1 TA = 25C
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE
Figure 31
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE
3 2.5 2 1.5 1 0.5 0 0.5 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t Time s VDD = 2.7 V RL = 600 CL = 100 pF AV = 1 TA = 25C 6 5 4 3 2 1 0 1 2 0 0.5 1 VDD = 5 V RL = 600 CL = 100 pF AV = 1 TA = 25C
Figure 32
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE
VO Output Voltage V
VO Output Voltage V
1.5
2.5
3.5
4.5
t Time s
Figure 33
Figure 34
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INVERTING SMALL-SIGNAL PULSE RESPONSE
100 80 VO Output Voltage mV 60 40 20 0 20 40 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t Time s VDD = 2.7 V RL = 600 CL = 100 pF AV = 1 TA = 25C 100 80 VO Output Voltage mV 60 40 20 0 20 40 60 0 0.5 1 1.5 2 2.5 3 t Time s 3.5 4 4.5 5
INVERTING SMALL-SIGNAL PULSE RESPONSE

VDD = 5 V RL = 600 CL = 100 pF AV = 1 TA = 25C
Figure 35
INVERTING LARGE-SIGNAL PULSE RESPONSE
3 2.5 2 1.5 1 0.5 0 0.5 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t Time s VDD = 2.7 V RL = 600 CL = 100 pF AV = 1 TA = 25C VO Output Voltage V 4 3.5 3 2.5 2 1.5 1 0.5 1 0 0.5 1 VDD = 5 V RL = 600 CL = 100 pF AV = 1 TA = 25C
Figure 36
INVERTING LARGE-SIGNAL PULSE RESPONSE
VO Output Voltage V
1.5
2 2.5 3 t Time s
3.5
4.5
Figure 37
Figure 38
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EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
160 140 Vn Input Noise Voltage nV/ Hz 120 100 80 60 40 20 0 10 100 1k 10k f Frequency Hz VDD = 2.7 V RS = 20 TA = 25C 140 120 VDD = 5 V RS = 20 TA = 25C
EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
Vn Input Noise Voltage nV Hz
100 80
60 40 20 0 10 100 1k 10k f Frequency Hz
Figure 39
NOISE VOLTAGE OVER A 10 SECOND PERIOD
VDD = 5 V f = 0.1 Hz to 10 Hz TA = 25C
Figure 40
300 200 Noise Voltage nV 100 GND 100 200 300
10
t Time s
Figure 41
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TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY
THD+N Total Harmonic Distortion Plus Noise % VDD = 2.7 V RL = 600 TA = 25C 1 THD+N Total Harmonic Distortion Plus Noise % 10
TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY

10 VDD = 5 V RL = 600 TA = 25C 1
Av = 100 0.1 Av = 10 Av = 1
0.1
Av = 100
Av = 10 0.01 Av = 1
0.01
0.001 10
100
1k f Frequency Hz
10k
100k
0.001 10
100
1k f Frequency Hz
10k
100k
Figure 42
GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE
5.2 RL = 600 CL = 100 pF f = 10 kHz TA = 25C 5
Figure 43
UNITY-GAIN BANDWIDTH vs LOAD CAPACITANCE
VDD = 5 V RL = 600 TA = 25C
5 Gain-Bandwidth Product MHz
4.8
Unity-Gain Bandwidth MHz
3 Rnull = 100 2 Rnull = 50 Rnull = 20
4.6
4.4
4.2
4 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD Supply Voltage V
Rnull = 0 0 10 100 1k 10k 100k
CL Load Capacitance pF
Figure 44
Figure 45
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PHASE MARGIN vs LOAD CAPACITANCE
90 80 m Phase Margin degrees 70 Rnull = 50 Gain Margin dB 60 50 Rnull = 20 40 30 20 10 0 10 Rnull = 0 VDD = 5 V RL = 600 TA = 25C 0 5 10 15 20 Rnull = 100 25 Rnull = 50 30 Rnull = 20 35 40 10 Rnull = 0 VDD = 5 V RL = 600 TA = 25C
GAIN MARGIN vs LOAD CAPACITANCE
Rnull = 100
100
1k
10k
100K
100
1k
10k
100K
Figure 46
TLV2770
Figure 47
TLV2773
AMPLIFIER WITH SHUTDOWN PULSE TURNON/OFF CHARACTERISTICS

6 4 2 Shutdown Signal V 0 SHDN = GND 2 4 6 8 VO 10 12 4 2 0 2 4 6 8 10 12 VDD = 5 V AV = 5 TA = 25C 4 3 2 1 0 1 14 SHDN = VDD 8 7 6 VO Output Voltage V Shutdown Signal V 5 8 6 4 2 0 2 4 6

8 SHDN = VDD 7 6 VDD = 5 V SHDN = GND AV = 5 TA = 25C Channel 1 Switched Channel 2 SHDN MODE Channel 1 VO Output Voltage V 31 5 4 3 2 1 VO 8 10 2.5 0 2.5 5 7.5 10 12.5 0 1 15
t Time s
t Time s
Figure 48
Figure 49
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TLV2775 CHANNEL 1 TLV2770

8 6 4 Shutdown Signal V 2 0 2 4 6 8 10 2.5 VO VDD = 5 V SHDN = GND AV = 5 TA = 25C Channel 1/2 Switched Channel 3/4 SHDN MODE Channel 1 SHDN = VDD 8 7 6 VO Output Voltage V Shutdown Signal V 5 4 3 2 1 0 1 15
SUPPLY CURRENT WITH SHUTDOWN PULSE TURNON/OFF CHARACTERISTICS

6 4 2 0 SHDN = GND 2 4 6 8 10 12 4 2 IDD VDD = 5 V AV = 5 TA = 25C 12 9 6 3 0 3 14 SHDN = VDD 24 21 18 15 I DD Supply Current mA I DD Supply Current mA
2.5
7.5
10
12.5
10
12
t Time s
t Time s
Figure 50
TLV2773
Figure 51
TLV2775

6 3 0 SHDN = GND Shutdown Signal V 3 6 9 12 IDD 15 18 5 0 3 15 VDD = 5 V AV = 5 TA = 25C Channel 1 Switched Channel 2 SHDN MODE 40 30 20 10 SHDN = VDD 70 60 50

6 3 0 SHDN = GND Shutdown Signal V 3 6 9 12 IDD 15 18 5 0 3 15 VDD = 5 V AV = 5 TA = 25C Channel 1/2 Switched Channel 3/4 SHDN MODE 40 30 20 10 SHDN = VDD 70 60 50
2.5
2.5
7.5
I DD Supply Current mA
10
12.5
2.5
2.5
7.5
10
12.5
t Time s
t Time s
Figure 52
Figure 53
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SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE
7 I DD Shutdown Supply Current A 6 5 4 VDD 5 V 3 AV = 5 RL = OPEN SHDN = GND Shutdown Forward Isolation dB 140 120 100 80 60 40 20 0 0 75 50 25 0 25 50 75 100 125 20 10 TLV2770
SHUTDOWN FORWARD ISOLATION vs FREQUENCY
VI(PP) = 2.7 V VI(PP) = 0.1 V
2 VDD 2.7 V 1
SHDN MODE AV = 1 VDD = 2.7 V RL = 10 k CL = 20 pF TA = 25C 102 103 104 f Frequency Hz 105 106
Figure 54
TLV2770
Figure 55
SHUTDOWN REVERSE ISOLATION vs FREQUENCY
VI(PP) = 2.7 V
140 120 Shutdown Reverse Isolation dB 100 80 60 40 20 0 20 10
VI(PP) = 0.1 V
SHDN MODE AV = 1 VDD = 2.7 V RL = 10 k CL = 20 pF TA = 25C 102 103 104 f Frequency Hz 105 106
Figure 56
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33
PARAMETER MEASUREMENT INFORMATION
_ + RL CL Rnull
Figure 57
driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the devices phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 58. A minimum value of 20 should work well for most applications.
RF RG Input
_ +
RNULL Output CLOAD
Figure 58. Driving a Capacitive Load
34
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APPLICATION INFORMATION offset voltage

The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF RG IIB V + VI RS IIB+ + OO +V IO 1) R R F "I IB) R S 1) R R F "I IB R F
VO
Figure 59. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 60).
RG RF f VI + R1 C1 VO V O + V I 1) R R F 1 1 ) sR1C1 3dB + 1 2pR1C1
Figure 60. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier.
C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) f 3dB + 1 2pRC
VI R1 R2 C2
+ _
RG
RF
RG =
RF 1 2 Q
Figure 61. 2-Pole Low-Pass Sallen-Key Filter
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35
APPLICATION INFORMATION using the TLV2772 as an accelerometer interface
The schematic, shown in Figure 62, shows the ACH04-08-05 interfaced to the TLV1544 10-bit analog-to-digital converter (ADC). The ACH04-08-05 is a shock sensor designed to convert mechanical acceleration into electrical signals. The sensor contains three piezoelectric sensing elements oriented to simultaneously measure acceleration in three orthogonal, linear axes (x, y, z). The operating frequency is 0.5 Hz to 5 kHz. The output is buffered with an internal JFET and has a typical output voltage of 1.80 mV/g for the x and y axis and 1.35 mV/g for the z axis. Amplification and frequency shaping of the shock sensor output is done by the TLV2772 rail-to-rail operational amplifier. The TLV2772 is ideal for this application as it offers high input impedance, good slew rate, and excellent dc precision. The rail-to-rail output swing and high output drive are perfect for driving the analog input of the TLV1544 ADC.
1.23 V R3 10 k C2 2.2 nF
R4 100 k 3V 1 Axis ACH040805 C1 0.22 F R1 100 k R2 1 M 3V 2 8 1 4 1/2 TLV2772 + 3 _ R5 1 k Output to TLV1544 (ADC) C3 0.22 F
Signal Conditioning
3V R6 2.2 k
Shock Sensor 1.23 V
1.23 V
C R TLV431 A
Voltage Reference
Figure 62. Accelerometer Interface Schematic The sensor signal must be amplified and frequency-shaped to provide a signal the ADC can properly convert into the digital domain. Figure 62 shows the topology used in this application for one axis of the sensor. This system is powered from a single 3-V supply. Configuring the TLV431 with a 2.2-k resistor produces a reference voltage of 1.23 V. This voltage is used to bias the operational amplifier and the internal JFETs in the shock sensor.
36
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APPLICATION INFORMATION
gain calculation Since the TLV2772 is capable of rail-to-rail output using a 3-V supply, VO = 0 (min) to 3 V (max). With no signal from the sensor, nominal VO = reference voltage = 1.23 V. Therefore, the maximum negative swing from nominal is 0 V 1.23 V = 1.23 V and the maximum positive swing is 3 V 1.23 V = 1.77 V. By modeling the shock sensor as a low impedance voltage source with output of 2.25 mV/g (max) in the x and y axis and 1.70 mV/g (max) in the z axis, the gain of the circuit is calculated by equation 1. Gain + Output Swing Sensor Signal Acceleration (1)
To avoid saturation of the operational amplifier, the gain calculations are based on the maximum negative swing of 1.23 V and the maximum sensor output of 2.25 mV/g (x and y axis) and 1.70 mV/g (z axis). Gain (x, y) + and Gain (z) + 1.23 V + 14.5 1.70 mV g 50 g (3) * 1.23 V + 10.9 2.25 mV g * 50 g (2)
By selecting R3 = 10 k and R4 = 100 k, in the x and y channels, a gain of 11 is realized. By selecting R3 = 7.5 k and R4 = 100 k, in the z channel, a gain of 14.3 is realized. The schematic shows the configuration for either the x- or y-axis. bandwidth calculation To calculate the component values for the frequency shaping characteristics of the signal conditioning circuit, 1 Hz and 500 Hz are selected as the minimum required 3-dB bandwidth. To minimize the value of the input capacitor (C1) required to set the lower cutoff frequency requires a large value resistor for R2 is required. A 1-M resistor is used in this example. To set the lower cutoff frequency, the required capacitor value for C1 is: C1 + 1 + 0.159 F 2p f LOW R 2 (4)
Using a value of 0.22 F, a more common value of capacitor, the lower cutoff frequency is 0.724 Hz. To minimize the phase shift in the feedback loop caused by the input capacitance of the TLV2772, it is best to minimize the value of the feedback resistor R4. However, to reduce the required capacitance in the feedback loop a large value for R4 is required. Therefore, a compromise for the value of R4 must be made. In this circuit, a value of 100 k has been selected. To set the upper cutoff frequency, the required capacitor value for C2 is: C2 + 1 + 3.18 F 2p f HIGH R 4 (5)
Using a 2.2-nF capacitor, the upper cutoff frequency is 724 Hz. R5 and C3 also cause the signal response to roll off. Therefore, it is beneficial to design this roll-off point to begin at the upper cutoff frequency. Assuming a value of 1 k for R5, the value for C3 is calculated to be 0.22 F.
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APPLICATION INFORMATION circuit layout considerations
To achieve the levels of high performance of the TLV277x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following.
D Ground planesIt is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decouplingUse a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
D SocketsSockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation.
D Short trace runs/compact part placementsOptimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier.
D Surface-mount passive componentsUsing surface-mount passive components is recommended for high

performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible.
38
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APPLICATION INFORMATION general power dissipation considerations

For a given JA, the maximum power dissipation is shown in Figure 63 and is calculated by the following formula: P Where: D + T T MAX A q JA
PD = Maximum power dissipation of TLV277x IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W)
MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE
2 1.75 Maximum Power Dissipation W 1.5 1.25 1 0.75 0.5 0.25
SOT-23 Package Low-K Test PCB JA = 324C/W SOIC Package Low-K Test PCB JA = 176C/W PDIP Package Low-K Test PCB JA = 104C/W TJ = 150C
MSOP Package Low-K Test PCB JA = 260C/W
0 55 40 25 10 5
20 35 50 65 80 95 110 125
TA Free-Air Temperature C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 63. Maximum Power Dissipation vs Free-Air Temperature
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APPLICATION INFORMATION shutdown function
Three members of the TLV277x family (TLV2770/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.8 A/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care needs to be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2. Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to be pulled to VDD (not GND) to disable the operational amplifier. The amplifiers output with a shutdown pulse is shown in Figures 48, 49, and 50. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. The bump on the rising edge of the TLV2770 output waveform is due to the start-up circuit on the bias generator. For the dual and quad (TLV2773/5), this bump is attributed to the bias generators start-up circuit as well as the crosstalk between the other channel(s), which are in shutdown. Figures 55 and 56 show the amplifiers forward and reverse isolation in shutdown. The operational amplifier is powered by 1.35-V supplies and configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency for both 0.1 VPP and 2.7 VPP input signals. During normal operation, the amplifier would not be able to handle a 2.7-VPP input signal with a supply voltage of 1.35 V since it exceeds the common-mode input voltage range (VICR). However, this curve illustrates that the amplifier remains in shutdown even under a worst case scenario.
40
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APPLICATION INFORMATION macromodel information

Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 64 are generated using the TLV2772 typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D Maximum positive output voltage swing D Unity-gain frequency D Maximum negative output voltage swing D Common-mode rejection ratio D Slew rate D Phase margin D Quiescent power dissipation D DC output resistance D Input bias current D AC output resistance D Open-loop voltage amplification D Short-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 VDD + css rp 2 IN dp IN+ 1 11 C1 rd1 GND 4 ve * TLV2772 operational amplifier macromodel subcircuit * created using Parts release 8.0 on 12/12/97 at 10:08 * Parts is a MicroSim product. * * connections: noninverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt TLV2772 12345 * c1 11 12 2.8868E-12 c2 6 7 10.000E12 css 10 99 2.6302E12 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 15.513E6 1E3 1E3 16E6 16E6 ga 6 0 11 12 188.50E6 gcm 0 6 10 99 9.4472E9 iss hlim j1 j2 r2 rd1 rd2 ro1 ro2 rp rss vb vc ve vlim vlp vln .model .model .model .model .ends *$ 3 90 11 12 6 4 4 8 7 3 10 9 3 54 7 91 0 dx dy jx1 jx2 + OUT 10 dc 145.50E6 0 vlim 1K 2 10 jx1 1 10 jx2 9 100.00E3 11 5.3052E3 12 5.3052E3 5 17.140 99 17.140 4 4.5455E3 99 1.3746E6 0 dc 0 53 dc .82001 4 dc .82001 8 dc 0 0 dc 47 92 dc 47 D(Is=800.00E18) D(Is=800.00E18 Rs=1m Cjo=10p) PJF(Is=2.2500E12 Beta=244.20E6 + Vto=.99765) PJF(Is=1.7500E12 Beta=244.20E6 + Vto=1.002350) rd2 54 de 5 12 dc j1 10 j2 + vc r2 53 6 gcm rss 3 9 iss + vb C2 7 + ga vlim 8 egnd + fb ro2 90 + dlp hlim 91 + vlp 92 vln + dln
ro1
Figure 64. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.
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41
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device 5962-9858801Q2A 5962-9858801QHA 5962-9858801QPA 5962-9858802Q2A 5962-9858802QHA 5962-9858802QPA TLV2770AID TLV2770AIDG4 TLV2770AIP TLV2770AIPE4 TLV2770CD TLV2770CDG4 TLV2770CDR TLV2770CDRG4 TLV2770CP TLV2770CPE4 TLV2770IDGKR TLV2770IDGKRG4 TLV2770IDR TLV2770IDRG4 TLV2770IP TLV2770IPE4 Status
(1)
Package Type Package Drawing LCCC CFP CDIP LCCC CFP CDIP SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP MSOP MSOP SOIC SOIC PDIP PDIP FK U JG FK U JG D D P P D D D D P P DGK DGK D D P P
Pins 20 10 8 20 10 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Package Qty 1 1 1 1 1 1 75 75 50 50 75 75 2500 2500 50 50 2500 2500 2500 2500 50 50
Eco Plan TBD TBD TBD TBD TBD TBD
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
POST-PLATE N / A for Pkg Type A42 A42 A42 A42 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type
POST-PLATE N / A for Pkg Type
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type
Addendum-Page 1
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30-Jul-2011
Orderable Device TLV2771AIDR TLV2771AIDRG4 TLV2771CD TLV2771CDBVR TLV2771CDBVRG4 TLV2771CDBVT TLV2771CDBVTG4 TLV2771CDG4 TLV2771CDR TLV2771CDRG4 TLV2771ID TLV2771IDBVR TLV2771IDBVRG4 TLV2771IDBVT TLV2771IDBVTG4 TLV2771IDG4 TLV2771IDR TLV2771IDRG4
Status
(1)
Package Type Package Drawing SOIC SOIC SOIC SOT-23 SOT-23 SOT-23 SOT-23 SOIC SOIC SOIC SOIC SOT-23 SOT-23 SOT-23 SOT-23 SOIC SOIC SOIC D D D DBV DBV DBV DBV D D D D DBV DBV DBV DBV D D D
Pins 8 8 8 5 5 5 5 8 8 8 8 5 5 5 5 8 8 8
Package Qty 2500 2500 75 3000 3000 250 250 75 2500 2500 75 3000 3000 250 250 75 2500 2500
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 2
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30-Jul-2011
Orderable Device TLV2772AID TLV2772AIDG4 TLV2772AIDR TLV2772AIDRG4 TLV2772AIP TLV2772AIPE4 TLV2772AMD TLV2772AMDG4 TLV2772AMDR TLV2772AMDRG4 TLV2772AMFKB TLV2772AMJGB TLV2772AMUB TLV2772AQD TLV2772AQDG4 TLV2772AQDR TLV2772AQDRG4 TLV2772AQPW TLV2772AQPWG4 TLV2772AQPWR TLV2772AQPWRG4 TLV2772CD
Status
(1)
Package Type Package Drawing SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC LCCC CDIP CFP SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP SOIC D D D D P P D D D D FK JG U D D D D PW PW PW PW D
Pins 8 8 8 8 8 8 8 8 8 8 20 8 10 8 8 8 8 8 8 8 8 8
Package Qty 75 75 2500 2500 50 50 75 75 2500 2500 1 1 1 75 75 2500 2500 150 150 2000 2000 75
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) TBD Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM POST-PLATE N / A for Pkg Type A42 A42 N / A for Pkg Type N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 3
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30-Jul-2011
Orderable Device TLV2772CDG4 TLV2772CDGK TLV2772CDGKG4 TLV2772CDGKR TLV2772CDGKRG4 TLV2772CDR TLV2772CDRG4 TLV2772CP TLV2772CPE4 TLV2772ID TLV2772IDG4 TLV2772IDGK TLV2772IDGKG4 TLV2772IDGKR TLV2772IDGKRG4 TLV2772IDR TLV2772IDRG4 TLV2772IP TLV2772IPE4 TLV2772MD
Status
(1)
Package Type Package Drawing SOIC MSOP MSOP MSOP MSOP SOIC SOIC PDIP PDIP SOIC SOIC MSOP MSOP MSOP MSOP SOIC SOIC PDIP PDIP SOIC D DGK DGK DGK DGK D D P P D D DGK DGK DGK DGK D D P P D
Pins 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Package Qty 75 80 80 2500 2500 2500 2500 50 50 75 75 80 80 2500 2500 2500 2500 50 50 75
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) TBD
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-220C-UNLIM
Addendum-Page 4
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30-Jul-2011
Orderable Device TLV2772MDG4 TLV2772MDR TLV2772MDRG4 TLV2772MFKB TLV2772MJGB TLV2772MUB TLV2772QD TLV2772QDG4 TLV2772QDR TLV2772QDRG4 TLV2772QPW TLV2772QPWG4 TLV2772QPWR TLV2772QPWRG4 TLV2773AIN TLV2773AINE4 TLV2773CDGS TLV2773CDGSG4 TLV2773CDGSR TLV2773CDGSRG4 TLV2773CDR
Status
(1)
Package Type Package Drawing SOIC SOIC SOIC LCCC CDIP CFP SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP PDIP PDIP MSOP MSOP MSOP MSOP SOIC D D D FK JG U D D D D PW PW PW PW N N DGS DGS DGS DGS D
Pins 8 8 8 20 8 10 8 8 8 8 8 8 8 8 14 14 10 10 10 10 14
Package Qty 75 2500 2500 1 1 1 75 75 1500 2500 150 150 2000 2000 25 25 80 80 2500 2500 2500
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM POST-PLATE N / A for Pkg Type A42 A42 N / A for Pkg Type N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 5
www.ti.com
30-Jul-2011
Orderable Device TLV2773CDRG4 TLV2773IDGSR TLV2773IDGSRG4 TLV2773IDR TLV2773IDRG4 TLV2773IN TLV2773INE4 TLV2774AID TLV2774AIDG4 TLV2774AIDR TLV2774AIDRG4 TLV2774AIN TLV2774AINE4 TLV2774AIPW TLV2774AIPWG4 TLV2774CD TLV2774CDG4 TLV2774CDR TLV2774CDRG4 TLV2774CN
Status
(1)
Package Type Package Drawing SOIC MSOP MSOP SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP SOIC SOIC SOIC SOIC PDIP D DGS DGS D D N N D D D D N N PW PW D D D D N
Pins 14 10 10 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
Package Qty 2500 2500 2500 2500 2500 25 25 50 50 2500 2500 25 25 90 90 50 50 2500 2500 25
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type
Addendum-Page 6
www.ti.com
30-Jul-2011
Orderable Device TLV2774CNE4 TLV2774CPW TLV2774CPWG4 TLV2774CPWR TLV2774CPWRG4 TLV2774ID TLV2774IDG4 TLV2774IDR TLV2774IDRG4 TLV2774IN TLV2774INE4 TLV2774IPW TLV2774IPWG4 TLV2774IPWR TLV2774IPWRG4 TLV2775AIN TLV2775AINE4 TLV2775AIPW TLV2775AIPWG4 TLV2775CD
Status
(1)
Package Type Package Drawing PDIP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP TSSOP TSSOP PDIP PDIP TSSOP TSSOP SOIC N PW PW PW PW D D D D N N PW PW PW PW N N PW PW D
Pins 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 16 16 16 16 16
Package Qty 25 90 90 2000 2000 50 50 2500 2500 25 25 90 90 2000 2000 25 25 90 90 40
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 7
www.ti.com
30-Jul-2011
Orderable Device TLV2775CDG4 TLV2775CN TLV2775CNE4 TLV2775ID TLV2775IDG4 TLV2775IDR TLV2775IDRG4 TLV2775IN TLV2775INE4 TLV2775IPWR TLV2775IPWRG4
Status
(1)
Package Type Package Drawing SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP TSSOP TSSOP D N N D D D D N N PW PW
Pins 16 16 16 16 16 16 16 16 16 16 16
Package Qty 40 25 25 40 40 2500 2500 25 25 2000 2000
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 8
www.ti.com
30-Jul-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2771, TLV2772, TLV2772A, TLV2772AM, TLV2772M, TLV2774, TLV2774A :
Catalog: TLV2772A, TLV2772 Automotive: TLV2771-Q1, TLV2772-Q1, TLV2772A-Q1, TLV2772A-Q1, TLV2772-Q1 Enhanced Product: TLV2772A-EP, TLV2772A-EP, TLV2774-EP, TLV2774A-EP Military: TLV2772M, TLV2772AM
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Enhanced Product - Supports Defense, Aerospace and Medical Applications Military - QML certified for Military and Defense Applications
Addendum-Page 9
PACKAGE MATERIALS INFORMATION

www.ti.com 29-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing SOIC MSOP SOIC SOIC SOT-23 SOT-23 SOT-23 SOIC SOT-23 SOT-23 SOIC SOIC SOIC TSSOP MSOP SOIC MSOP SOIC D DGK D D DBV DBV DBV D DBV DBV D D D PW DGK D DGK D 8 8 8 8 5 5 5 8 5 5 8 8 8 8 8 8 8 8
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 180.0 178.0 178.0 330.0 178.0 178.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 12.4 12.4 12.4 12.4 9.0 9.0 9.0 12.4 9.0 9.0 12.4 12.4 12.4 12.4 12.4 12.4 12.4 12.4 6.4 5.3 6.4 6.4 3.15 3.23 3.23 6.4 3.23 3.23 6.4 6.4 6.4 7.0 5.3 6.4 5.3 6.4
B0 (mm) 5.2 3.4 5.2 5.2 3.2 3.17 3.17 5.2 3.17 3.17 5.2 5.2 5.2 3.6 3.4 5.2 3.4 5.2
K0 (mm) 2.1 1.4 2.1 2.1 1.4 1.37 1.37 2.1 1.37 1.37 2.1 2.1 2.1 1.6 1.4 2.1 1.4 2.1
P1 (mm) 8.0 8.0 8.0 8.0 4.0 4.0 4.0 8.0 4.0 4.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
W Pin1 (mm) Quadrant 12.0 12.0 12.0 12.0 8.0 8.0 8.0 12.0 8.0 8.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 Q1 Q1 Q1 Q1 Q3 Q3 Q3 Q1 Q3 Q3 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1
TLV2770CDR TLV2770IDGKR TLV2770IDR TLV2771AIDR TLV2771CDBVR TLV2771CDBVR TLV2771CDBVT TLV2771CDR TLV2771IDBVR TLV2771IDBVT TLV2771IDR TLV2772AIDR TLV2772AMDR TLV2772AQPWR TLV2772CDGKR TLV2772CDR TLV2772IDGKR TLV2772IDR
2500 2500 2500 2500 3000 3000 250 2500 3000 250 2500 2500 2500 2000 2500 2500 2500 2500
Pack Materials-Page 1

Device
Package Package Pins Type Drawing SOIC TSSOP MSOP SOIC MSOP SOIC SOIC SOIC TSSOP SOIC TSSOP SOIC TSSOP D PW DGS D DGS D D D PW D PW D PW 8 8 10 14 10 14 14 14 14 14 14 16 16
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 12.4 12.4 12.4 16.4 12.4 16.4 16.4 16.4 12.4 16.4 12.4 16.4 12.4 6.4 7.0 5.3 6.5 5.3 6.5 6.5 6.5 6.9 6.5 6.9 6.5 6.9
B0 (mm) 5.2 3.6 3.4 9.0 3.4 9.0 9.0 9.0 5.6 9.0 5.6 10.3 5.6
K0 (mm) 2.1 1.6 1.4 2.1 1.4 2.1 2.1 2.1 1.6 2.1 1.6 2.1 1.6
P1 (mm) 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
W Pin1 (mm) Quadrant 12.0 12.0 12.0 16.0 12.0 16.0 16.0 16.0 12.0 16.0 12.0 16.0 12.0 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1
TLV2772MDR TLV2772QPWR TLV2773CDGSR TLV2773CDR TLV2773IDGSR TLV2773IDR TLV2774AIDR TLV2774CDR TLV2774CPWR TLV2774IDR TLV2774IPWR TLV2775IDR TLV2775IPWR
2500 2000 2500 2500 2500 2500 2500 2500 2000 2500 2000 2500 2000
*All dimensions are nominal
Device TLV2770CDR TLV2770IDGKR TLV2770IDR TLV2771AIDR
Package Type SOIC MSOP SOIC SOIC
Package Drawing D DGK D D
Pins 8 8 8 8
SPQ 2500 2500 2500 2500
Length (mm) 340.5 358.0 340.5 340.5
Width (mm) 338.1 335.0 338.1 338.1
Height (mm) 20.6 35.0 20.6 20.6

Device TLV2771CDBVR TLV2771CDBVR TLV2771CDBVT TLV2771CDR TLV2771IDBVR TLV2771IDBVT TLV2771IDR TLV2772AIDR TLV2772AMDR TLV2772AQPWR TLV2772CDGKR TLV2772CDR TLV2772IDGKR TLV2772IDR TLV2772MDR TLV2772QPWR TLV2773CDGSR TLV2773CDR TLV2773IDGSR TLV2773IDR TLV2774AIDR TLV2774CDR TLV2774CPWR TLV2774IDR TLV2774IPWR TLV2775IDR TLV2775IPWR
Package Type SOT-23 SOT-23 SOT-23 SOIC SOT-23 SOT-23 SOIC SOIC SOIC TSSOP MSOP SOIC MSOP SOIC SOIC TSSOP MSOP SOIC MSOP SOIC SOIC SOIC TSSOP SOIC TSSOP SOIC TSSOP
Package Drawing DBV DBV DBV D DBV DBV D D D PW DGK D DGK D D PW DGS D DGS D D D PW D PW D PW
Pins 5 5 5 8 5 5 8 8 8 8 8 8 8 8 8 8 10 14 10 14 14 14 14 14 14 16 16
SPQ 3000 3000 250 2500 3000 250 2500 2500 2500 2000 2500 2500 2500 2500 2500 2000 2500 2500 2500 2500 2500 2500 2000 2500 2000 2500 2000
Length (mm) 182.0 180.0 180.0 340.5 180.0 180.0 340.5 340.5 346.0 346.0 358.0 340.5 358.0 340.5 346.0 346.0 358.0 346.0 358.0 346.0 346.0 346.0 346.0 346.0 346.0 346.0 346.0
Width (mm) 182.0 180.0 180.0 338.1 180.0 180.0 338.1 338.1 346.0 346.0 335.0 338.1 335.0 338.1 346.0 346.0 335.0 346.0 335.0 346.0 346.0 346.0 346.0 346.0 346.0 346.0 346.0
Height (mm) 20.0 18.0 18.0 20.6 18.0 18.0 20.6 20.6 29.0 29.0 35.0 20.6 35.0 20.6 29.0 29.0 35.0 33.0 35.0 33.0 33.0 33.0 29.0 33.0 29.0 33.0 29.0
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE
0.280 (7,11) 0.245 (6,22)
4 0.065 (1,65) 0.045 (1,14)
0.063 (1,60) 0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)
015
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee Solutions www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Applications Communications and Telecom www.ti.com/communications Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Transportation and Automotive Video and Imaging Wireless www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/automotive www.ti.com/video www.ti.com/wireless-apps
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TLV 2771

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TLV277x, TLV277xA FAMILY OF 2.

All specifications measured at 5 V.

Copyright 19982004, Texas Instruments Incorporated

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

TLV277x PACKAGE PINOUT

NC 1OUT NC VDD+ NC NC 2OUT NC 2IN NC

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

SHDN VDD OUT NC

TLV2772 D, DGK, JG, P, OR PW PACKAGE (TOP VIEW)

TLV2772M AND TLV2772AM U PACKAGE (TOP VIEW)

TLV2773 DGS PACKAGE (TOP VIEW)

1OUT 1IN 1IN + GND

VDD 2OUT 2IN 2IN+

NC 1OUT 1IN 1IN + GND

NC VDD + 2OUT 2IN 2IN +

1OUT 1IN 1IN+ GND 1SHDN

VDD 2OUT 2IN 2IN+ 2SHDN

TLV2773 D OR N PACKAGE (TOP VIEW)

TLV2774 D, N, OR PW PACKAGE (TOP VIEW)

TLV2775 D, N, OR PW PACKAGE (TOP VIEW)

1OUT 1IN 1IN+ GND NC 1SHDN NC

VDD 2OUT 2IN 2IN+ NC 2SHDN NC

1OUT 1IN 1IN+ VDD 2IN+ 2IN 2OUT

4OUT 4IN 4IN+ GND 3IN+ 3IN 3OUT

1OUT 1IN 1IN+ VDD 2IN+ 2IN 2OUT 1/2SHDN

4OUT 4IN 4IN+ GND 3IN + 3IN 3OUT 3/4SHDN

TYPICAL PIN 1 INDICATORS

Pin 1 Printed or Molded Dot

Pin 1 Bevel Edges

Pin 1 Molded U Shape

recommended operating conditions

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

Total harmonic distortion plus noise

Phase margin at unity gain Gain margin

Full range is 0C to 70C.

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

Total harmonic distortion plus noise

Phase margin at unity gain Gain margin

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

Low-level output voltage

AVD ri(d) ci(c) zo

Common-mode rejection ratio

Full range is 40C to 125C.

Phase margin at unity gain

Gain margin Full range is 40C to 125C.

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

VIC = 0, VO = 0, , RS = 50 , VDD = 2.5 V 2.5

Low-level output voltage

AVD ri(d) ci(c) zo

Common-mode rejection ratio

Full range is 40C to 125C.

operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

Full range is 40C to 125C.

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

AVD ri(d) ci(c) zo CMRR

Phase margin at unity gain

SLOS209G JANUARY 1998 REVISED FEBRUARY 2004

VDD = 2.5 V, VIC = 0,

AVD ri(d) ci(c) zo CMRR

operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)

Phase margin at unity gain