Code No: R7310404 III B.Tech.

I Semester(R07) Regular Examinations, DIGITAL IC APPLICATIONS

(Electronics & Communication

[]] December 2009

Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks

Max Marks: 80

;Q

*****
(a) Design CMOS transistor

circuit for 2-input AND gate. Explain the circuit with the help

of function table.VI (b) Explain the following terms with reference to CMOS 10gic.l/1 Logic levels. n. Noise margin. iii. Power supply rails. IV. Propagation delay.
I.
r

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'I

(a) Design a TTL three-state table.

J1

NAND gate and explain the operation with the help offunction

(b) Explain the terms: i. Noise margin. ii. Fan-out with reference to TTL. (c) Explain sinking current and sourcing current of TTL out. Which of the parameters the fan-out and how? ITJ (a) \\'rite a VHDL Entity and Architecture for a 3-bit synchronous decide

counter using Flip-Flops.

(b) Discuss different delays and concept of packages in VHDL.~

(a) Design a logic circuit to detect prime number of a 4-bit input. Write the VHDL program
for the same in structure style of modeling.

V1

(b) Design the logic circuit and write a data flow style VHD":'program function: / F(A) = fTp,q,r,s(l, 3, 4, 5, 6, 7, 9,12,13, 14y/{
H

for the following

J/

({)

(a) Explain the working of 3:8 Decoder and write VHDL code using CASE statement.'.A (b) Realize the following expression using 74 x 151 IC f(y)=AB+BC+AC.

VJ

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7. ~

(a) Implement 4-bit Ripple Adder using 1 bit Full Adder and write VHDL code for this inlplementation. (b) Design a 16 bit comparator using 74 x 85 ICs.v11

(a) Discuss the logic circuit of 74 x 377 register. structural style.

Vl

Write a VHDL program

for the same in

(b) Design a modulo-60 counter using 74x 163 ICs.V\ (a) Discuss how PROM, EPROM and EEPROM technologies differ from each other. ,/} from the first

(b) Design an 8 x 8 diode ROM using 74 x 138 for the following data starting location. 44,22,33,FF,DD,CC,0l,7E.

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Code No: R7310404 III B.Tech. I Semester(R07) Regular Examinations, DIGITAL IC APPLICATIONS
(Electronics & Communication

rn
December 2009
Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks

Max Marks: 80

*****
1. (a) What is the difference between Transmission Time and Propagation two parameters with reference to CMOS logic. t/l Delay? Explain these

(b) Draw the resistive model of a CMOS inverter circuit and explain its behavior for LOW alld HIGH outputs. c/J 2. (a) Draw the circuit diagram of two-input 10K ECL OR gate and explain its operation.

(b) Explain the terms DC noise margin (ii) Fan-out with reference to TTL gate. (c) A single pull-up resistor to +5V is used to provide a constant-l logic source to 15 different 74LSOO inputs. What is the maximum value of this resistor? How much high state dc noise margin can be provided in this case. 3. (a) Draw the design flow of VHDL and explain each block. (b) Explain the use of packages. Give the syntax and structure of a package in VHDL.

4. Design the logic circuit and write a data-flow style VHDL program for the following functions,. (a) F(A) (b) F(X) 5.
=

TI

1J,(7,T!S

(1,3,4,5,6,7,9,12,13,14).

I:A,B,C,D(3, 5, 6, 7,13) + d(l, 2, 4,12,15).

(a) Implement 4-bit Ripple Adder using I-bit Full Adder and write VHDL code for this implementation. (b) Using two 74 x 138 decoders design a4 to 16 decoders.

6.

(a) Design a 16-bit comparator (b) Write a behavioral

using 74 x 85 ICs.

VHDL program to compare 16-bit signed and unsigned integers. register.

7.

(a) Write VHDL code for 4-bit serial-In Parallel-out

(b) Design a modulo-IOO counter using 74 x 163 binary counter. 8. (a) Explain the necessity of two-dimensional decoding mechanism transistor memory in ROM and explain the opetation. in memories. Draw MOS

(b) Discuss how PROM, EPROM and EEPROM technologies differ from each other.

III B.Tech. I Semester(R07) Regular Examinations, DIGITAL Ie APPLICATIONS

(Electronics & Communication

December 2009

Engineering)

Time: 3 hours Answer any FIVE questions All questions carry equal marks

Max Marks: 80

*****
1.

(i) Explain
CPr

how to estimate output of CMOS gateVl

sinking current for low output

and sourcing current

for high

Explain the following terms with reference to CMOS 10gic.V]

i. Logic levels.

ii. Noise margin. iii. Propagation iv. Transmission 2. delay. time. logic? Draw the circuit of Tri-state TTL logic and explain its

~~rhat is meant by Tri-state functions. ~lVJcntion

the DC noise margin levels of ECL lOj{" family. of VHDL and any other procedural language.

(wExplain the difference in program structure Give an example.

(bi What are the various types of objects in VHDL and explain?
(cy Briefly explain about different delays in VHDL. ('Explain structural design elements of VHDL. for the following

(b);esign the logic circuit and write a data-flow style VHDL program function. F(X) = l:A,B,C,D(3, 5, 6, 7,10,13,14) + d(l, 2, 4,15).

5fDesign a 3 input 5-bit multiplexer. Write the truth table and draw the logic diagram. the data flow VHDL program for the same. 6./(80) Design a 16-bit comparator using 74 x 85 ICs.

Provide

(b) Write a behavioral VHDL program to compare 16-bit signed and unsigned integers. 7.

<fa)

Explain the difference between D-Latch and D-Flip flop using the process block in VHDL.

)15f vVrite VHDL code for 4-bit serial-In parallel-Out register.

8. (a) Realize the logic function performed by 74 x 381 with ROM. (b) How many ROM bits are required to build a 16 bit adder/subtractor trol, carry input, carry output and two's complement overflow out-put? scbematic with all inputs and outputs. with mode conShow the block