Overview Chapter 6 Part B

Combinational Logic Functions Decoder Encoder Multiplexer Demultiplexer Magnitude Comparator Parity Generator and Checker

Encoders
Encoder: A digital circuit that generates a specific code at its outputs in response to one or more active inputs. It is complementary in function to a decoder. Output codes are usually Binary or BCD.
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Priority Encoders
Priority Encoder: An encoder that generates a code based on the highestpriority input. For example, if input D3 = input D5, then the output is 101, not 011. D5 has a higher priority than D3 and the output will respond accordingly.
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8-to-3 Encoder Truth Table

Active - HIGH Inputs D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 Q2 Q1 Q0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Priority Encoder Equations

Q2 = D7 + D6 + D5 + D4 Q1 = D7 + D6 + D5 D4 D3 + D5 D4 D2 Q0 = D7 + D6 D5 + D6 D4 D3 + D6 D4 D2 D1

Priority Encoder VHDL Entity

-- hi_pri8a.vhd ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR (7 downto 0); q : OUT BIT_VECTOR (2 downto 0)); END hi_pri8a;

Priority Encoder VHDL Architecture

ARCHITECTURE a OF hi_pri8a IS BEGIN -- Concurrent Signal Assignments q(2) <= d(7) or d(6) or d(5) or d(4); q(1) <= d(7) or d(6) or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2)); -- in a similar fashion

q(0) END a;

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Another VHDL Encoder 1

-- hi_pri8b.vhd ENTITY hi_pri8a IS PORT( d : IN BIT_VECTOR (7 downto 0); q : OUT INTEGER RANGE 0 TO 7); END hi_pri8b;

Another VHDL Encoder 2

ARCHITECTURE a OF hi_pri8b IS BEGIN encoder; q <= 7 WHEN d(7) = 1 ELSE 6 WHEN d(6) = 1 ELSE 5 WHEN d(5) = 1 ELSE 4 WHEN d(4) = 1 ELSE 3 WHEN d(3) = 1 ELSE 2 WHEN d(2) = 1 ELSE 1 WHEN d(1) = 1 ELSE 0; END a;
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Basic Multiplexers (MUX)

(MUX): A digital circuit that directs one of several inputs to a single output based on the state of several select inputs. A MUX is called a m-to-1 MUX. A MUX with n select inputs will require m = 2n data inputs (e.g., a 4-to-1 MUX requires 2 select inputs S1 and S0).
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Basic Multiplexers (MUX)

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Basic Multiplexers (MUX)

4-to-1 Multiplexers Truth Table

S1 0 0 1 1
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S0 0 1 0 1

Y D0 D1 D2 D3
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Multiplexer Logic
Boolean expression for a 4-to-1 MUX is Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0 This expression can be expanded to any size MUX so the VHDL architecture could use a very long concurrent Boolean statement.

Double Subscript Notation

Naming convention in which variables are bundled in numerically related groups, the elements of which are themselves numbered. The first subscript identifies the group that a variable belongs to (D01, D00). The second subscript indicates which element of the group a variable represents.

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Truth Table for a 4-to-1 4-bit Bus MUX

S1
0 0 1 1

Truth Table for a 4-to-1 4-bit Bus MUX

S0
0 1 0 1

Y3 Y2 Y1 Y0 D03 D02 D01 D00 D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
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VHDL Constructs For MUXs

The following three VHDL constructs can be used to describe the Multiplexer:
Concurrent Signal Assignment Statement Select Signal Assignment Statement CASE Statement

PROCESS and Sensitivity List

PROCESS: A VHDL construct that contains statements that are executed if a signal in its sensitivity list changes. Sensitivity list: A list of signals in a PROCESS statement that are monitored to determine whether the Process should be executed. process_label: PROCESS (signal1, signal2, signal3) BEGIN -- Process Code Goes Here END PROCESS process_label;
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Case Statement
A case statement is a sequential VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.
CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE;

MUX 4-to-1 VHDL 1

Process and Case statements combined to implement Multiplexer Basic Entity declaration for a 4-to-1 MUX:
ENTITY mux4case IS PORT( d0, d1, d2, d3 : IN BIT; s : IN BIT_VECTOR (1 downto 0); y : OUT BIT); END mux4case;

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MUX 4-to-1 VHDL 2

ARCHITECTURE mux4to1 OF mux4case IS BEGIN -- Monitor select inputs and execute if they change PROCESS(s) BEGIN CASE s IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" WHEN others END CASE; END PROCESS; END mux4to1; => => => => => y y y y y <= <= <= <= <= d0; d1; d2; d3; '0';

Board Work
Modify the VHDL from the previous example to implement a 8-to-1 mux. Implement the following truth table using a 4-to-1 mux:
AB 00 01 10 11
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Z 0 1 0 1
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Homework
Chapter 6
16 18 20 24 25 (BCD Priority Encoder) a (BCD Priority Encoder) (Multiplexer) (Multiplexer Truth table) a (Multiplexer VHDL)

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