UNIVERSITY OF SOUTHAMPTON

Design of CMOS OpAmp for a D/A Converter Buffer

MSc Design Assignment
Manraj Singh Gujral msg1g10 16th May 2011

Contents
1. 2. 3. i. ii. iii. 1. iv. v. vi. 4. 5. 6. 7. Introduction .................................................................................................................................... 2 Hand Calculations ........................................................................................................................... 2 Circuit Simulation ............................................................................................................................ 8 AC Analysis Small Signal: ............................................................................................................. 8 DC Sweep Simulation: ................................................................................................................. 8 AC small signal Gain/Phase Simulation Set-up vs. Common Model Level ............................... 9 Modifications .......................................................................................................................... 9 Large Signal Step Response simulation................................................................................. 11 Large Signal Sine Full Power Bandwidth Simulation ................................................................. 13 Slew Rate Simulation ............................................................................................................ 14 Result ............................................................................................................................................ 16 Conclusion ..................................................................................................................................... 16 References .................................................................................................................................... 16 Appendix: ...................................................................................................................................... 17 Test 1 ................................................................................................................................................. 17 Test 2 ................................................................................................................................................. 17 Test 3 ................................................................................................................................................. 18 Test 4 ................................................................................................................................................. 19 Test 5 ................................................................................................................................................. 20 TABLE for HAND CALCULATION PROCESS PARAMETERS .................................................................. 20 Body connections Connected to VDD for the Differential Pair PMOS .............................................. 21 Ac Analysis of OpAmp with Bulk connected to Vdd (Std NWell Process) ......................................... 21

1. INTRODUCTION This report describes the design process of a simple CMOS OpAmp with specified parameters. The Design is carried out in 0.35m N-Well Process. The Specifications of the Design are as shown in the Table below:
Table1 : A list of specifications Parameter Power Supply, VDD VSS Input Signal Range App. Mode Gain Output Range Output Load Conditions DC Gain Full power Bandwidth Phase Margin Settling Time Bias Current Value 3.3V 0V 0.2V to 1.2V x 2 non-inverting mode using 10k 0.4V - 2.4V Capacitance of 0 to 30pF Resistance : 10k to infinity > 60dB (with all specified loads)with input common mode of 0.2V to 1.2V > 100kHz at 2V p-p > 45deg within 1% of final value within 500ns with less than 15% overshoot 25A

The report accompanies a list of items in Appendix. Appendix contains the MOS Parameter Sheet that was used for calculations. The Test circuits, those were specified in the specification sheet, have been listed in the Appendix to avoid duplication they whereas their waveforms form a part of the main body of Report.

2. HAND CALCULATIONS For this exercise we will employ the use of a 2 stage OpAmp.

Fig. 1 : A 2-Stage OpAmp model which gives an advantage by Better output voltage swing and Compensation[1]

It can be shown from the transfer function of an OpAmp that 0.22 - for a Phase Margin of atleast 60o [2]

= 0.22 30 10 = 6.6 5.85 o 60 but atleast better than 45o .

. ) - Since we do not need a phase margin of

Fig. 2: (a) 2-Stage Op-amp circuit (b) equivalent small signal model [1]

i.e, for

1 6

6+ 6 ,

6 =

= 1 , i.e, unity Gain Bandwidth, we have = 1 , , 2

- Eqn. (1)

Degrees

Fig. 3: Bode Plot as per the Specifications

From the bode plot of the specification as shown in figure 3 , we assume a single pole drop of 20dB/Dec from 40dB at 100 kHz to arrive at unity gain frequency of about 10 MHz. Also at this point the Phase margin required should be more than 45O. Therefore we substitute, f = 10MHz in Eqn. (1). 2 10 10 5.85 10 1 = 4 10 = 1 Eqn. (2)

=gm2

It is specified that the OpAmp should have full power bandwidth greater than 100 kHz at 2V peak to peak. i.e., we can find out Slew Rate, as Therefore, 1.25 V/s.

. Where time is nothing but 1/frequency

We improve the Slew Rate of our design, and take SR = 5 V/s (assumption) Since, SR = ITAIL / CLoad

5 10 =

= 150 106

30 10

Therefore with a Tail Current of 150A, we use the Trans-conductance formula to calculate the W/L of the MOS 1, as represented in Figure 2. (a) We know that for a MOS device in Saturation, = 2

=
Assuming a Tail Current, ITAIL = 150A and get
=

Eqn. (3) [1]

50 x 106 A/V2 , n (at VBS=0V) = 1.33 for PMOS, we

= 28.29

Eqn. (4)

According to the specifications the Inputs to the OpAmp are in the range of Vmin = 0.2V, and V max =1.2V We need to ensure that none of the MOS transistors in the first stage goes into the Triode Region in this range of input voltages. It is critical that we look at the various voltage w.r.t Gate, Source and Drain terminals for P- and N-MOS devices.

+ + G D

+ G

D Vth

(1) In Triode Region

(2) At the Edge of Triode Region (a) PMOS Regions

(2) In Saturation Region

+G D

Vth D

+
G

(1) In Triode Region

(2) At the Edge of Triode Region (a) NMOS Regions

(3) In Saturation Region

Fig. 4: Conceptual Visualization of voltage references in Saturation & Triode Regions for PMOS and NMOS [3]

It is not readily straight forward when we try to write the Triode-Saturation boundary voltage equations for POMS and NMOS. In our Amplifier we have PMOS in our differential pair (M1 and M2, ref figure 2. (a)) and the current mirrors are made from NMOS (M3 and M5). We would need to revisit this figure 4 when taking in terms of VSG , i.e., Voltage of Source w.r.t Gate, and VGD ,i.e., Voltage of Gate w.r.t Drain, when solving for Vmax and Vmin. Please note that , for example, in an NMOS the voltage at Drain is higher than the Source voltage even though both are labelled as negative (-). and + signs are for representation purpose only attempting to explain the relationship between Gate and Source potential in terms of magnitude. First we attempt to study the effect of Vmin on the Current mirrors, M3 and M4.
Vdd M5 Vdd

Vbias Vsg Vmax

Vsd

M1

M3 Vss (a)

Fig. 5: Vmax and Vmin of the input voltage and its effect on the 1 Stage (Neglecting Back Gate effects in M1 (and M2: its pair) since it is connected to Source)

Vsd across M5 will be low and the device might slip into Triode region of Operation

Vbias

M5

Vsd

Vmin Vgd Vsd across M3 will be low and the device might slip into Triode region of Operation

M1

{ M3
Vgs (b)
st

M4 Vss

When minimum voltage is applied at the input, it should be over VSS by the amount as = = +
( ) ( )

+
( ) |

Eqn. (5)

At the edge of the saturation region (and also from figure 4) we know that |

VT(n) is the Threshold voltage of the NMOS. We have assumed that the bulk and the source terminals of both NMOS and PMOS are connected to their resp. source terminals, and therefore no body effect comes into play. Also VGD is the potential difference between Gate and Drain terminals of PMOS M1. Analysing the PMOS at the edge of saturation region in figure 4, we modify Equation (5) as = = + ( +
( )

( )

)+(

( )

( )

Eqn. (6)

It is assumed that the Back Gate effect on Threshold voltage is zero. Although it is a standard 0.35m N-Well Process, but the Bulk is connected to the Source for calculation purpose. Substituting the Values of Vmin = 0.2 V, IDS1= ITAIL/2 , and remaining values from the Hand Calculations Process Parameters Chart, attached in the Appendix, we get the values of W/L of the Current mirror NMOS as
,

= 11.08

( ( ) )

Eqn. (7)

Similarly for maximum value of input voltage we can write the equation as =
( ( ( ) ) )

( )

( )

Eqn. (8)

Substituting the values for VDD = 3.3V , IDS1= ITAIL /2 and from the given Hand Calculations Process Parameters Chart, we find that = 11.08 Now, = 2.2 = 2.2 4 10 .22 Eqn. (10) [2]

Eqn. (9)

6 ,

4.52

10 =

Eqn. (11)

99.89

Eqn. (12)

6 3

= 6.75 10

25.76

Eqn. (13)

Fig.6: Op-Amp Circuit designed with the following parameters: W/L (1,2) = 28 W/L (3,4) = 11 W/L (5) = 11 W/L (6) =100 W/L (7) = 27 W/L (8) = 1 Cc = 6pF

3. CIRCUIT SIMULATION
i. AC Analysis Small Signal:

Fig. 7 : Waveform for AC Analysis Small Signal (at DC offset of 0.2V): o 1. Low frequency gain > 62 2. Gain at 100kHz 43dB o 3. Phase Margin > 54

ii.

DC Sweep Simulation:

Fig.8 : Waveform for DC sweep simulation

iii.

AC small signal Gain/Phase Simulation Set-up vs. Common Model Level

Fig.9 : Waveform for AC small signal Gain/Phase Simulation Set-up vs. Common Model Level o 1. Low frequency gain at Dc offset 0.2V 48 o 2. Low frequency gain at Dc offset 1.2V 57

Clearly, the Low frequency Gain at low DC offset is not as per the requirement. Although the specification requiring 40dB at 100 kHz is achieved. 1. Modifications Therefore certain changes were made to increase the gain. 1. Tail current in Stage-I was reduced by lowering the W/L ratio to increase the overall output gain. 2. M6 Transistor size was increased. 3. Compensation Capacitance, Cc, lowered from 5.8pF to 4.5pF to maintain the 40dB at 100 kHz. Please note that these changes were made iteratively by re-plotting the waveforms after small (delta) changes- parametric sweep of M6 Transistor keep all other values constant. The final values of the W/L of Tail Current MOS (M3) and the output stage M6 to achieve a low frequency gain of at least 60dB are shown in Fig.10

Fig.10 : Re-Calculated Op-Amp parameters. The Changes made are: 1. W/L of M6 = 400 2. W/L of M5 = 3

Fig.11 : Waveform for the recalculated OpAmp in AC small signal Gain/Phase Simulation Set-up vs. Common Model Level o 1. Low frequency gain at Dc offset 0.2V > 60 o 2. Gain at 100kHz 40 o o 3. Phase margin of 71 (at DC offset of 0.2V) and 60 (at DC offset of 1.2V)

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Fig.12: Waveform for DC sweep simulation for recalculated OpAmp, with intermediate points to show offset Table 2: Offset at various points on the waveform

Input Voltage (mV) Output Voltage(mV) Offset Voltage(mV) 306.771 610.72 9.20E-03 619.271 1235.67 4.64E-03 903.125 1803.29 3.28E-03 Average Offset 5.70E-03
The value of offset is generally very low. If we take an average offset is about .0057 mV in the feedback system.

iv.

Large Signal Step Response simulation

Fig.13: Waveform for Large Signal Step Response simulation

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Fig.14 : Zoomed in view of the Signal Step Response simulation

From the waveform in figure 14, we can calculate the rise time of our OpAmp. Vmax = 2.39659 V Vmin = 1.9974 V Vmax Vmin = 0.39951 Therefore, we calculate the Rise time as the time taken from 10% of the voltage range to 90% of the voltage range. 10% of Voltage range = 2.036V 90% of the Voltage range = 2.356V These values can be seen on the waveform. Rise Time (for the final step) 55.82ns

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v.

Large Signal Sine Full Power Bandwidth Simulation

Fig. 15 : Waveform for Large Signal Sine wave at 10 kHz

Fig.16 : Waveform for Large Signal Sine wave at 100 kHz

(1)

(2)

Fig.17 : Waveform for Large Signal Sine wave at 1MHz

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From the waveform in figure 17, we can observe two important points: 1. The maximum peak of the output is reduced from 2.19V in 10 kHz to 2.18V in 1MHz test. This is due to the AC characteristics of the OpAmp as illustrated in Figure. As the frequency increases the Gain starts to roll off. 2. The Peaks of input voltage and output voltage occur at different time. Vpeak input occurs at 1.252s where as Vpeak output at 1.287s. This is due to the reducing phase margin as we go to higher frequencies. This can also be seen from the AC characteristics in Figure 11

vi.

Slew Rate Simulation

Fig.18 : Circuit to simulate the Slew Rate. R-load = 10k, and Capacitance =10pF

We are driving this circuit a little higher than the required output range for the sake of this test.

Fig.19 : OpAmp being driven to an output of 0.8V to 2.8V.

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Fig. 20: A Zoomed-in view of the rising edge of the output waveform. 90% Vout = 2.712 V , 10%Vout = 1.0091V

Rise time, Tr = 0.6715s

Slew Rate = . . = .

S.R. = 3.46 /

Since we had reduced the Tail Current in the Design Process, therefore our initial calculated Slew Rate of 5 V/ s (approx.) is reduced to 3.46 V/ s.

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4. RESULT
All the design parameters listed in table1 are achieved. The tests and their test circuits (in Appendix) are accompanied by waveforms. Below is the list of values calculated for the OpAmp Parameters. There are deviations from the calculated values and the cause of those is listed in the remarks.
Table 4: A list of Calculated vs. Actual Simulation Values

M1 M2 M3 M4 M5 M6 M7 M8 Cc IBias

Calculated Values 28/1 28/1 11/1 11/1 11/1 100/1 27/1 1/1 5.8pF 25A

Actual Simulation values 28/1 28/1 11/1 11/1 3/1 400/1 27/1 1/1 4.5pF 25A

Remarks To reduce the Tail Current To improve the Gain for Large signal AC Test. To improve the 100kHz Gain value -

5. CONCLUSION
Although a lot of design equations and results match the final calculated values, there still remains the issue of accuracy of calculations and usage of various formulae. In this particular exercise, VBS = 0V. If for the PMOS differential pair, the Body was connected to VDD then the Threshold Voltages would have changed and our design would require different set of values. An AC analysis of Body connected to VDD, with the actual simulated values obtained in Table 4, is simulated and attached in Appendix for reference.

6. REFERENCES
[1] [2] [3] Prof. W Redman-White, Analogue & Mixed Signal CMOS Design, Lecture Notes 2011, Dept. of Electronics & Computer Science, University of Southampton. 2010-11 Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design, 2nd edition.2002 Behzad Razavi , Design of Analog CMOS Integrated Circuits, 17th Reprint, Tata McGraw-Hill Edition 2002.

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7. APPENDIX:
Test 1 OP-AMP BASIC AC (Small Signal) GAIN/PHASE SIMULATION TEST SET-UP
10 1F
_ + Vin: AC - Use AC value of 1V for small signal simualtions VinCM: Put DC source in series to set common mode of input Minimum range 0.2V - 1.2V
10

VSS +3.3V

Vout

RL

VSS 0V

CL

Test 2 OP-AMP DC SWEEP SIMULATION TEST SET-UP

10k 10k
_ + VSS +3.3V

Vout

RL = 10k >

Vin: Sweep DC value to obtain output range

VSS 0V

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Test 3
OP-AMP AC (Small Signal) GAIN/PHASE SIMULATION TEST SET-UP vs COMMON MODE LEVEL
Resistors set DC output level to 2X input DC, but AC gain is open loop due to large capacitor

10

10

10

10

VSS +3.3V

_ +

Vout

RL

100F
Vin: AC - Use AC value of 1V for small signal simualtions VinCM: Put DC source in series to set common mode of input Minimum range 0.2V - 1.2V VSS 0V

CL

RFB = 20k
Loading of feedback resistor network needed for X2 gain added in parallel for open loop gain test

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Test 4
OP-AMP LARGE SIGNAL STEP RESPONSE SIMULATION TEST SET-UP

10k 10k
_ +

VSS +3.3V

Vout

RL

V1
VSS 0V

CL

V2 V3 V4 V5
Vmin DC value 0.2V

V1-5 Pulse sources. Each 1ns rise time, 0V - 0.2V step, Time between edges when added = 1us

V1 V2 V3 V4 V5 t
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Test 5

OP-AMP LARGE SIGNAL SINE FULL POWER BANDWIDTH SIMULATION TEST SET-UP
10k 10k
_ + Vin: Sine 0.5V pk 10kHz, 100kHz 1MHz VinCM: Put DC source in series to set common mode of input at 0.6V VSS +3.3V

Vout

RL

VSS 0V

CL

TABLE for HAND CALCULATION PROCESS PARAMETERS

(Lmin = 0.35m, Vdd max = 3.3V) Parameter N Cox Cox n (at VBS = 0) C CGDo CGSo VTO CDB CSB B P Units

200 50 A/V2 4.3 4.3 fF/2 1.33 1.33 0.3 0.3 V-1 1.75 4.5 V/m 250 250 aF/ 250 250 aF/ -1 0.05/(L 0.1) 0.05/(L 0.1) V 0.6 0.7 V 1.1 1.1 fF/2 Assume Drain & Source area are (0.7xW)2 1.1 1.1 fF/2 1/2 0.4 0.6 V 0.7 0.7 V

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Body connections Connected to VDD for the Differential Pair PMOS

Fig. 21 : OpAmp Circuit showing body connection

Ac Analysis of OpAmp with Bulk connected to Vdd (Std NWell Process)

Fig. 22 : For Bulk Connections connected to VDD for Differential Pair PMOS. The performance degrades. Gain at 0.2V DC offset 29 dB

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